TWI332265B - Liquid crystal display and method for fabricating the same - Google Patents

Liquid crystal display and method for fabricating the same Download PDF

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Publication number
TWI332265B
TWI332265B TW095149352A TW95149352A TWI332265B TW I332265 B TWI332265 B TW I332265B TW 095149352 A TW095149352 A TW 095149352A TW 95149352 A TW95149352 A TW 95149352A TW I332265 B TWI332265 B TW I332265B
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Taiwan
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electrode
film
region
pattern
circuit
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TW095149352A
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Chinese (zh)
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TW200802887A (en
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Young Joo Kim
Seok Woo Lee
Soo Jeong Park
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Lg Display Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136286—Wiring, e.g. gate line, drain line
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/136213—Storage capacitors associated with the pixel electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/124—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1259—Multistep manufacturing methods

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Nonlinear Science (AREA)
  • General Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Mathematical Physics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Optics & Photonics (AREA)
  • Geometry (AREA)
  • Manufacturing & Machinery (AREA)
  • Liquid Crystal (AREA)
  • Thin Film Transistor (AREA)
  • Devices For Indicating Variable Information By Combining Individual Elements (AREA)

Description

1332265 九、發明說明： 【發明所屬之技術領域】 本發明係關於-種液晶顯示裝置及其製造方法，尤豆係關於 -種減少遮罩的數目以簡化製裎步驟且改善產量的液晶顯示裝置 及其製造方法。 【先前技術】 現今的資訊社會中，顯示器作為視覺資訊傳輸媒介的重要性 日益顯著。開發顯示器的關鍵取決於對低功率消耗、外形的薄度、 重量的輕度以及高影響品質的需要。對應於平面齡器㈤興以 display ; FPD)的主體裝置的液晶顯示裝置〇iquidcrystaidispiay ; LCD)可滿足這些需求並且能夠大量生產。因此，廠商已經製造 基於液晶顯示裝置的各種新產品，而且液晶顯示裝置已經廣泛地 被用作替代陰極射線管（cathode ray tube ; CRT)的主要部件。 通裇，液晶顯示裝置依照影像資訊各自供應資料訊號至排列 為矩陣形式的液晶分子，並且控制液晶分子的透光率以顯示需要 的影像。 液晶顯示裝置主要採用主動式矩陣驅動模式，其中非晶矽薄 膜電晶體（amorphous silicon thin film transistor ; a-Si TFT )用作開 關元件以驅動晝素部的液晶。 自從1986年開始，非晶矽薄膜電晶體已經實際用於3吋的液 晶攜帶式電視中，因為英國的1/6(：〇1111^]：在1979年已經奠定了這 6 1332265 個概念。最近，業界已經開發出50吋或者更大的大型薄膜電晶體 液晶頒不裝置。尤其地，業界主動使用非晶矽薄膜電晶體的原因 在於，它能夠實現低溫的製程步驟，從而可以使用低成本的絕緣 基板。 然而，由於非晶矽薄膜電晶體的電子移動性為，因 此在需要大於1百萬赫之高速作業的周邊電路巾受到限制。在這 ^ ae^ (polycrystalline silicon ； poly-Si) 電晶體同時整合晝素部以及驅動電路部於玻璃基板之上，其中多 晶石夕電晶體的場效應移動性高於非㈣_電晶體的場效應移動 性。 自從1982年開發液晶彩色電視以來，多晶石夕電晶體已經被用 於小財賴_如_像機巾。因衫轉電晶體具有低靈敏 度和向場效應移動性的優點，所以可直接地製造驅動電路於基板 之上。 、移動性的增加可改善驅動電路部的作業頻率，其中驅動電路 4決疋了絲畫素的數目。這使得顯示㈣表現更加精細。此外， 因為降低晝素部軌號麵之充電咖可減少偷職的失真， 從而可改善影像品質。 此外’因為多晶㈣膜電晶體可被小於iq伏特的電壓所驅 動，和非祕電晶體的驅動電壓高達25伏特概，具有功率消耗 7 1332265 下面，請參考「第 圖」詳細描述液晶顯示裝置的結構。 示意圖 第1圖」所示料―般液晶顯示裝置結構的平面示意圖， 尤，、疋將驅動電路整合於_基板上之液晶顯示裝置結構的平面 如「第1圖」所不’液晶顯示裝置包含彩色渡光片基板 列基板H)以及職練色_片基板5和陣列_Q之間的液 晶層（圖中未表示）。1332265 IX. Description of the Invention: [Technical Field] The present invention relates to a liquid crystal display device and a method of fabricating the same, and a liquid crystal display device in which the number of masks is reduced to simplify the twisting step and improve the yield And its manufacturing method. [Prior Art] In today's information society, the importance of displays as visual information transmission media is becoming increasingly significant. The key to developing a display depends on the need for low power consumption, thinness of form, light weight, and high impact quality. The liquid crystal display device 〇iquidcrystaidispiay (LCD) corresponding to the main unit of the display device (f) is capable of meeting these needs and can be mass-produced. Therefore, manufacturers have manufactured various new products based on liquid crystal display devices, and liquid crystal display devices have been widely used as main components in place of cathode ray tubes (CRTs). By the way, the liquid crystal display device supplies the data signals to the liquid crystal molecules arranged in a matrix according to the image information, and controls the light transmittance of the liquid crystal molecules to display the desired image. The liquid crystal display device mainly adopts an active matrix driving mode in which an amorphous silicon thin film transistor (a-Si TFT) is used as a switching element to drive the liquid crystal of the halogen portion. Since 1986, amorphous germanium thin film transistors have been used in 3 inch LCD portable TVs because of the British 1/6 (: 〇1111^): in 1979, the concept of 6 1332265 has been laid. Recently The industry has developed a large-scale thin film transistor liquid crystal device of 50 吋 or larger. In particular, the reason why the industry actively uses the amorphous germanium film transistor is that it can realize a low-temperature process step, thereby enabling low-cost use. Insulating substrate. However, due to the electron mobility of the amorphous germanium film transistor, peripheral circuit tapes requiring high-speed operation of more than 1 megahertz are limited. In this case, polycrystalline silicon (poly-silicon) The crystal simultaneously integrates the molybdenum part and the driving circuit part on the glass substrate, wherein the field effect mobility of the polycrystalline silicon crystal is higher than that of the non-fourth crystal. Since the development of the liquid crystal color television in 1982, Polycrystalline crystals have been used in small wealth _ _ like machine wipes. Because the shirt has the advantages of low sensitivity and field effect mobility, it can be directly The driving circuit is fabricated on the substrate. The increase in mobility improves the operating frequency of the driving circuit portion, wherein the driving circuit 4 determines the number of silk pixels. This makes the display (4) more fine. In addition, because the halogen portion is lowered The charging of the track number can reduce the distortion of the stealing, which can improve the image quality. In addition, because the polycrystalline (tetra) film transistor can be driven by a voltage less than iq volts, and the driving voltage of the non-myster crystal is as high as 25 volts. With power consumption 7 1332265 Below, please refer to "Figure" for a detailed description of the structure of the liquid crystal display device. Fig. 1 is a plan view showing the structure of the general liquid crystal display device, in particular, the driving circuit is integrated in _ The plane of the liquid crystal display device structure on the substrate is as shown in FIG. 1 'the liquid crystal display device includes the color light-emitting substrate substrate substrate H) and the liquid crystal layer between the professional color film substrate 5 and the array_Q (Fig. Not shown in the middle).

陣列基板1G包含晝素部35以及驅動電路部3q，其中晝素部 35係為影像顯示區域’單元晝素以矩_式制於其中，驅動電 路部30包含資料驅動電路31以及閘極驅動電路&，其係沿晝素 部35的邊緣排列。雖然圖中未表示，但是陣列基板ι〇、的=部 35包含複數條閘極線和資料線，以垂直和水平方向排列於陣列基 板10之上以定義複數個晝素區域；薄膜電晶體，形成於問極線和 資料線的交叉部；以及晝素電極，形成於畫素區域中。 每個薄膜電晶翻作關元件，其可施加或者阻擋訊號電壓 到達或者斷财素電極，鼓係為—種制電場控制電流流動之 % 效應電晶體（field effect transistor· ; ΙΈΤ ；)。 陣列基板10的驅動電路部30位於陣列基板1〇的晝素部％ 的邊緣，其中陣列基板1〇比彩色濾光片基板5更加突出。資料驅 動電路31位於突出的陣列基板1〇的長邊，而閉極驅動電路^位 於突出的陣列基板10的短邊。 8 1332265 此時，在細_電路31和閘極驅動電路& 器的互補式金氧半導體 作為轉換 體（comPlementaiy metal 〇xide semKxmductoi·; CMOS )結構的薄膜 ，岭as體驗輕地輪出-輸入 訊現。‘ 互補式金氧半導雜為—種錢轉義構的電路，用 於需要高速訊號處理的驅動電路部之電晶體中，同時需要η通道 薄膜電晶體和ρ通道薄膜電晶體，其速度和密度特徵相當 的 NMOS 和 PMOS。 閘極驅動電路32和資料驅動電路31透過閘極線和資料線將 各自供應掃描訊號和資料訊號至晝素電極。因為閘極驅動電路^ 和資料驅動電路31連接於外部訊號輸人終端（圖中未表示），所 以它烟於親外部職輸人終端控料部訊錄人，並且輸出 訊5虎至晝素電極。 此外，釤色慮光片基板5的晝素部35包含顯示彩色的彩色遽 光片（圖中未表示），以及共同電極（圖中未表示），用作形成於 陣列基板10中之畫素電極的相反電極。 上述方式製造的彩色濾光片基板5以及陣列基板1〇配設有液 晶間隙，從而彼此之間透過間隔物（圖中未表示）而分隔。彩色 濾光片基板5和陣列基板10透過形成於晝素部35邊緣的密封圖 案而彼此接合’以形成液晶顯示裝置面板。此時，彩色濾光片基 板5以及陣列基板10透過形成於彩色濾光片基板5或者陣列基板 9 1332265 10中的接合鍵(bonding key)而彼此接合。 因為上述液晶顯示裝置具有使用多晶矽電晶體之驅動電路， 所以具有極佳的裝置特性、卓越的影像品質、精細度以及低消耗 功率等優點。 然而，因為具有驅動電路的液晶顯示裝置應該配設有形成於 單一基板上的η通道薄膜電晶體以及p通道的薄膜電晶體，所以 其製程步觀僅娜成單類型通道_晶㈣膜電晶體的步驟更 加複雜。 製造包含薄膜電晶_陣列基板時，需要經過數次的光微影 製程。 / 光微影製程包含—―的製程步驟：轉移鮮上印刷的圖案 至沉積有細的基板之切形成需要關形，其中這鹏列的製 程步驟包含光_塗佈、曝光以及顯影製程步驟。這個實例中衣 因為光微影製程減少了產量並且增加了馳電晶體出現缺陷的機 率，從而產生問題。 尤其地’因為被設相形朗案的光麵格昂貴，所以如果 用於製程步驟的光罩數量增加，洛曰日§ —姑班〜 液日日,.s員不裝置的製造成本也將依 照比例而增加。 【發明内容】 因此’本發明的目的在於接祉你、六θ β 仕於钕供一種液晶顯示裝置及其製造方 法，藉由減少光罩的數目以簡仆制1 間化製造製財驟並且提高產量。 :’、、了獲％•本發明的這些目的和其他優點’現對本發明作具體 2和^括性的描述，本發明之―種液晶顯示裝置的製造方法包 =·，定義出晝素部之_電晶體區域的絕緣基板；形成主動 曰於、％緣基板之上以覆蓋晝素部的_電晶體區域形成晝素部 的間電極於絲層之上；在晝素侧電極的兩側，形成晝素部的 源極區域和晝素部的汲極區域於主動層中；職包含第-和第二 接觸孔的保麵於具有晝素部之汲極區域的基板上，其中第一和 第二接觸孔分別曝露出畫素部的源極區域和晝素部的沒極區域； 依序地形成翻導電膜和金屬膜於保護膜之上；以及，選擇性地 姓刻金屬膜和透明導電膜以形成晝素部的源電極圖案/晝素部的 源電極，此晝素部的源電極圖案/晝素部的源電極係依序地沉積 以覆蓋第-接觸孔，並且形隸素部的汲電極_〆晝素部的没 電極’此晝素部峡電極_/畫素部的__依序地沉積以 覆蓋第二接觸孔。 本發明的另一目的在於提供一種液晶顯示裝置，其包含有絕 緣基板，係由晝素部的薄膜電晶體區域所定義；主動層，形成於 基板之上以覆蓋畫素部的薄膜電晶體區域；晝素部的閘電極，形 成於主動層之上；晝素部的源極區域和畫素部的祕區域，形成 於畫素部之閘電極兩_主動層中；包含第_和第二接觸孔的保 護膜，形成於包含晝素部之祕區域的基板上，第—和第二接觸 孔各自曝露出晝素部的源極區域和晝素部的汲極區域；畫素部的 11 1332265 源電極圖案/晝素部的源電極’其係依序地被沉積於保護膜之上 以覆盍第一接觸孔；以及晝素部的汲電極圖案/晝素部的汲電 極，其係依序地被沉積於保護膜之上以覆蓋第二接觸孔。 結合圖式，本發明的前述以及其他目的，徵、方面以及優 點將在本發明的以下詳細描述中更加顯而易見。 【實施方式】 以下將結合®式之實施麟本發_較針财式作詳細說 明。 弟2圖」係為本發明第一實施例之液晶顯示裝置之部分陣 列基板之平面示意圖。尤其地，「第2圖」表科含畫素部之薄膜 電晶體的一個晝素。 …^際的液日日日顯示裝置包含㈣關極線以及Μ條資料線 所形成的ΜχΝ個晝素’其中閘極線交又於資料線，但是為了簡化 _起見’「第2圖」僅以—個晝素之圖式以簡潔描述。 μ圖」所7F本發明第—實施例之陣列基板110包含 • 線叫雜117，以水平和垂直方向湖於卩娜板no 義畫素區域；薄膜電晶體，形成於閘極線116和資料線 、又又部，以及畫錢極118，形成於畫魏域姐連接 用以和彩色遽光片基板（圖中未表示）上的共同電極 一起驅動液晶（圖中未表示）。 薄膜電晶體包含_極121，連接㈣極線‘源電極⑵， 12 連接於貝料線117 ;以及;；及電極123，連接於畫素電極118。薄膜 電：體更包含主動圖案m ’其可使用供應至閘電極m的間極 電壓於源電極122和汲電極123之間形成導電通道。 、，此日寸’第一貫施例之主動圖案124，係由多晶石夕薄膜所形成， 並且主動_ 124,的部分延伸至晝素區域以連接於儲存圖案 咖’其中儲存圖#丨24，，構成第-儲存電容器以及共同線購。 換。之，共同線1〇8形成於畫素區域中，實質上與閘極線Μ方 2相同’並且與其下的儲存財124，，重疊，以藉由介於其中的第 一絕緣膜（®中未表示）而形絲_儲存電容.此時，透過不 同於構成主動_ 124,的多㈣_之鮮製程以進行儲存區掺 雜，而形成第一實施例的儲存圖案124，，。 *源電極122和没電極123透過分別形成於第一絕緣膜和第二 絕緣膜（圖中未表示）中的第一接觸孔HOa和第二接觸孔勵 而電連接至主動圖案124，的源極區域和絲區域。此外，源電極 ^的—部分於—财向上延伸輯成麵線m之-部分，而沒 °卩77則延伸至畫素11域’透過形成於第三絕緣膜（圖 未表不）中的第三接觸孔140c以電連接於晝素電極。 此②電極123部分延伸至畫素區域，並與其下的共 同線重S ’透過介於其巾的第二絕緣臈⑽成第 「以下將結合「第卿第卿第冗圖」、「第则」、 弟3E圖」、「第3F圖」、「第见圖」、「第紐圖」以及「第31 13 1332265 圖」描述上述陣列基板的製程步驟。 「第3A圖」、「第3B圖」、「第3C圖」、「第3D圖」、「第迮 圖」、「第3F圖」、「第3G圖」、「第3H圖」以及「第3i圖」分別 表示沿「第2圖」解陣縣板之贴，線之接賴程步驟之剖面 圖。「第3A圖」、「第3B圖」'「第％圖」、「第3d圖」、「第迮 圖」、「第3F圖」、「第3G圖」、「第班圖」以及「第31圖」示例 性地說日^設有n通道_電晶體的晝素部之陣列基板的製程。 如第3A圖」所不’石夕薄膜形成於例如玻璃的透明絕緣材料 的陣列基板U0之上’然後被結晶以形成多晶_膜。此時，陣 列基板H0由晝素部和電路部（圖中未表示）定義，其中晝素部 被劃分為η通道薄膜電晶體輯以及儲存區域，電路部㈣分為η 通道薄膜電晶體區朗及ρ通道_電晶體區域。紐，钱刻多 晶碎薄膜以形成構成主動圖案和儲存圖案之多晶㈣膜圖案以 (第:道光罩製程）。此時’緩衝層ηι可介於陣列基板叫多 晶矽薄膜圖案124之間。 如「第3B圖」所示，多晶石夕薄膜圖案124被單一光阻遮罩部 分地遮蔽以執行摻雜，從而形成儲存_ m”。被光阻所遮蔽的 多晶石夕__24部分則形成主動圖案124，（第二道光罩製程)。 ，如第3C圖」所不’第—絕緣膜llSa以及第一導電膜依序 二成於物基板11Q的整個表面之上，紐選雜触刻第一 導㈣以形成第-導電膜的閘電極121於主動圖案124，之上，同 於儲存圖帛124”之上（第三道光罩製 時形成第一導電膜的共同線 種）〇 第-導電膜係由低電阻率的不透明導電材料所形成 鋁、1呂合金、鎢、銅、鉻以及銦等，從而形成閘電極⑵和共同 =108。此¥，共同線爾將於晝素區域之内重曼其下的儲 似，，錢過介於其⑽—繼⑽以糊—儲存電^ 第3D圖」所不，第一遮光膜170形成於包含閘電極1?1 ^共同線⑽的基板之上。第—遮光膜m被瞧以遮蔽陣列 土板⑽的整個表面和電路部^通道薄膜電晶體區域，以曝光 通運缚膜電晶祕域。此實例巾，並未將電路部表示出來。铁後， 使用第—遮麵m作為鱗，A量摻_p+離子被植入電路部 ^p通道賴電晶體區域’以形成計源極區域和汲極區域（圖中 未表不）（第四道光罩製程）。 一如「第3E圖」所示，移除第一遮光膜17〇。接下來，形成第 一遮光膜170於包含p+源極區域和汲極區域的基板之上。第二遮 光被圖案化以遮蔽電路部的p通道薄膜電晶體區域、晝素 八路。卩的n通韻膜電晶體_的—部分以及儲存區域。缺後 使用第二遮光膜闕麵罩，錄_n+離子麵人晝素部的 主動圖案m，’其中n+源極區域咖和汲極區域賤形成於佥 素部的主動圖案124,中（第五道光罩製程）。 、里 第3F圖」所不’移除第二遮光膜口〇,，然後輕推雜的 15 1332265 η-離子被植从移除第二遮光膜之卩翔基板nQ的整個表面，從而The array substrate 1G includes a pixel portion 35 and a driving circuit portion 3q. The pixel portion 35 is an image display region. The unit pixel is formed in a matrix, and the driving circuit portion 30 includes a data driving circuit 31 and a gate driving circuit. &, which is arranged along the edge of the elementary portion 35. Although not shown in the drawing, the = portion 35 of the array substrate ι, includes a plurality of gate lines and data lines, arranged vertically and horizontally on the array substrate 10 to define a plurality of halogen regions; a thin film transistor, An intersection formed between the interrogation line and the data line; and a halogen electrode formed in the pixel area. Each thin film is turned into a shut-off element, which can apply or block the signal voltage to reach or break the acid electrode, and the drum is a kind of electric field control current flowing through the field effect transistor (field effect transistor; ΙΈΤ;). The driving circuit portion 30 of the array substrate 10 is located at the edge of the pixel portion % of the array substrate 1 , wherein the array substrate 1 更加 protrudes more than the color filter substrate 5 . The data driving circuit 31 is located on the long side of the protruding array substrate 1'', and the closed-circuit driving circuit is located on the short side of the protruding array substrate 10. 8 1332265 At this time, in the thin _ circuit 31 and the gate thyristor & complement MOS as a conversion body (comPlementaiy metal 〇xide semKxmductoi·; CMOS) structure of the film, Ling as experience light wheel-input News. 'Complementary MOS-semiconductor is a circuit for converting money into a structure, which is used in a transistor of a driver circuit portion requiring high-speed signal processing, and requires an η-channel thin film transistor and a p-channel thin film transistor at a speed and Density characteristics are comparable to NMOS and PMOS. The gate driving circuit 32 and the data driving circuit 31 supply respective scanning signals and data signals to the pixel electrodes through the gate lines and the data lines. Because the gate driving circuit ^ and the data driving circuit 31 are connected to the external signal input terminal (not shown), it is smoked in the externally-invested terminal control unit, and the output is 5 electrode. Further, the halogen portion 35 of the enamel light-receiving sheet substrate 5 includes a color light-emitting sheet (not shown) for displaying color, and a common electrode (not shown) for use as a pixel formed in the array substrate 10. The opposite electrode of the electrode. The color filter substrate 5 and the array substrate 1 manufactured in the above manner are provided with liquid crystal gaps, and are separated from each other by a spacer (not shown). The color filter substrate 5 and the array substrate 10 are bonded to each other through a sealing pattern formed on the edge of the element portion 35 to form a liquid crystal display device panel. At this time, the color filter substrate 5 and the array substrate 10 are bonded to each other through a bonding key formed in the color filter substrate 5 or the array substrate 9 1332265 10 . Since the above liquid crystal display device has a driving circuit using a polycrystalline silicon transistor, it has excellent device characteristics, excellent image quality, fineness, and low power consumption. However, since the liquid crystal display device having the driving circuit should be provided with an n-channel thin film transistor formed on a single substrate and a p-channel thin film transistor, the process step is only a single type channel-crystal (four) film transistor. The steps are more complicated. When manufacturing a thin film transistor-array substrate, it is necessary to pass several photolithography processes. / Photolithography process includes - a process step: transferring the freshly printed pattern to the deposition of a thin substrate to be formed into a shape, wherein the process steps of the process include photo-coating, exposure, and development process steps. This example has a problem because the photolithography process reduces the yield and increases the probability of defects in the chirping crystal. In particular, 'because the glossy surface of the set-up case is expensive, if the number of masks used for the process steps increases, the manufacturing cost of the equipment will not be the same as the day of the day. Increase in proportion. SUMMARY OF THE INVENTION Therefore, the object of the present invention is to provide you with a liquid crystal display device and a method for fabricating the same, and to reduce the number of masks to make a simple manufacturing process. Increase production. The present invention is specifically described and exemplified in the present invention. The manufacturing method of the liquid crystal display device of the present invention includes the definition of the halogen component. An insulating substrate of the transistor region; forming an intermediate electrode on the % edge substrate to cover the surface portion of the germanium portion to form a pixel portion on the wire layer; on both sides of the halogen side electrode Forming a source region of the element portion and a drain region of the element portion in the active layer; the surface including the first and second contact holes on the substrate having the drain region of the element, wherein the first And a second contact hole respectively exposing a source region of the pixel portion and a non-polar region of the pixel portion; sequentially forming a turned conductive film and a metal film on the protective film; and, selectively, a metal film and a transparent conductive film to form a source electrode pattern of the element portion/source electrode of the element portion, and a source electrode pattern of the element portion of the element portion is sequentially deposited to cover the first contact hole, and The 汲 electrode of the elementary part _ the electrode of the 〆昼 部 part of the ' 部 峡 峡 峡The _/ pixel portion is sequentially deposited to cover the second contact hole. Another object of the present invention is to provide a liquid crystal display device including an insulating substrate defined by a thin film transistor region of a halogen portion; an active layer formed on the substrate to cover a thin film transistor region of the pixel portion The gate electrode of the element is formed on the active layer; the source region of the element and the secret region of the pixel are formed in the two _ active layers of the gate electrode of the pixel; including the first and second The protective film of the contact hole is formed on the substrate including the secret region of the element, and the first and second contact holes respectively expose the source region of the element portion and the drain region of the element portion; 1332265 source electrode pattern / source electrode of the halogen portion is sequentially deposited on the protective film to cover the first contact hole; and the germanium electrode pattern of the halogen portion / the germanium electrode of the halogen portion It is sequentially deposited on the protective film to cover the second contact hole. The foregoing and other objects, aspects, and advantages of the present invention will become more apparent [Embodiment] The following will be explained in detail in conjunction with the implementation of the ® type. Fig. 2 is a plan view showing a part of the array substrate of the liquid crystal display device of the first embodiment of the present invention. In particular, the "Fig. 2" table contains a single element of the thin film transistor of the pixel portion. The liquid-day and day-to-day display device of the ...^ contains the (4) gate line and the element of the data line formed by the data line. The gate line is connected to the data line, but for the sake of simplicity _ '2' It is described in a concise manner only with a graphic representation of the elements. The array substrate 110 of the first embodiment of the present invention comprises: a line 117, which is horizontally and vertically oriented in the noisy area of the enamel plate; a thin film transistor is formed on the gate line 116 and the data. The line, the other part, and the drawing pole 118 are formed on the drawing of the Wei domain to connect the common electrode on the color slab substrate (not shown) to drive the liquid crystal (not shown). The thin film transistor includes a _ pole 121, a (four) pole line 'source electrode (2), 12 connected to the bead line 117; and; and an electrode 123 connected to the pixel electrode 118. The film: body further includes an active pattern m' which forms a conductive path between the source electrode 122 and the germanium electrode 123 using the inter-electrode voltage supplied to the gate electrode m. The active pattern 124 of the first embodiment is formed by a polycrystalline film, and the active portion 124 is extended to the halogen region to be connected to the storage pattern. 24, constitute a first-storage capacitor and a common line purchase. change. The common line 1 〇 8 is formed in the pixel region, substantially the same as the gate line 2 and overlaps with the underlying memory 124, to be separated by the first insulating film (® And the shape of the wire_storage capacitor. At this time, the storage pattern is formed by performing a process of doping different from the multiple (four) _ constituting the active _ 124 to form the memory pattern 124 of the first embodiment. The source electrode 122 and the non-electrode 123 are electrically connected to the source of the active pattern 124 through the first contact hole HOa and the second contact hole respectively formed in the first insulating film and the second insulating film (not shown). Polar area and silk area. In addition, the portion of the source electrode ^ is extended in the portion of the surface line m to the portion of the surface line m, and the portion of the source electrode is extended to the pixel region 11' through the third insulating film (not shown). The third contact hole 140c is electrically connected to the halogen electrode. The 2 electrode 123 partially extends to the pixel region, and the common line weight S' below it is transmitted through the second insulating layer (10) of the towel. The following will be combined with "the second syllabary of the second dynasty" and "the first The process of the array substrate described above is described in "3E", "3F", "Picture", "New" and "31 31 1332265". "3A", "3B", "3C", "3D", "D", "3F", "3G", "3H" and " The 3i maps respectively show the cross-sections of the steps of the line of the patch on the county board along the "Fig. 2". "3A", "3B", "%", "3d", "Digital", "3F", "3G", "Division" and " FIG. 31 exemplarily shows a process of providing an array substrate of an n-channel_transistor portion of a transistor. As shown in Fig. 3A, the film is formed on the array substrate U0 of, for example, a transparent insulating material of glass, and is then crystallized to form a polycrystalline film. At this time, the array substrate H0 is defined by a halogen portion and a circuit portion (not shown), wherein the pixel portion is divided into an n-channel thin film transistor series and a storage region, and the circuit portion (four) is divided into an η-channel thin film transistor region. And ρ channel_transistor area. New, the money is engraved to form a polycrystalline (tetra) film pattern to form an active pattern and a storage pattern (first: reticle process). At this time, the buffer layer ηι may be interposed between the array substrate and the polysilicon film pattern 124. As shown in "FIG. 3B", the polycrystalline thin film pattern 124 is partially shielded by a single photoresist mask to perform doping to form a memory _m". The polycrystalline slab __24 portion blocked by the photoresist Then, the active pattern 124 is formed, (the second mask process). As shown in FIG. 3C, the first insulating film 11Sa and the first conductive film are sequentially formed on the entire surface of the object substrate 11Q. Touching the first conductive (four) to form the gate electrode 121 of the first conductive film on the active pattern 124, on the same as the memory pattern 124" (the common line forming the first conductive film when the third mask is formed) The first conductive film is made of a low-resistivity opaque conductive material, such as aluminum, 1 Lu alloy, tungsten, copper, chromium, and indium, thereby forming a gate electrode (2) and a common = 108. This, the common line will be 昼In the prime region, the storage is similar to that in the prime region. If the money is between (10) and then (10), the first light-shielding film 170 is formed on the gate electrode containing 1? Above the substrate of the wire (10). The first light-shielding film m is smashed to shield the entire surface of the array earth plate (10) and the circuit portion of the thin film transistor region to expose the dielectric film. This example towel does not show the circuit portion. After the iron, the first mask m is used as the scale, and the A-doped _p+ ion is implanted into the circuit portion of the circuit portion to form the source region and the drain region (not shown). Four mask processes). As shown in "3E", the first light-shielding film 17 is removed. Next, a first light-shielding film 170 is formed over the substrate including the p+ source region and the drain region. The second visor is patterned to shield the p-channel thin film transistor region of the circuit portion, and the octagonal eight-way. The part of the n-pass film transistor _ and the storage area. After the absence, the second mask is used, and the active pattern m of the _n+ ion surface is recorded, where the n+ source region and the drain region are formed in the active pattern 124 of the element. Five mask process). In the 3F figure, the second light-shielding film is removed, and then the light-touch 15 1332265 η-ion is implanted from the entire surface of the flying substrate nQ from which the second light-shielding film is removed, thereby

形成輕摻雜汲極（ligMy doped drain ; LDD)區域1241。「第3F 圖j中’參考“號124c表示通道區域，其中通道區域於源極區域 1撕和没極區域1施之間形成導電通道。更詳細地，輕摻雜沒極 區域1241形成於源極區域124a和通道區域124c之間以及汲極區 域124b和通道區域124c之間。此外，雖然圖中未表示，輕推雜 及極區域1241形成於晝素部的⑽道薄膜電晶體區域中，而且& 離子也被植入電路部的η通道區域以形成輕摻雜汲極區域。 然後，第二絕緣膜n5b被沉積於包含輕摻雜汲極區域1241 的陣列基板110的整個表面上以後，第一絕緣膜115a以及第二絕 緣膜115b被部分地移除以形成第一接觸孔14〇&和第二接觸孔 140b ’其中第-接觸孔丨術曝露出部分的源極區域撕，而第二 接觸孔140b曝露出部分的汲極區域124b (第六道光罩製程）。 如「第3G圖」所示，第二導電膜形成於陣列基板110的整個 表面之上，然後選擇性地被蝕刻以形成源電極122，並透過第一接 觸孔140a電連接於源極區域124a，此外還形成没電極⑵，並透 過第二接觸孔14Gb電連接於祕d域124b (第七道光罩製程）。 此k ’晝素部之源電極1£2的一部分沿某個方向延伸以形成 貢料線117’而晝素部之沒電極123的一部分則延伸至晝素區域並 且重疊於其下的共同線⑽，透過介於兩者間的第二絕緣膜115b 以形成第二館存電容器。 16 如第3H圖」所示’第二絕緣膜115^被沉積於陣列基板⑽ 的整個表面之上’然後選擇性地被爛以形成第三接觸孔勵， 其中第三接觸孔140c曝露出部分的汲電極123(第八道光罩製程）。 如「第31圖」所示’第三導電膜形成於形成有第三絕緣膜115c 的陣列基板110的整個表面上，然後選擇性地被侧以形成晝素 電極118 ’並透過第三接觸孔·電連接於汲電極123 (第九道 光罩製程）。 第三導電麟由具有良妤透射率騎明導紐卿成，例如 銦錫氧化物（mdiUmtinGxlde ;则或者銦鋅氧化物（mdmm屢 oxide，IZO) ’從而形成晝素電極118。 /如上所述，本發明之第—實施例中，主動圖案以及儲存電極 係由多晶咬薄膜形成，並且透過單_光罩製程為儲存圖案完成儲 存區摻雜’從而透過完整的九道光罩製程可製造出晝素部和電路 部的薄膜電晶體。 第4圖」係為本發明第二實施例之液晶顯示裝置之陣列基 板之一部分的平面示意圖。 如「第4圖」所示’依照本發明之第二實施例，絕緣基板2〇ι 包含閘極線213G和資料線，其係分別於水平和垂直方向佈設 以定義出畫素區域。絕緣基板2〇1係對應於陣列基板。用作開關 疋件的薄膜電晶體（thinfllmtransistGr;TFT)形成於閘極線⑽ 和貝料線240的父又部’晝素部的及電極圖案2i9p2係為晝素電 17 1^32265 =嫌!素區域中並且連接於薄膜電晶體，用以和彩色 二^(圖中未表示）的共同電極（圖中未表示卜 饮日日（圖中未表示）〇A lightly doped drain (LDD) region 1241 is formed. The reference numeral 124c in "3FFig. j" denotes a channel region in which a channel region forms a conductive path between the source region 1 tear and the electrodeless region 1 . In more detail, the lightly doped gate region 1241 is formed between the source region 124a and the channel region 124c and between the drain region 124b and the channel region 124c. Further, although not shown in the drawing, the nappy and polar regions 1241 are formed in the (10) thin film transistor region of the halogen portion, and the & ions are also implanted in the n-channel region of the circuit portion to form a lightly doped drain. region. Then, after the second insulating film n5b is deposited on the entire surface of the array substrate 110 including the lightly doped gate region 1241, the first insulating film 115a and the second insulating film 115b are partially removed to form a first contact hole. 14〇& and second contact hole 140b' wherein the source region of the exposed portion of the first contact hole is torn, and the second contact hole 140b exposes a portion of the drain region 124b (sixth mask process). As shown in "3G", a second conductive film is formed over the entire surface of the array substrate 110, and then selectively etched to form the source electrode 122, and is electrically connected to the source region 124a through the first contact hole 140a. Further, a non-electrode (2) is formed and electrically connected to the secret field 124b through the second contact hole 14Gb (seventh mask process). A portion of the source electrode 1£2 of the k' unit portion extends in a certain direction to form a tributary line 117', and a portion of the electrode 123 of the element portion extends to the common region of the halogen region and overlaps thereunder. (10) A second storage capacitor is formed by the second insulating film 115b interposed therebetween. 16 as shown in FIG. 3H, 'the second insulating film 115 is deposited on the entire surface of the array substrate (10)' and then selectively smashed to form a third contact hole, wherein the third contact hole 140c exposes a portion汲 electrode 123 (eighth reticle process). As shown in "31", the third conductive film is formed on the entire surface of the array substrate 110 on which the third insulating film 115c is formed, and then selectively side-by-side to form the pixel electrode 118' and through the third contact hole. • Electrically connected to the ruthenium electrode 123 (ninth reticle process). The third conductive lining is formed by a high-density transmittance of, for example, indium tin oxide (mdiUmtinGxlde; or indium zinc oxide (mdmm oxide), thereby forming a halogen electrode 118. In the first embodiment of the present invention, the active pattern and the storage electrode are formed by a polycrystalline bite film, and the storage region is doped by a single-mask process to store the pattern, thereby manufacturing through a complete nine-mask process. A thin film transistor of a halogen portion and a circuit portion. Fig. 4 is a plan view showing a portion of an array substrate of a liquid crystal display device according to a second embodiment of the present invention, as shown in Fig. 4 In the second embodiment, the insulating substrate 2〇 includes a gate line 213G and a data line which are respectively arranged in the horizontal and vertical directions to define a pixel area. The insulating substrate 2〇1 corresponds to the array substrate. The thin film transistor (thinfllmtransistGr; TFT) is formed on the gate line (10) and the parent side of the shell line 240, and the electrode pattern 2i9p2 is in the area of the 昼素电17 1^32265=嫌! to Thin film transistor for common electrode with color II (not shown) (not shown in the figure (not shown in the figure)〇

_電晶體包含晝素部的閘電極213G2和晝素部的源電極 接於及旦素桃及電極221D1 ’其中晝素部的閘電極213G2連 問極線213G’晝素部的源電極221S1及畫素部的汲電極 1連接於貧料線240。薄膜電晶體更包含第一主動層 ^PIA，透過利用供應至晝素部的閑電極2ι迎之閉電壓以於晝 素部，源電極221S1和晝素部的汲電極2酬之間形成導電通 乙第-主動層205P1A被劃分為晝素部的源極區域2〇5piAs和 晝素部的汲極區域205P1AD。第-絲層獅1A的—部分被延 伸至j素部（準確地說，係儲存區域），儲存電極2〇5§則形成於 第一主動層205P1A的延伸部分中。 共同線213C形成於晝素區域中，實質上與閘極線2BG的方 向相同。共同線213C重疊於儲存電容2〇5S，透過介於兩者間之 閣極絕緣膜（圖中未表示）以構成儲存電容器。共同線213C可被 與閘極線213G相同的膜圖案化。 保護膜（圖中未表示）佈設於包含共同線213C的基板之上。 第—接觸孔215H1和第二接觸孔215H2形成於保護膜和閘極絕緣 膜中’其中第一接觸孔215H1曝露出第一主動層2〇5P1A之畫素 部的源極區域205P1AS，而第二接觸孔215H2曝露出晝素部的汲 18 1332265 極區域205P1AD。晝素部的源電極221S1和晝素部的;：及電極2?lm 各自透過第一接觸孔215H1和第二接觸孔215H2而電連接於第一 主動層205P1A之晝素部的源極區域205P1AS和畫素部極區 域 205P1AD。 晝素部的源電極圖案219P1係配置於畫素部的源電極22isi 和晝素部的源極區域205P1AS之間。此外，晝素部的沒電極圖案 219P2則配置於晝素部的汲電極221Di和晝素部的及極區域 205P1AD之間。晝素部的汲電極圖案219P2係佈設以部分地延伸 至晝素區域。此時，晝素部的及電極圖案219P2可對應於查素+ ° 換言之，晝素部的源電極圖案219P1和晝素部的及電極圖案 219P2各自被佈設於晝素部的源電極221S1和晝素部的汲電極 22im之下。晝素部的沒電極圖案219p2和畫素部的源電極圖宰 219P1被相同的膜圖案化。畫素部的汲電極圖案2i9p2和畫素= 的源電極圖案219P1可被透明導電膜圖案化。 且 「第5A圖」、「第5B圖」、「第5C圖」、「第5〇圖」、「第纪 圖」、「第5F圖」、「第5G圖」、「第5H圖」、「第51圖」、「第y 圖」^及「第5K圖」分別為沿「第4圖」所示之線瓜瓜，之剖面 圖，「第7A圖」、「第7B圖」、「第7C圖」、「第7D圖」、「第兀 圖」以及「第7F圖」分別為沿「第6圖」所示之線^^，之剖面 圖。下面將結合「第5Α圖」、「第5Β圖」、「第5c圖」、「第犯圖、 19 1332265 「弟 5E 圖 I、「常 「/r/r 乐5F圖」、弟5G圖」、「第5H圖」、「第51圖」、 「弟5J圖丨、「结 荜5Κ®」、第7A圖」、「第7B圖」、「第7C圖」、 「第7D圖，、「结& r ^ 弟7E圖」以及第7F圖」描述本發明第二實施 例之液晶顯示裝置的製造方法。 查立^ 5A圖」以及「第从圖」所示’製備絕緣基板2〇卜 *％路#、間極墊部以及密封線部各自定義於絕緣基板201 :八卜素°卩被劃分為n通道（或者P通道）薄膜電晶體區域 =存區域1路部被劃分為n通道薄㈣晶體區域和p通道薄 膜毛日日體區域。晝素部可配設有n通道薄膜電日日日體和P通道的薄 :電體為了便利起見，下面將描述晝素部的η通道薄膜電晶 體區域。此外，電路部麻設η通道_電晶體和ρ通道薄膜電 晶體以組成互補金氧半導體結構。 接下來，緩_ 2〇3以及多晶頻2〇5依序地形成於絕緣基 板2〇1之上。多晶頻2Q5的形成方式如下：先沉積非晶賴然 後再將其結晶。接著’形成第一遮光膜231於包含多晶賴挪 的基板之上。此時’第一遮光膜231係形成用以遮蔽部分的主動 層，其中主動㈣各自職於畫素部的n通道_電晶體區域、 電路部的η通道薄膜電晶體區域以及電路部的p通道薄膜電晶體 區域中。 ^ 如「第SB圖」所示，使用第-遮光膜如作為遮罩以賴多 晶石夕膜’從而使晝素部的n通道薄膜電晶體區域、電路部的續 20 丄 JJZZO：) 道薄膜電晶體區域以及電路部的P通道薄膜電晶體區域中之多晶 矽膜形成第-、第二以及第三多晶石夕圖案着i、詹2以及屢3 (第一道光罩製程）。 "如「第5C圖」所示，移除第一遮光膜。接下來，形成第二遮 光膜233於包含第一、第二以及第三多晶石夕圖案的基板上。此時， 所形成之第二遮光膜233制以賴第―、第二以及第三多晶石夕 ，案205H、2G5P2以及鹏，並且曝露出儲存區域中的部分多 曰曰夕1U然後，使用第二遮光膜233作為遮罩，推雜雜質離子 進入基板以形成儲存電極。排除儲存電極施以外的第一 夕一夕1U 2G5P1财於畫素部的n通道細電晶體區域之主動 層第一夕曰曰石夕圖案相當於電路部的η通道薄膜電晶體區域之主 動層，以及第三多晶♦圖案相當於ρ通道薄膜電晶體區域的主動 曰此τ旦素的η通道薄膜電晶體區域之主動層、電路部的打 通道薄膜電晶魏域之絲層以及魏部的ρ通道_電晶體區 域之主動層將分別稱為第—线層、第二絲層以及第三主動層 205Ρ1Α、205Ρ2Α以及205Ρ3Α (第二道光罩製程）。 如第5D圖」所示，首先移除第二遮光膜。將閑極絕緣膜 2〇7、第-金屬膜213以及第三遮光膜235依序地形成於包含第 一、第二以及第三主動層2〇5Ρ1Α、2〇5Ρ2Α以及2〇5ρ3Α的基板之 上。此時’閘極絕緣膜2〇?可為二氧化矽（Si〇2)膜。此外，第 三遮光膜235之形成係用以覆蓋畫素部、電路的n通道薄膜電晶 21 體區域以及部分的“ 膜扭作為遮罩以晶體區域。然後，使用第三遮光 膜電晶體區域中之電路部4屬膜^以形成電路部”通道薄 部和電路部的η通道_ f“極細。此時，因為畫素 沒有被_化並且H道賴電晶舰域中的^金屬膜如 屬膜犯_刻製程。因此Γ，透過賴刻製程完成第—金 可被過量地部的第肩極聰的· 獅的第i電極2⑽之^^ 235 n 的第-源極區域勒s矛/執行㈣子摻雜。結果，電路部 第三主動層2咖中。路部的第—跡區域蕭3D形成於 如「弟5E圖j所+ 势 -源極區域二;：遮光膜237形成於 — …领弟-汲極區域205P3D之基板上。 和域237之料制㈣蓋畫素部帽分的間電極 、線、、视部的11通道_電晶體區域中之部分第二閘電極 以及ρ通道薄膜電晶體區域。 如「第5?圖,以;$「坌”门 弟7Α圖」所示，使用第三遮光膜237 姓刻剩餘的第一金屬膜：213， 、 开>成/、同線213C及畫素部中配設 有畫素部的閘電極213G2之閘極線。同時，電路部的第二閉電極 2UG3形成於電路部的n通道薄膜電晶體區域中，而第—金屬層 圖案2腦軸於祕_巾❻四道拉餘）。此時，可以使 22 1332265 用濕綱秘_餘㈣—金驗213。結果，晝素部的閘電極 213G2共同線213c以及電路部的第二閘電極的側面可被 過量地姓刻。 接下來，針對具有第四遮光膜的基板執行n+離子摻雜。結果， 旦素柏源極區域2〇5PlAS以及晝素部的沒極區域2〇5PlAD形成 於第-主動層2G5P1A巾，並位於晝素部賴電極21迎的兩侧 下方；電路部的第二祕區域難2S和電路部的第二及極區域 205P2D則形成於第二主動層2()5p2中，並位於電路部的第二問電 極213G3的兩側下方。 如「第5F圖」所示，移除第三遮光膜，然後使用晝素部的間 電極213G2和電路部的第二閘電極犯⑴作為遮罩，針對基板的 整個表面執行n•料之〉及姉雜(LDD)。絲，帛—輕摻雜没極 區域205P1AL形成於第—主動層詹1A中，而第二輕摻雜汲極 區域205P2L形成於第二主動層2Q5p2中。第—和第二輕捧雜没極 區域205HAL和205P2L形成有相同數量的·刻特徵尺寸 (Critical Dnnension ; CD)偏差，並可藉由在不具有單一光罩的 狀態下摻雜基板的整個表面而獲得。 如「第5G圖」以及「第7B圖」所示，保護膜215形成於具 有第一和第二輕摻雜汲極區域2〇5piAL和2〇5p2L之基板上。依 照適當順序沉積的二氧化賴以及氮秘（silieGnni祕；狐） 膜可用作保護膜215。此時’保護膜215係依照如下方式形成··首 23 1332265 ====膜且經過活化退火之後，再沉積氮切膜並且經 過風化退火（弟-方法）。保護膜215的另一形成方式如下：依序 形成-乳化石夕膜以及氮化石夕膜，然後進行退火程序（第二 如果保護膜215係透過望-# . 讀如—方杨成，則二氧化賴的活化以及 氮化石夕膜的氫化可透過-次退火程序而同時完成。 同時，單一氮化石夕臈可以用作保護膜215。如上所述，本發明 :用包Γ化頻用作保護膜215的結構。本實施财，氮切 馭係用作可產生氫化作用的氫來源。 然而’如果採用二氧化賴/氮切膜的結構或者單-氮化 2的結細蝴咖215，购靖數為6 5 數並且袖帥積厚度下，每轉絲_電容大於介電常 數為3.9之二氧切膜的電容。因此，分別佈設於保護細二 加°之.1的_和__效應將增加，以致訊號延遲增 ¥致產生有關兩速作業以及高解析度之問題。 為^決這個問題，保護膜215可形成二氧化賴/氮化梦 -Μ頻之二層結構’其中介電常數較低的二氧切膜沉 賴之上。如果制：氧化頻/氮化頻/二氧化石夕 =構作為保護膜215，則在相同沉積厚度下，各單元區域 Γ谷將小於二氧化频/氮切膜結構或者氮化頻結構的電 t絲，線和資料線之間的電效應降低，因此訊號延遲降 -仗而可貫現焉逮作業或者高解析度。 24 1332265 其次’使用單-光罩（圖巾未表示）钱刻保護膜和問極絕緣 膜’以形成第一、第二、第三、第四、第五及第六接觸孔215H1、 215H2、215H3、215H4、215H5 及 215H6 以及開口部 2150 (第五 运光罩製程）。第一接觸孔215H1以及第二接觸孔215H2曝露出 晝素部的源極區域205P1AS以及晝素部的汲極區域2〇5piAD。此 外’第三接觸孔215H3以及第四接觸孔215H4曝露出電路部的第 二源極區域205P2S以及電路部的第二汲極區域2〇5p2D。第五接 觸孔215H5以及第六接觸孔215H6則曝露出電路部的第一源極區 域205P3S以及電路部的第一汲極區域2〇5P3D。此外，開口部2丨5〇 則曝露出第一金屬層圖案213G4。 接著，卩早壁金屬膜217形成於具有第一至第六接觸孔、 215H2、215H3、215H4、215H5 及 215H6 以及開口部 215〇 的基 板之上。此時，鉬膜用作障壁金屬膜217。此外，障壁金屬膜217 的厚度約為300埃(A)至700埃(A)，較佳為500埃(A)。隨後，遮 光膜239被沉積在具有障壁金屬膜217的基板之上。此時，如果 保濩膜215具有1.5微米至2.5微米的厚度，較佳為2·〇微米，則 遮光膜239的沉積厚度為〇·5微米至ι·〇微米，其中較佳為〇8微 米。 如「第5H圖」以及「第7C圖」所示，經灰化的第四遮光膜 239P係透過灰化(ashing)遮光膜239而形成。此時，於第_、第二、 第三、第四、第五及第六接觸孔215m、215H2、215H3、215H4、 25 1332265 215H5及215H6以及開口部215〇中形成經灰化的第四遮光膜 239P的殘留’並且曝露出保護膜215社表面。接下來，透過渴 飯刻製程針對具有經灰化的帛四遮光膜239p的基板進行選擇性地 移除保護膜2丨5上的障壁金屬膜π。結果，障壁金屬膜圖案⑽ 被形成以覆蓋第-、第二、第三'第四、第五及第六接觸孔21细、 215H2、215H3、215H4、215H5 及 215H6 以及開口部 2150。此時， 視保護膜215的厚度（>2.〇微米）而定，障壁金屬膜圖案2i7p可 走被形成以覆I第-、第二、第三、第四、第五及第六接觸孔 215ΪΠ、215H2、215H3、215H4、215H5 及 215H6 的底部。障壁 金屬膜圖案217P用於改善後來形成的透明導電膜、晝素部的源極 區域205PA1S、晝素部的汲極區域2〇5PA1D、電路部的第二源極 區域205P2S、電路部的第二汲極區域205P2D、電路部的第一源 極區域205P3S以及電路部的第一汲極區域2〇5P3D之間的接觸電 阻。 如「第51圖」以及「第7D圖」所示，移除經灰化的第四遮 光膜239P，然後透明導電膜219、第二金屬膜221以及絕緣膜223 形成於具有障壁金屬膜圖案217P的基板之上。接下來，使用狹縫 或者半色調光罩（圖中未表示）形成第五遮光膜241於具有絕緣 膜223的基板之上。此時，第五遮光膜241係對開口部2150以及 第一、第二、第三、第四、第五及第六接觸孔215Η1、215Η2、215ίί3、 215Η4、215Η5及215Η6的相應部形成覆蓋，並且允許電路部的η 26 1332265 通道薄膜電晶魏域、電路部的p通道_電晶體_以及畫素 部的n通道薄膜電晶體區域的厚度較畫素部_存區域以及閘極 墊部為厚。 如「第5J圖」以及「第7E圖」所示，使用第五遮光膜作為 麵刻遮罩以進仃第二金屬膜以及透明導電膜之麵㈣程。接下 來’灰化第六遮光膜，然後透過經灰化的第五遮光膜圖案瓣曝 露出絕緣膜223和第二金屬膜221 (第六道光罩製程）。結果，晝 素部的源電極圖案219P1/畫素部的源電極22isi/晝㈣的= -絕緣圖案223P!以及晝素部的汲電極圖案2i9p2/畫素部的汲 電極細/畫素部的第二絕緣圖案聰依序地被沉積以覆蓄 第-接觸孔細以及第二接觸孔職，並且形成於晝素部: η通道雜電晶體區域中。同時，形成電路部的第二源電極 2肥/電路部的第二源電極2搬/電路部的第一絕緣圖安' 223P3以及電路部的第：汲電極瞧綱/電路部 : 極221D2/電路部的第二絕绫 一及電 弟、，巴緣圖案223P4,亚依序地沉積 三接觸孔2削和第四接觸孔2聰。 ^弟 極圖案搬5/電路部_ $路销卜源電 /电岭。丨的弟一源電極221S3/ 圖案223P5以及電路部的第 ' 一絕緣 峪P的弟—及電極_219P6/電 汲電極221D3/電路部的笙…妨* ’^弟一 / -路弟四絕緣圖案腿依序地 第五接觸孔215Η5以及第丄垃經β ν 相从覆盍 心接觸孔215Η6,且形成於電路、 通道薄膜電晶體區域中。此Β士 +主 -卩的ρ 丫此日丁，晝素部的汲電極圖案21沖 為 27 Π32265 二晝素電極。同時，透明導電膜圖案219P7形成於閘極墊部以港 蓋開口部215。。其中，透明導電膜圖案219P7透過開α部復 連接至第—金屬層圖案213G4。 〇The transistor includes a gate electrode 213G2 of the halogen portion and a source electrode of the halogen portion connected to the source electrode 221S1 of the element portion of the electrode line 213G' of the element electrode 213G2 and the gate electrode 213G2 of the element portion The germanium electrode 1 of the pixel portion is connected to the lean line 240. The thin film transistor further includes a first active layer PIA, and a conductive voltage is formed between the source electrode 221S1 and the germanium electrode of the halogen portion by using a closed voltage supplied to the dummy electrode 2ι supplied to the element portion. The B-th active layer 205P1A is divided into a source region 2〇5piAs of the halogen portion and a drain region 205P1AD of the halogen portion. The portion of the first-layer lion 1A is extended to the y-part (more precisely, the storage area), and the storage electrode 2 〇 5 § is formed in the extended portion of the first active layer 205P1A. The common line 213C is formed in the halogen region and is substantially the same as the direction of the gate line 2BG. The common line 213C overlaps the storage capacitor 2〇5S, and transmits a barrier insulating film (not shown) interposed therebetween to constitute a storage capacitor. The common line 213C can be patterned by the same film as the gate line 213G. A protective film (not shown) is disposed on the substrate including the common line 213C. The first contact hole 215H1 and the second contact hole 215H2 are formed in the protective film and the gate insulating film 'where the first contact hole 215H1 exposes the source region 205P1AS of the pixel portion of the first active layer 2〇5P1A, and the second The contact hole 215H2 exposes the 汲18 1332265 pole region 205P1AD of the element. The source electrode 221S1 of the halogen portion and the electrode portion 2:lm and the electrode 2?lm are electrically connected to the source region 205P1AS of the pixel portion of the first active layer 205P1A through the first contact hole 215H1 and the second contact hole 215H2. And the pixel region 205P1AD. The source electrode pattern 219P1 of the pixel portion is disposed between the source electrode 22isi of the pixel portion and the source region 205P1AS of the pixel portion. Further, the electrodeless pattern 219P2 of the halogen portion is disposed between the tantalum electrode 221Di of the halogen portion and the parallel region 205P1AD of the halogen portion. The tantalum electrode pattern 219P2 of the halogen portion is disposed to partially extend to the halogen region. At this time, the electrode portion and the electrode pattern 219P2 of the halogen element can correspond to the check element + °. In other words, the source electrode pattern 219P1 of the element portion and the electrode pattern 219P2 of the element portion are respectively disposed on the source electrode 221S1 and the electrode of the element portion. The 汲 electrode of the element is below 22im. The electrodeless pattern 219p2 of the halogen portion and the source electrode pattern 219P1 of the pixel portion are patterned by the same film. The germanium electrode pattern 2i9p2 of the pixel portion and the source electrode pattern 219P1 of the pixel= can be patterned by the transparent conductive film. And "5A", "5B", "5C", "5th", "Digital", "5F", "5G", "5H", "51", "Y y" and "5K" are the sectional views of the line shown in Figure 4, "Figure 7A", "Phase 7B", " Sections 7C, 7D, 兀, and 7F are cross-sectional views of the line ^^ shown in Fig. 6. The following will be combined with "5th map", "5th map", "5c map", "figure map, 19 1332265", brother 5E map I, "normal" /r/r music 5F map, brother 5G map" , "5H", "51", "5", "5", "7A", "7B", "7C", "7D", " A method of manufacturing a liquid crystal display device according to a second embodiment of the present invention will be described with reference to <RTIgt;</RTI> The "Insulation Substrate 2" *% Road #, the inter-pole pad portion, and the sealing line portion are respectively defined on the insulating substrate 201 as shown in "Calli ^ 5A" and "Picture from the figure": 八素素卩 is divided into n The channel (or P channel) thin film transistor region = the storage region 1 is divided into an n-channel thin (four) crystal region and a p-channel thin film day region. The elemental unit can be equipped with an n-channel thin film electric day and day and a thin P channel: for the sake of convenience, the n-channel thin film transistor region of the elemental part will be described below. Further, the circuit portion is provided with an n-channel_transistor and a p-channel thin film transistor to constitute a complementary metal-oxygen semiconductor structure. Next, the buffer _ 2 〇 3 and the poly pattern frequency 2 〇 5 are sequentially formed over the insulating substrate 2 〇 1 . The polycrystalline frequency 2Q5 is formed in the following manner: first, the amorphous Lai is deposited and then crystallized. Next, a first light-shielding film 231 is formed over the substrate including the polycrystal. At this time, the first light-shielding film 231 forms an active layer for shielding portions, wherein the active (four) each operates on the n-channel_transistor region of the pixel portion, the n-channel thin film transistor region of the circuit portion, and the p-channel of the circuit portion. In the thin film transistor area. ^ As shown in the "Fig. SB", the use of the first-light-shielding film as a mask to the polycrystalline stone film, so that the n-channel thin film transistor region of the elemental part, the circuit section continues 20 丄JJZZO:) The polycrystalline germanium film in the thin film transistor region and the P-channel thin film transistor region of the circuit portion forms the first, second, and third polycrystalline spines, i, Zhan 2, and repeat 3 (first mask process). " Remove the first light-shielding film as shown in Figure 5C. Next, a second light shielding film 233 is formed on the substrate including the first, second, and third polycrystalline stone patterns. At this time, the formed second light-shielding film 233 is formed by the first, second, and third polycrystalline stones, 205H, 2G5P2, and Peng, and exposes a portion of the storage area, and then used. The second light shielding film 233 serves as a mask to push impurity ions into the substrate to form a storage electrode. Excluding the storage electrode, the first layer of the 1U 2G5P1 is the active layer of the n-channel fine transistor region of the pixel portion. The first 曰曰 曰曰 夕 图案 pattern corresponds to the active layer of the n-channel thin film transistor region of the circuit portion. And the third polycrystalline ♦ pattern corresponds to the active layer of the p-channel thin film transistor region, the active layer of the n-channel thin film transistor region of the τ-denier, the channel-type thin film electro-equivalent filament layer of the circuit portion, and the Wei department The active layers of the p-channel-transistor region will be referred to as a first-line layer, a second wire layer, and a third active layer 205Ρ1Α, 205Ρ2Α, and 205Ρ3Α, respectively (second mask process). As shown in Fig. 5D, the second light shielding film is first removed. The dummy insulating film 2〇7, the first metal film 213, and the third light shielding film 235 are sequentially formed on the substrate including the first, second, and third active layers 2〇5Ρ1Α, 2〇5Ρ2Α, and 2〇5ρ3Α. on. At this time, the gate insulating film 2 can be a germanium dioxide (Si 2 ) film. In addition, the third light-shielding film 235 is formed to cover the pixel portion, the n-channel thin film transistor region of the circuit, and a portion of the "film twist as a mask to the crystal region. Then, the third light-shielding film transistor region is used. The circuit portion 4 of the circuit is formed to form the circuit portion "the thin portion of the channel and the n-channel of the circuit portion _f" is extremely thin. At this time, since the pixel is not _ and the metal film of the H-ray crystal field is If it is a film _ _ engraving process. Therefore, through the etch process to complete the first - gold can be over-the-counter of the shoulder of the thief lion's ith electrode 2 (10) ^ ^ 235 n of the first - source region s Spear/execution (four) sub-doping. As a result, the third active layer of the circuit is in the middle of the circuit. The first trace of the road is Xiao 3D formed in "the 5E figure j + potential-source region 2;: the light-shielding film 237 Formed on the substrate of the ...-collar-bungee area 205P3D. The material of the field 237 (4) the electrode, the line of the cover part cap, the 11th channel of the view part, the part of the second gate of the transistor area Electrode and ρ channel thin film transistor region. For example, "5th figure, to; "坌"" The first metal film remaining in the film 237 is: 213, , > into /, the same line 213C, and the gate line of the gate electrode 213G2 in which the pixel portion is disposed in the pixel portion. At the same time, the second closed electrode 2UG3 of the circuit portion is formed in the n-channel thin film transistor region of the circuit portion, and the first metal layer pattern 2 has a brain axis in the secret. At this point, you can make 22 1332265 wet _ _ _ (four) - gold check 213. As a result, the gate electrode 213G2 common line 213c of the halogen portion and the side surface of the second gate electrode of the circuit portion can be excessively surnamed. Next, n+ ion doping is performed for the substrate having the fourth light shielding film. As a result, the 2〇5PlAS of the source region of the denier and the non-polar region 2〇5PlAD of the alizarin part are formed in the first active layer 2G5P1A towel, and are located below the sides of the element of the elemental electrode 21; the second part of the circuit part The second region and the second region 205P2D of the circuit portion are formed in the second active layer 2() 5p2 and are located below both sides of the second electrode 213G3 of the circuit portion. As shown in "5F", the third light-shielding film is removed, and then the interlayer electrode 213G2 of the element portion and the second gate electrode of the circuit portion are used as a mask, and the entire surface of the substrate is performed. And noisy (LDD). The wire, 帛-light doped immersion region 205P1AL is formed in the first active layer 1A, and the second lightly doped drain region 205P2L is formed in the second active layer 2Q5p2. The first and second portable impurity regions 205HAL and 205P2L are formed with the same number of critical dimensions (Critical Dnnension; CD) deviation, and may be doped by the entire surface of the substrate without a single reticle And get. As shown in "5G" and "Fig. 7B", the protective film 215 is formed on the substrate having the first and second lightly doped drain regions 2〇5piAL and 2〇5p2L. A ruthenium oxide and a nitrogen secret (silie Gnni) fox film deposited in an appropriate order can be used as the protective film 215. At this time, the protective film 215 was formed in the following manner. After the film was subjected to activation annealing, a nitrogen cut film was deposited and weathered and annealed (different-method). Another way of forming the protective film 215 is as follows: sequentially forming an emulsified stone film and a nitriding film, and then performing an annealing process (second if the protective film 215 is transmitted through the watch-#. Read as - Fang Yangcheng, then two The activation of the oxidized lanthanide and the hydrogenation of the nitriding film can be simultaneously performed by the -annealing process. Meanwhile, a single nitride enamel can be used as the protective film 215. As described above, the present invention: using a cladding frequency as a protective film The structure of 215. In this implementation, the nitrogen enthalpy is used as a hydrogen source that can generate hydrogenation. However, if the structure of the dialysis/nitrogen film is used or the structure of single-nitriding 2 is used, The number is 6 5 and the thickness of the sleeve is thicker. The capacitance per filament is larger than the capacitance of the dioxic film with a dielectric constant of 3.9. Therefore, the _ and __ effects of the protective fine two plus ° are respectively set. It will increase, so that the delay of the signal increase will cause problems related to the two-speed operation and high resolution. To solve this problem, the protective film 215 can form a two-layer structure of the dioxide/nitriding dream-Μ frequency. The lower constant oxygen dioxide membrane is above the foundation. If the system: Oxidation frequency / nitriding frequency / dioxide dioxide = as a protective film 215, then at the same deposition thickness, each unit area valley will be smaller than the dioxide frequency / nitrogen cutting film structure or the nitriding frequency structure of the electric t wire, The electrical effect between the line and the data line is reduced, so the signal delay is reduced, and the operation or high resolution can be achieved. 24 1332265 Secondly, use a single-mask (not shown) to engrave the protective film and ask a pole insulating film 'to form first, second, third, fourth, fifth and sixth contact holes 215H1, 215H2, 215H3, 215H4, 215H5 and 215H6 and an opening portion 2150 (fifth operation mask process). A contact hole 215H1 and a second contact hole 215H2 expose the source region 205P1AS of the element portion and the drain region 2〇5piAD of the element portion. Further, the third contact hole 215H3 and the fourth contact hole 215H4 expose the circuit portion. The second source region 205P2S and the second drain region 2〇5p2D of the circuit portion. The fifth contact hole 215H5 and the sixth contact hole 215H6 expose the first source region 205P3S of the circuit portion and the first drain of the circuit portion Area 2〇5P3D. In addition, the opening 2丨5〇 exposes the first metal layer pattern 213G4. Next, the 卩 early wall metal film 217 is formed on the substrate having the first to sixth contact holes, 215H2, 215H3, 215H4, 215H5, and 215H6 and the opening portion 215〇. At this time, the molybdenum film is used as the barrier metal film 217. Further, the barrier metal film 217 has a thickness of about 300 Å (A) to 700 Å (A), preferably 500 Å (A). Subsequently, the light-shielding film 239 is Deposited on the substrate having the barrier metal film 217. At this time, if the film 215 has a thickness of 1.5 μm to 2.5 μm, preferably 2 μm, the thickness of the light-shielding film 239 is 〇·5 μm to ι·〇 micron, preferably 〇 8 μm. As shown in "5H" and "7C", the ashed fourth light-shielding film 239P is formed by ashing the light-shielding film 239. At this time, the fourth shading is formed in the first, second, third, fourth, fifth, and sixth contact holes 215m, 215H2, 215H3, 215H4, 25 1332265 215H5 and 215H6, and the opening portion 215A. The film 239P remains "and exposes the surface of the protective film 215". Next, the barrier metal film π on the protective film 2丨5 is selectively removed by the thirst process for the substrate having the ashed 帛4 light-shielding film 239p. As a result, the barrier metal film pattern (10) is formed to cover the first, second, third 'fourth, fifth and sixth contact holes 21, 215H2, 215H3, 215H4, 215H5 and 215H6 and the opening portion 2150. At this time, depending on the thickness (> 2. micron) of the protective film 215, the barrier metal film pattern 2i7p can be formed to cover the first, second, third, fourth, fifth, and sixth contacts. The bottom of the holes 215ΪΠ, 215H2, 215H3, 215H4, 215H5 and 215H6. The barrier metal film pattern 217P is for improving the transparent conductive film formed later, the source region 205PA1S of the halogen portion, the drain region 2〇5PA1D of the pixel portion, the second source region 205P2S of the circuit portion, and the second portion of the circuit portion. The contact resistance between the drain region 205P2D, the first source region 205P3S of the circuit portion, and the first drain region 2〇5P3D of the circuit portion. As shown in FIG. 51 and FIG. 7D, the ashed fourth light-shielding film 239P is removed, and then the transparent conductive film 219, the second metal film 221, and the insulating film 223 are formed in the barrier metal film pattern 217P. Above the substrate. Next, a fifth light-shielding film 241 is formed over the substrate having the insulating film 223 using a slit or a halftone mask (not shown). At this time, the fifth light shielding film 241 forms a cover for the opening portion 2150 and the corresponding portions of the first, second, third, fourth, fifth, and sixth contact holes 215Η1, 215Η2, 215ίί3, 215Η4, 215Η5, and 215Η6, Further, the thickness of the n-channel thin film transistor region of the η 26 1332265 channel film, the p-channel transistor of the circuit portion, and the n-channel thin film transistor region of the pixel portion are allowed to be larger than the pixel portion and the gate pad portion. thick. As shown in "5J" and "7E", the fifth light-shielding film is used as the face mask to advance the surface of the second metal film and the transparent conductive film (fourth). Next, the sixth light-shielding film is ashed, and then the insulating film 223 and the second metal film 221 are exposed through the ashed fifth light-shielding film pattern flap (the sixth mask process). As a result, the source electrode pattern 219P1 of the pixel portion, the source electrode 22isi/昼(4) of the pixel portion, and the 绝缘 electrode pattern 2i9p2 of the pixel portion and the 汲 electrode portion/pixel portion of the pixel portion The second insulating pattern is sequentially deposited to cover the first contact hole and the second contact hole, and is formed in the pixel portion: n-channel impurity crystal region. At the same time, the first source of the second source electrode 2 of the circuit portion 2, the second source electrode 2 of the circuit portion, the first insulation diagram of the circuit portion, the '223P3, and the first portion of the circuit portion: the electrode assembly/circuit portion: the pole 221D2/ The second and first circuit of the circuit part, the rim pattern 223P4, sequentially deposits three contact holes 2 and the fourth contact hole 2 Cong. ^Dipole pattern moving 5/circuit department _ $路销卜源电/电岭.丨 一 一 一 source electrode 221S3 / pattern 223P5 and the circuit part of the 'one insulation 峪 P brother - and electrode _219P6 / electric 汲 electrode 221D3 / circuit part of the 笙 ... * ' ^ ^ brother / / road brother four insulation The pattern legs sequentially follow the fifth contact holes 215Η5 and the second layer through the β ν phase from the core contact holes 215Η6, and are formed in the circuit, channel thin film transistor region. This gentleman + main - 卩 ρ 丫 丫 丫 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼 昼At the same time, the transparent conductive film pattern 219P7 is formed in the gate pad portion to open the lid opening portion 215. . The transparent conductive film pattern 219P7 is reconnected to the first metal layer pattern 213G4 through the open α portion. 〇

°可，晝素部的第一絕緣圖案223Ρ1、晝素部的第二絕緣圖筹 223Ρ2、電路部的第一絕緣圖案223Ρ3、電路部的第二絕緣圖驾 223Ρ4、電路部的第三絕緣圖案223Ρ5以及電路部的第四絕 > 和彩色濾光片基板用於降低組立結合(cell b〇nding)製程二J 勺/、同龟極電各。因此’可避免液晶之延遲現象。 〆 如「第5K圖」以及「第7F圖」所示，移 光膜如然後形成密封線225於密封線部。 Λ化的弟五髮 程二=述第二實施例中，製造液晶顯示褒置的靠 二道光罩^成動層（第一道光罩製程）；形成儲存電極（| 衣程）’形成電路部的第一閘電極於電 電晶體區域（第 Ρ通這_ 以及電路部的第二間=成畫素部的閑電極、共同抑 部於保_ (第五2 罩製程）；形成接觸孔和開， 晝4===:，晝， 素部的及電細及電料 卩岐_圖案/4 極以及電路部的第』:=極圖案/電路部的第二_ 部的第〜源、電極圖宰魏部的第二及電極以及妨 電極圖案/電路部的第:::弟1、電極以及電路部的第1 及祕以錢日辑電膜_ (第六道光 28 1332265 縣程）。因此，經過六道光罩製程的互補式金氧半導體結構可在 南開口率條件下實現。 本發明之液晶顯示裝置及其製造方法具有以下優點。 使用單-遮罩透過繞娜找鄉成晝素電極以及源電 及電極。因此，可減少製造薄膜電晶體時所使用的遮罩數目，似 而減少製程步驟以及製造成本。 攸 本發明中，因為透明導電膜圖錢形成於密封線部和間極塾 部的外摩中’所以可將侵姓所弓f起的損害減至最小。 雖然本發明以前述之實施例揭露如上，然其並非用以 發明。在不脫離本發明之精神和範圍内，所為之更動與潤錦 屬錢明之專娜護翻之内。_本_解定之賴範圍請 麥照所附之申請專利範圍。 【圖式簡單說明】 第1 _蝴秘啊路之—般_轉置的結構平 面圖， ㈣Γ 2 _讀為本發明第—實施例之液晶顯示裝置之部分陣 列基板之平面示意圖； 至第31圖所示分別為沿第2圖所示之陣列基板之線 Π-Π之製程步驟之剖面圖，· f 4圖所示係為本發明第二實施例之液晶顯示裝置之部分陣 列基板之平面示意圖，· 29 1332265 第5A圖至第5K圖所示分別為沿第4圖所示之線ΠΙ-ΙΠ’之剖 面圖； 第6圖所示係為本發明第二實施例之液晶顯示裝置之陣列基 板之閘極墊部之平面示意圖；以及 第7Α圖至第7F圖所示分別為沿第6圖所示之線IV-IV’之剖 面圖。 【主要元件符號說明】°, the first insulating pattern 223Ρ of the element portion, the second insulating pattern 223Ρ of the element portion, the first insulating pattern 223Ρ3 of the circuit portion, the second insulating pattern of the circuit portion 223Ρ4, and the third insulating pattern of the circuit portion 223Ρ5 and the fourth electrode of the circuit part> and the color filter substrate are used to reduce the assembly process (cell b〇nding process) two J scoops/, the same to the turtle electric. Therefore, the retardation of the liquid crystal can be avoided.移 As shown in Fig. 5K and Fig. 7F, the light-transfer film then forms a seal line 225 at the seal line. Λ化弟五程程二= In the second embodiment, the two-layer reticle forming layer of the liquid crystal display device is fabricated (the first reticle process); the storage electrode (|clothing process) is formed to form a circuit The first gate electrode of the portion is in the region of the electro-optic crystal (the second pass of the _ and the second portion of the circuit portion = the idle electrode of the pixel portion, the common suppressor portion _ (fifth 2 mask process); forming a contact hole and opening , 昼4===:,昼, the part of the element and the electric material and the material 卩岐_pattern/4 pole and the part of the circuit part:==polar pattern/the second part of the circuit part The second and the electrodes of the Tuzaiwei and the electrode pattern/circuit part of the:::1, the first part of the electrode and the circuit part and the secret of the electric film _ (the sixth light 28 1332265 county). Therefore, the complementary MOS structure through the six-mask process can be realized under the condition of the south aperture ratio. The liquid crystal display device of the present invention and the method for fabricating the same have the following advantages. The use of a single-mask through the circumnavigation Electrode and source and electrode. Therefore, the number of masks used in manufacturing the thin film transistor can be reduced. The process steps and the manufacturing cost are reduced. In the present invention, since the transparent conductive film is formed in the outer portion of the sealing line portion and the inter-pole portion, the damage caused by the infringement of the surname can be minimized. The present invention has been disclosed in the foregoing embodiments, but it is not intended to be invented, and it is not to be construed as a part of the invention. Please refer to the patent application scope attached to Maizhao. [Simplified illustration of the drawing] The first _ _ _ _ _ _ _ _ _ transposed structural plan, (d) Γ 2 _ read the liquid crystal display device of the first embodiment of the present invention A schematic plan view of a portion of the array substrate; a sectional view of the process of the line Π-Π along the array substrate shown in FIG. 2 is shown in FIG. 31, and FIG. 4 is a second embodiment of the present invention. A schematic plan view of a portion of the array substrate of the liquid crystal display device, 29 1332265, Figs. 5A to 5K are respectively sectional views of the line ΠΙ-ΙΠ' shown in Fig. 4; Invention of liquid crystal display device of the second embodiment A plan view of the gate pad portion of the array substrate; and Figs. 7 to 7F are cross-sectional views taken along line IV-IV' shown in Fig. 6. [Description of main component symbols]

5 彩色遽光片基板 10 陣列基板 30 驅動電路部 31 資料驅動電路 32 閘極驅動電路 35 晝素部 108 共同線 110 陣列基板 111 緩衝層 115a 第一絕緣膜 115b 第二絕緣膜 115c 第三絕緣膜 116 閘極線 117 資料線5 color slab substrate 10 array substrate 30 drive circuit portion 31 data drive circuit 32 gate drive circuit 35 nucleus portion 108 common line 110 array substrate 111 buffer layer 115a first insulating film 115b second insulating film 115c third insulating film 116 gate line 117 data line

A 30 1332265 118 晝素電極 121 閘電極 122 源電極 123 汲電極 124 多晶矽薄膜圖案 124’ 主動圖案 124” 儲存圖案 124a 源極區域 124b >及極區域 124c 通道區域 1241 輕摻雜汲極區域 140a 第一接觸孔 140b 第二接觸孔 140c 第三接觸孔 170 第一遮光膜 170’ 第二遮光膜 201 絕緣基板 203 缓衝層 205 多晶梦膜 205S 儲存電極 205P1 第一多晶矽圖案 31 1332265 205P2 第二多晶矽圖案 205P3 第三多晶矽圖案 205P1A 第一主動層 205P2A 第二主動層 205P3A 第三主動層 205P1AS 畫素部的源極區域 205P2S 電路部的第二源極區域 205P3S 電路部的第一源極區域 205P1AD 晝素部的没極區域 205P2D 電路部的第二汲極區域 205P3D 電路部的第一汲極區域 205P1AL 第一輕掺雜没極區域 205P2L 第二輕摻雜汲極區域 207 閘極絕緣膜 213 第一金屬膜 213C 共同線 213G 閘極線 213G1 電路部的第一閘電極 213G2 晝素部的閘電極 213G3 電路部的第二閘電極 213G4 第一金屬層圖案 32 1332265A 30 1332265 118 halogen electrode 121 gate electrode 122 source electrode 123 germanium electrode 124 polysilicon thin film pattern 124' active pattern 124" storage pattern 124a source region 124b > and polar region 124c channel region 1241 lightly doped drain region 140a One contact hole 140b second contact hole 140c third contact hole 170 first light shielding film 170' second light shielding film 201 insulating substrate 203 buffer layer 205 polycrystalline dream film 205S storage electrode 205P1 first polysilicon pattern 31 1332265 205P2 Dimorphism pattern 205P3 Third polysilicon pattern 205P1A First active layer 205P2A Second active layer 205P3A Third active layer 205P1AS Source region 205P2S of the pixel portion Second source region 205P3S of the circuit portion First of the circuit portion Source region 205P1AD No-pole region 205P2D of the pixel portion Second gate region 205P3D of the circuit portion First gate region 205P1AL of the circuit portion First lightly doped gate region 205P2L Second lightly doped gate region 207 Gate Insulating film 213 First metal film 213C Common line 213G Gate line 213G1 First gate electrode 213G2 of circuit portion 昼Second gate electrode 213G3 of the circuit portion of a gate electrode portion of the first metal layer pattern 213G4 321332265

215 保護膜 215H1 第一接觸孔 215H2 第二接觸孔 215H3 第三接觸孔 215H4 第四接觸孔 215H5 第五接觸孔 215H6 第六接觸孔 2150 開口部 217 障壁金屬膜 217P 障壁金屬膜圖案 219 透明導電膜 219P1 畫素部的源電極圖案 219P3 電路部的第二源電極圖案 219P5 電路部的第一源電極圖案 219P2 晝素部的汲電極圖案 219P4 電路部的第二汲電極圖案 219P6 電路部的第一汲電極圖案 219P7 透明導電膜圖案 221 第二金屬膜 221D1 晝素部的汲電極 221D2 電路部的第二汲電極 33 1332265215 protective film 215H1 first contact hole 215H2 second contact hole 215H3 third contact hole 215H4 fourth contact hole 215H5 fifth contact hole 215H6 sixth contact hole 2150 opening portion 217 barrier metal film 217P barrier metal film pattern 219 transparent conductive film 219P1 Source electrode pattern 219P3 of the pixel portion Second source electrode pattern 219P5 of the circuit portion First source electrode pattern 219P2 of the circuit portion 汲 electrode pattern 219P4 of the pixel portion Second 汲 electrode pattern 219P6 of the circuit portion First 汲 electrode of the circuit portion Pattern 219P7 Transparent conductive film pattern 221 Second metal film 221D1 汲 electrode portion 221D2 Circuit portion second 汲 electrode 33 1332265

221D3 電路部的第一汲電極 221S1 晝素部的源電極 221S2 電路部的第二源電極 221 S3 電路部的第一源電極 223 絕緣膜 223P1 晝素部的第一絕緣圖案 223P2 畫素部的第二絕緣圖案 223P3 電路部的第一絕緣圖案 223P4 電路部的第二絕緣圖案 223P5 電路部的第三絕緣圖案 223P6 電路部的第四絕緣圖案 225 密封線 231 第一遮光膜 233 第二遮光膜 235 第三遮光膜 237 第四遮光膜 239 遮光膜 239P 經灰化的第四遮光膜 240 資料線 241 第五遮光膜 241P 經灰化的第五遮光膜圖案 34221D3 circuit portion first electrode 221S1 source electrode 221S2 of circuit element second source electrode 221 of circuit portion S3 first source electrode 223 of circuit portion insulating film 223P1 first insulating pattern 223P2 of element portion Second insulating pattern 223P3 First insulating pattern 223P4 of circuit portion Second insulating pattern 223P5 of circuit portion Third insulating pattern 223P6 of circuit portion Fourth insulating pattern 225 of circuit portion Sealing line 231 First light shielding film 233 Second light shielding film 235 Three light-shielding film 237 Fourth light-shielding film 239 Light-shielding film 239P Ashed fourth light-shielding film 240 Data line 241 Fifth light-shielding film 241P Ashed fifth light-shielding film pattern 34

Claims (1)

1332265 1)9年3月1%修(更)正替換頁 '· 十、申請專利範圍·· 1· 一種液晶顯示裝置的製造方法，包含有： 製備-絕緣基板.，其中定義有一畫素部之一薄膜電晶體區 域； 形成一主動層於該絕緣基板之上以覆蓋該晝素部之該薄 膜電晶體區域； 形成S玄晝素部之一閘電極於該主動層之上； 馨 形成遠畫素部之一源極區域以及該晝素部之-汲極區域 於該主動層中，並位於該晝素部之該閘電極的兩側； 形成具有一第一和第二接觸孔之一保護膜於具有該晝素 部之該及極區域之该基板上，其巾該第—和第二接觸孔分別曝 露出該旦素部之該源極區域和該晝素部之該汲極區域； 依序地形成一透明導電膜以及一金屬膜於該保護膜之 上；以及 Φ 選擇11地餘刻該金屬膜和該透明導電膜以形成該晝素部 之原。極圖木/忒晝素部之一源電極，其係依序沉積以覆蓋 該第一接觸孔，以及形成該晝素部之一汲電極圖案/該畫素部 之·^及电極’其係依序沉積以覆蓋該第二接觸孔 …中素部之§亥源電極圖案/該晝素部之該源電極以 及該畫素部之紐電_案/難素狀舰電極係利用一 單一遮罩進行繞射曝光而形成。 35 1332265 2. 如申請專利範圍第1項所^ϊϊ4置的製造方法，其中，: 於形成該晝I部之該閘電極之麵前，更包含形成—酿絕緣 膜於具有該主動層之該基板上。 3. 如申w專利⑯圍第i項所述之液晶顯示裝置的製造方法，其中 该保墁膜係藉由在具有該晝素部之該汲極區域之該基板上沉-積及活化退火(activatlon anneal) 一二氧化石夕膜，並且在經活化 之該二氧化矽膜上沉積及氫化退火㈣阿咖10n避al)一氮 化矽膜而形成。 Φ 4’如申请專利範圍第丨項所述之液晶顯示裝置的製造方法，其中 該保瘦膜係藉由在具有該汲極區域之該基板上依序地形成一 二氧化矽膜和一氮化矽膜，並在退火(anneal)該氮化矽膜和該二 乳化石夕膜之後同時執行該二氧化石夕膜的活化程序和該氮化矽 膜的氫化程序而形成。 5·如申料概圍第丨項所述之液晶|R示裝置的製造方法，其中 該保蠖膜係藉由在具有該汲極區域之該基板上依序地形成一鲁 —氧化梦膜、一氮化石夕膜以及一二氧化石夕膜而形成。 6’如申請翻範圍第i項所述之液晶齡裝置的製造方法，其中 於形成邊保護膜之後更包含形成一障壁金屬圖案，其係填充於 破第一和第二接觸孔内。 7 &gt; 如申明專利範圍第6項所述之液晶顯示裝置的製造方法，其中 戎障壁金屬圖案係藉由形成一障壁金屬膜於該保護膜上以覆 36 年i修(更)正替換頁 1 二二和°玄弟—接觸孔’沉積一遮光膜於包含該障壁金屬膜 以土反上’灰化(ashing)該遮光膜以形成一爆露該障 且殘留於該第一和該第—蜀膜 膜圖安所^ 接觸孔内之遮光膜圖案，蝕刻該遮光. 成。 以及錄該遮光膜圖案而形 8.如申請專利範圍第μ 4广辟入间▲ 、心，夜日日頌不裝置的製造方法，其中 口玄IV土至屬暝係由鉬膜所形成。 9·如申請專利範圍第7項所述之 „ (日日.、'、員不裝置的製造方法》其中 攝壁金屬膜的厚度介於0.5微米至！微米。 10. 如申請專利範圍第i項 、 _ ，夜日日頌不裝置的製造方法，其中 於形成该金屬膜之步驟後，更 上。 小成—絕緣膜於該金屬膜 11. 如申請專利範圍第U項所述之 日”、、員不衣置的製造方法，其 :之步驟前’更包含選擇性地 中於餘刻该金屬膜和該透明導電 第—絕緣圖案於該晝素部 蝕刻該絕緣膜以形成該晝素部之 第二絕緣圖案於該晝素 晝素部之—薄膜電晶體區 部之該薄膜電晶體區域和 之該源電接上，以及形成該晝I部之 部之該汲電極上。 其包含有： 妓備一絕緣基板，其中定義出 12. —種液晶顯示裝置的製造方法， 域、一閘極墊部，以及佈設於讀查本 旦；3% 該閘極墊部間之一密封線部； 37 1332205 薄 膜電==抑她6輪增辆細之該 开乂成該畫素部之一閘電極於該主動層上； 开〆成該晝素部之一源極 一間極胁觀絲板之—雜^麟上，亚簡時形成 ”=:Γ部之—源極區域以及該畫素部之，區域 動層巾，並麵她«素部之刻輪的兩側； 开V成L 3帛-和第二接觸孔之—保護膜以及一開口部 於具有該晝素部之該祕區域之該基板上，該第—和第二接觸 孔刀別曝路ttj該晝素部之該祕區域和該晝素部之該沒極區 域，且該開口部曝露出該閘極墊； 及 依序地形成-透料電膜以及—金屬膜於該保護 膜上；以 選擇性地钱刻該金屬膜以及該透明導電膜，以形成該晝素 部之-源電極圖案/該畫素部之一源電極，其係依序沉積以覆 蓋該第一接觸孔’形成該晝素部之一及電極圖案，該晝素部之 -及電極，其係依序沉積以覆蓋該第二接觸孔，以及形成該問 極塾部之-透明導電膜圖案/該閘極墊部之一金屬膜圖案，其 係依序沉積以覆蓋該開口部以及該密封線部. 其中該晝素部之顧、電極_/該晝素部之該源電極以 及該晝素部之該没電極圖案/該晝素部之該没電極，以及該閘 38 !)9 !)91332265 1) March 1st, 1% repair (more) replacement page '· X. Patent application scope · 1· A method of manufacturing a liquid crystal display device, comprising: a preparation-insulating substrate, wherein a pixel portion is defined a thin film transistor region; forming an active layer over the insulating substrate to cover the thin film transistor region of the germanium portion; forming a gate electrode of the S-sinusoidal portion on the active layer; a source region of the pixel portion and a drain region of the pixel portion in the active layer and on both sides of the gate electrode of the pixel portion; forming one of the first and second contact holes a protective film on the substrate having the polar region of the element portion, wherein the first and second contact holes respectively expose the source region of the dendrite portion and the drain region of the pixel portion Forming a transparent conductive film and a metal film on the protective film in sequence; and Φ selects the metal film and the transparent conductive film to form the original portion of the halogen portion. a source electrode of a pole figure wood/enamel portion, which is sequentially deposited to cover the first contact hole, and one of the pixel portions of the pixel portion/the pixel portion and the electrode And sequentially depositing to cover the source electrode of the element portion of the second contact hole, the source electrode of the element portion, and the neon/case/difficult ship electrode system of the pixel portion The mask is formed by diffraction exposure. 35 1332265 2. The manufacturing method according to claim 1, wherein: in the formation of the gate electrode of the 昼I portion, further comprising forming a sinter insulating film on the active layer On the substrate. 3. The method of manufacturing a liquid crystal display device according to the above-mentioned item, wherein the film is deposited and activated by the substrate in the drain region having the element portion. (activatlon anneal) A dioxide dioxide film formed on the activated cerium oxide film and hydrogenated and annealed (d) Aca 10n a) tantalum nitride film. The method for manufacturing a liquid crystal display device according to the above aspect of the invention, wherein the thin film is formed by sequentially forming a hafnium oxide film and a nitrogen on the substrate having the drain region. The ruthenium film is formed, and after the annealing of the tantalum nitride film and the emulsified film, the activation process of the ruthenium dioxide film and the hydrogenation process of the ruthenium nitride film are simultaneously performed. 5. The method of manufacturing a liquid crystal display device according to the above aspect, wherein the protective film is formed by sequentially forming a Lu-Oxide Dream Film on the substrate having the drain region. , a nitride film and a dioxide dioxide film formed. The method of manufacturing a liquid crystal age device according to the above aspect, wherein the forming of the edge protective film further comprises forming a barrier metal pattern which is filled in the first and second contact holes. The method for manufacturing a liquid crystal display device according to claim 6, wherein the barrier metal pattern is formed by forming a barrier metal film on the protective film to cover a 36-year-old (more) replacement page. 122 and °Xuandi-contact hole' depositing a light-shielding film to "ash" the light-shielding film on the metal film containing the barrier to form an explosion of the barrier and remaining in the first and the first —蜀膜膜图安^ The pattern of the light-shielding film in the contact hole, etch the shading. And the shape of the light-shielding film is recorded. 8. As in the patent application scope, the manufacturing method of the ▲, the heart, and the night is not installed, and the sputum is formed by the molybdenum film. 9· As stated in item 7 of the scope of application for patents (days, ', manufacturing methods for non-devices', the thickness of the metal film of the wall is between 0.5 μm and μm. 10. If the scope of patent application is i Item, _, a manufacturing method of a device that is not installed in the night, wherein the step of forming the metal film is further performed. The small-insulating film is on the metal film 11. As described in the U of the patent application scope" And a method of manufacturing the device, wherein: the step of: further comprises selectively etching the metal film and the transparent conductive first-insulating pattern to etch the insulating film on the element to form the element a second insulation pattern is electrically connected to the thin film transistor region of the thin film transistor portion of the halogen element portion and the source, and the germanium electrode forming the portion of the germanium I portion. There is: an insulating substrate, which defines a manufacturing method of a liquid crystal display device, a domain, a gate pad, and a layout for reading the original; 3% of the sealing pad between the gate pads Department; 37 1332205 Thin film electricity == inhibit her 6 rounds Finely opening the gate electrode of the pixel part to the active layer; opening the source of one of the element parts of the elemental part of the elemental nucleus =: the part of the crotch - the source area and the element of the picture, the area of the layer of the layer, and the sides of the wheel of the engraving of the part of the ring; open V into L 3 帛 - and the second contact hole - protective film And an opening portion on the substrate having the secret region of the element portion, the first and second contact hole knives ttj the secret region of the element portion and the electrodeless portion of the element portion And the opening portion exposes the gate pad; and sequentially forming a dielectric film and a metal film on the protective film; selectively etching the metal film and the transparent conductive film to form the a source electrode of the source portion or a source electrode of the pixel portion, which is sequentially deposited to cover the first contact hole 'forming one of the pixel portion and the electrode pattern, and the electrode portion and the electrode And sequentially depositing to cover the second contact hole, and forming a transparent conductive film pattern/one of the gate pad a film pattern sequentially deposited to cover the opening portion and the sealing line portion. wherein the electrode portion, the electrode_/the source electrode of the element portion, and the electrode pattern of the element portion The electrode of the 昼素部, and the brake 38 !)9 !)9 月1 %修(更)jE替換頁 °墊4之4透日料電膜醜/該閘極整部之該金屬膜圖案，係 利用一單一光罩進行繞射曝光而形成。 〃 ’丁' 如申。月專利乾圍第12綱述之液晶顯示裝置的製造方法，其 I於形成該閘轉部之該透明導電案/極墊部之該 :圖木之步驟後，更包含選擇性地钱刻該鬧極塾部之該金 屬膜圖案以曝露該密封線部，並形成—密封線於該密躲部 中0 一種液晶顯示裝置的製造方法，其包含有： 製備-絕緣基板，其中定義出—畫素部之一薄膜電晶體區 成以及-電路部’該電路部被劃分為—η通道薄膜電晶體區域 以及一p通道薄膜電晶體區域； 形成弟-、第二以及第三主動層於該基板上之同—層結 構中’以力別覆盍該晝素部之該薄膜電晶體區域、該η通道薄 膜電晶體區域以及該ρ通道_電晶體區域； 形成該畫素部之-第-閘電極於該第三主動層上； 依序地形成該電路狀1〜源麵如及該電路部之 -第-没麵域於該第三主麵巾，並分別位於該電路部之該 第一閘電極的兩側； 形成該畫素部之-閘電極以該電路部之—第二間電極 於該第一和該第二主動層上； 形成該畫素部之-源極區知及該晝素部之―没極區域 頁 ------ j 兩側 於=第-主動層中’並分別位於該晝素部之該閘電極的 5 Μ开/成-亥电路部之一第二源極區域以及該電路部之一第二 沒極區域於該第二主動層中，並分別位於該電路部之 ; 電極的兩側； 、弟一閘 的保講膜1 ^帛—、H四、第五及第六接觸孔 \7又該電路部之該第二&gt;及極區域之該基板上，其中 “弟帛—第二、第四、第五及第六接觸孔係分別曝露出 該畫素部之該源極區域、兮佥丰 、 兮第素权麵極_、該電路部之 該弟-源郝域、該電路部之該第二沒極區域 第一源極區域以及該電路部之該第-祕區域；狀該 忙序也$成透明導電膜以及—金屬膜於該保護膜上；以 及 選擇性地_該金屬膜.以及該透明導電膜， 鄯之，源電極圖案/該畫素、‘該旦素 命抒圍安/ 魂電極、該電路部之一第- 源電極_/該電路部之H電極 弟- 電極圖案/該電路部之 ㊉ 4路部之-第 以裹篆謗第一、第-以及冰 極’其係分別依序沉積 以 $ I从経孔， 淡該晝素部之，極、該電路; 圖索/该電路部之一第二沒電極·，以 弟一U 索/該電路部之—第—汲電極，其::部之—汲電極圖 ,、第叫及第續麻。、说私積以覆蓋； 40 1332265 沴(更)正替換頁 15. 如申請專利範圍第14項所述之液晶顯示裝置的製造方法，其 中於开ν成該保護膜之步驟後，更包含形成一障壁金屬圖案，係 填充於§玄第一和第.二接觸孔中。 16. 如申請專利範圍第15項所述之液晶顯示装置的製造方法，其 ^玄障壁金屬圖案係藉由形成—障壁金屬膜於該保護膜上以 復二該第—和弟二接觸孔’沉積一遮光膜於具有該障壁金屬膜 、=板上’灰化麵光膜以形成—曝露該障壁金屬膜且殘留 和第二接觸孔内之遮光膜圖案，透過該遮光膜圖案钱 ※雜壁金屬膜，以及移除該遮光顧案而形成。 如申叫專利範圍第I6項所述之液晶顯示裝 之t«電極圖案/該畫素部之 、 v弟-#、電_案/該電路部之 电路奴 第—源°Λ 一/原、電極、該電路部〇 h極圖案/該電路部之該第I之該 電極圖案/碎晝素部之該 雷電極、該晝素部之該及 荦/兮&amp; 电極該電路部之气第+ .木/該電路部之該第二⑼ 丨之為—及電極圖 圖案/t亥雷路邻之μ 及該笔路部之該第〜及電 田。路口Ρ之该乐-及電 样 叉甩極 單〜 林進行繞射曝光而形成。4依序沉積並利用 19’—種液晶顯示裝置，其包含有‘ 41 1 年3.月1 $修(更)正替換g —巴緣基板，其係疋義有—畫素部之—薄膜電晶體區域，· 曰~主動層，娜成於縣板上以覆M財素部之該薄膜電 曰曰肢*區; 該畫素部之一閘電極，係形成於該主動層上； =畫素部之—雜區域以及該畫素部之—汲極區域係形 又二主y中，並分別位於該晝素部之該閘電極的兩側； 保護膜’其包含一第一和第二接觸孔，並形成於具有該 A…之該汲極區域之該基板上，其中該 別曝露Ψ兮+主 禾接陶孔分 域^以2 該源極區域以及該晝素部之該汲極區 =素部之—源電極圖案/該晝素部之一源電極，其係依 =積於該保護膜上以覆蓋該第—接觸孔；以及該晝素部之— 圖案/該晝素部之一及電極，其係依序沉積於該保護膜 乂覆盍该第二接觸孔， -中相電極之墊部的—透 20•成於該密封線部與該閑極墊部之外靡中。 . =專彻爾19項所述之液晶顯示裝置，更包含—絕緣 及=沉積於該源電極上，以及—第二絕緣圖案，係沉積於該 X电極之上。. · 绝緣19 轉置’更包含—閑極 4介於該晝素部之該絲層和綱電極間。 42 1332265 _ : 汾年3.月！％修便)正替換頁 A t L, -----— ·, 22·如申請專利範圍第W項所述之液晶顯示装置，其中該保護膜 • 係由一單—氮化石夕膜、依序沉積之一二氧化石夕膜氮化石夕膜 以及依序沉積之-二氧化賴/—氮切膜八二氧化石夕膜 其中任一而形成。 23.如申請專利範圍第19項所述之液晶顯示裝置，更包含一障壁 金屬膜，係形成於該第一和該第二接觸孔中’且介於該晝素部 之該源極區域和㈣電極圖額以及該晝素部之該祕區域 和該及電極圖案間。 24‘如申請專利範圍第23項所述之液晶顯示裝置，其中該障壁金 屬膜係由鉬膜所形成。 25. 如申請專利範圍第19項所述之液晶顯示裝置，其中該晝素部 之該源電簡案/該畫素部之紐電極圖案係由透明導電膜 所形成’且該晝素部之該源電極/該冑素部之②電極係由金屬 春 膜所形成。 26. 如申請專利範圍第19項所述之液晶顯示裝置，其中該書素部 之5玄/及電極圖案係為一晝素電極。 27. —種液晶顯示裝置，其包含有： • —絕緣基板，其定義有—晝素部之—軸電晶體區域、_ 閘極墊部，以及佈設於該晝切之該_電晶體區域和該閑接 墊部間之一密封線部； 一主動層，係形成於該絕緣基板上以覆蓋該畫素部之該薄 43 膜電晶體區域； 一閘電極以及一閘極塾’係分別形成於該主動層上以及兮 閘極塾部； . 該晝素部之一源極區域以及該晝素部之一汲極區域，其中 該源極區域以及該汲極區域係位於該主動層中該晝素部之該 閘電極兩側； -保護膜，其包含—第—和第二接觸孔以及1 口部，且 =具有該晝素部域之該絕緣基板上，其中該第一 口乐-接觸孔分顺露出該晝素部之該祕區域 部之該及麵域，且_ 口部曝露__墊； 該晝素部之1、電極圖案/該晝素部之 5沉積以覆蓋該第1觸孔；該晝素部之-没電極圖荦 序沉積以覆蓋該第二接觸孔 線部；2 31明導電膜圖案’其係覆蓋該開口部以及該密封 閘極:=:如爾膜圖案’係形成於該密封線部與該 .=3利Γ第27項所述之液晶顯示裝置，更包含-障壁 部之係形成於該第一和第二接觸孔中，.且介於該晝素 分1(1域和起電極__及該晝素部之該沒極區 ^和垓汲電極圖案間。 ^32265 年1曰饺(更)正替換頁I 29.如申請專利範圍第2S項所述之液 ^ 屬膜係由翻膜所形成。 U衣置’其中該障壁金 30.如申請專利範圍第27項所述之液晶顯示裝㈤ 之該源電極圖案、該畫素 ί ,、令該晝素部 丁 及電極圖奉 該透明導電膜圖案係由透明導電膜所形成^鬧極墊部之 源電極和該畫素部之_ 7亚且该晝素部之該 3】# 1 1之I及電接係由金屬膜所形成。 轧一種液晶顯示裝置，其包含有： 成 —絕緣基板，被定義有—查喜 一 閉極墊部、—穷封線— 之—缚膜電晶體區域、- 山观相及-電路部，其中 —η通道薄膜雷曰；a* F 4被里丨]分為 竹㈣Γ 域以及—p通道薄膜電晶體區域4中 =卩佈設於該畫素部之該_電晶體_和該閑極塾 ，士播由弟一、弟一和第三主動層’其係位於該基板上之同-声 ^ ，分別覆蓋該晝素部之該薄膜電晶體區域、該n通道薄 膜电晶體區域以及該P通道薄膜電晶體區域；. 該畫素部之-閑電極以及該電路部之一第—和第二問電 極，分別形成於該第一、第三和第二主動層上. 邊晝素部之-源極區域以及該晝素部之1極區域，係形 成於該第-主動層中，並分別位於該晝素部之該間電極的兩 側，該電路部之一第二源極區域以及該電路部 、 〜第 &gt;及極區 域，係形成於該第二主動層中，並分別位於該電路部之該第二 45 更)正雜頁 閉電極的兩側，以及該電路部之 &lt;一第—^ 源極區域以及該雷路邱 弟及極區域，係形成於該第三 。路。Ρ ‘部之該第—閘電極H 小亚分別位於該 包路部之該第—閘電極的兩侧； —保護膜，係形成於呈带 基板上，其包含_第—、第」二：亥第一没極區域之該 =’分別曝露出該晝素部之該=區及第六接 :Τ該電路部之該第二源極區域 ：-素部之該汲極 ν、该電路部之該第_源極區域，以及b部之該第二沒極區 區域；以及 \電路部之該第一汲極 该畫素部之—源電賴案/該晝素 沉積以覆蓋該第-接觸孔；該書”之之—源電極，係依序 部之一振電極，係依序沉積以覆蓋舞二電極圖案/該畫素 一第二源電極圖案/該電路部之—麵孔；該電路部之 覆蓋該第三_孔；該電路部之—L、n係依序沉積以 之一第二轉極，係依序沉積哺蓋:7_案/該電路部 之一第1、電_案/該電路部之—/叫觸孔]該電路部 以覆蓋該第五_孔；以及該電路部之〜源電極，係依序沉積 部之~宽_. 及電極圖荦/今+ 卑&amp;電極，係依序沉積以覆蓋 路 /、中’該閘極墊部之—透明.導電安、1孔’ 線部與謗閘極墊部之外廓中。 、水，係形成於該密封 如申請專概圍第31销述之液晶顯年 、衣置，更包含形成一 46 32. '—Ά宫翻 障壁金屬職，其# sj ^ ^ 〜充於該第—、外_ 以及弟六接觸孔内，龙且八 罘一、第三、第四、第五 晝素部之該源電極圖_ 1續素部之該源極區域和該 之該汲電極圖案間、讀電:里素°卩之該汲極區域和該畫素部 該第，電極圖案間、源極區域和該電路部之 之該第二汲電極圖_、_ j 沒極區域和該電路部 部之該第-源電接圖宰門&quot;包路部之該第—源極區域和該電路 該電路部之該第—沒電_2該電路部之該第一汲極區域和 Ο ο A- Λ ^ 圖水間。 如申#專利範圍第32項 屬圖案係由_所形成。、&quot;&quot;之液晶顯示裝置，其中該障壁金 ㈣請專利範圍第〜 之_電極圖案/該晝素部，不裝置，其中該晝素部 二源電極圖案/該電路部及電極圖案、該電路部之該第 =-源電極圖案心電路部 極、讀電路部之驾;^之該㈣極/職素部之該汲電 及该電路部之該第-源電極A °㉝二沒電極，以 金屬犋所形成。 。卩之该弟—汲電極係由 47Month 1% repair (more) jE replacement page ° 4 pad 4 through the solar film ugly / the metal film pattern of the entire gate is formed by a single mask for diffraction exposure. ’ ’ Ding’ is Shen. The method for manufacturing a liquid crystal display device according to the fourth aspect of the patent is as follows: after the step of forming the transparent conductive case/pole pad portion of the gate turn portion: the step of the figure, the method further includes selectively The metal film pattern of the pole portion is exposed to expose the sealing line portion, and a sealing line is formed in the hiding portion. The manufacturing method of the liquid crystal display device comprises: preparing an insulating substrate, wherein the drawing is defined a thin film transistor region and a circuit portion of the element portion are divided into an n-channel thin film transistor region and a p-channel thin film transistor region; forming a second-, second, and third active layer on the substrate In the same layer-layer structure, the thin film transistor region, the n-channel thin film transistor region, and the p-channel-transistor region of the pixel portion are covered by force; the first gate of the pixel portion is formed Electrodes are disposed on the third active layer; sequentially forming the circuit-like 1 - source surface and the - undone area of the circuit portion in the third main surface, and respectively located at the first portion of the circuit portion The two sides of the gate electrode; forming the pixel part - The electrode is disposed on the first and the second active layer by the second electrode of the circuit portion; the source region forming the pixel portion is known as the "no-polar region page" of the pixel portion---- - j is in both the first active region and the second source region of the circuit portion of the gate electrode of the gate portion The area is in the second active layer, and is respectively located in the circuit part; on both sides of the electrode; the first layer of the brake film 1 ^ 帛 -, H four, the fifth and sixth contact holes \ 7 and the circuit On the substrate of the second portion and the polar region, wherein "the second, fourth, fifth, and sixth contact holes respectively expose the source region of the pixel portion, a first element region of the second portion of the circuit portion and the first source region of the second portion of the circuit portion and the first secret region of the circuit portion Also forming a transparent conductive film and a metal film on the protective film; and selectively _ the metal film. and the transparent conductive film, 鄯, source electrode pattern / Pixel, 'the one's life, the singularity of the circuit, one of the circuit parts, the source electrode _/ the H electrode of the circuit part - the electrode pattern / the circuit part of the 10th section - the first篆谤The first, the first, and the ice pole' are deposited sequentially in order to $ I from the pupil, the light of the element, the pole, the circuit; the second / the electrode of the circuit part, The brother of a U cable / the first part of the circuit - the first electrode, which:: the part of the - electrode diagram, the first and the third, and the private product to cover; 40 1332265 沴 (more) replacement page 15. The method of manufacturing a liquid crystal display device according to claim 14, wherein after the step of forming the protective film, the method further comprises forming a barrier metal pattern, which is filled in § Xuan first and second. In the contact hole. 16. The method of fabricating a liquid crystal display device according to claim 15, wherein the metal barrier pattern is formed by forming a barrier metal film on the protective film to multiplex the first and second contact holes. Depositing a light-shielding film on the barrier metal film, the on-board 'ashing surface light film to form the light-shielding film pattern exposed to the barrier metal film and remaining in the second contact hole, and transmitting the light-shielding film pattern A metal film is formed, and the shading is removed. For example, the t«electrode pattern of the liquid crystal display device described in the patent range No. I6, the v---, the electric circuit, the circuit slave of the circuit, the source, the source, the original The electrode, the circuit portion, the 极h pole pattern, the first electrode pattern of the first portion of the circuit portion, the lightning electrode of the ruthenium portion, the 荦/兮& The second (9) of the + / wood circuit portion is - and the electrode pattern pattern / t Hailei Road neighboring μ and the pen and the portion of the pen and the field. The intersection of the music - and the sample of the fork 甩 single ~ forest is formed by diffraction exposure. 4 sequentially depositing and utilizing a 19'-type liquid crystal display device, which includes '41 1 year 3. month 1 $ repair (more) is replacing g-ba margin substrate, which is a thin film of The transistor region, · 曰 ~ active layer, Na Cheng on the county plate to cover the M electric component of the thin film electric limb * area; the gate electrode of the picture is formed on the active layer; The pixel region and the pixel region of the pixel portion are two main y and are respectively located on both sides of the gate electrode of the pixel portion; the protective film 'containing a first and a a contact hole formed on the substrate having the drain region of the A, wherein the other exposed germanium + main interconnected ceramic domain is divided by 2 the source region and the germanium portion a polar region = a source electrode pattern / a source electrode of the pixel portion, which is based on the protective film to cover the first contact hole; and the pattern of the halogen portion - the pattern And an electrode, which is sequentially deposited on the protective film to cover the second contact hole, and the bottom portion of the middle phase electrode is formed in the sealing line portion With the spare pole pad outside the squat. The liquid crystal display device of claim 19, further comprising - insulating and = deposited on the source electrode, and - a second insulating pattern deposited on the X electrode. • Insulation 19 transpose 'more includes - idle pole 4 is between the silk layer and the electrode of the element. 42 1332265 _ : Three years of the following year! The liquid crystal display device of the above-mentioned claim, wherein the protective film is composed of a single-nitridium film, One of the dioxide dioxide cerium nitride nitride film and the sequentially deposited-dioxide/nitrogen-cut film octahydrate dioxide film are sequentially deposited. The liquid crystal display device of claim 19, further comprising a barrier metal film formed in the first and second contact holes and interposed between the source region of the pixel portion and (4) The electrode map and the secret area of the element and the electrode pattern. The liquid crystal display device of claim 23, wherein the barrier metal film is formed of a molybdenum film. 25. The liquid crystal display device of claim 19, wherein the source electric pattern of the halogen portion/the contact electrode pattern of the pixel portion is formed by a transparent conductive film and the element portion The source electrode / the two electrodes of the halogen portion are formed of a metal spring film. 26. The liquid crystal display device of claim 19, wherein the pixel portion of the surface portion is a halogen electrode. 27. A liquid crystal display device comprising: - an insulating substrate defining a - - - - - - - - - - - - - - - - - - - - - - - - - a sealing line portion between the idle pads; an active layer formed on the insulating substrate to cover the thin film transistor region of the pixel portion; a gate electrode and a gate electrode are respectively formed And a gate region of the pixel portion, wherein the source region and the drain region are located in the active layer a side of the gate electrode of the halogen portion; a protective film comprising - a first and a second contact hole and a mouth portion, and = the insulating substrate having the pixel portion, wherein the first mouth - The contact hole is divided to expose the area of the secret portion of the element portion, and the mouth portion is exposed to the __ pad; the electrode pattern of the element portion is deposited to cover the first portion 1 contact hole; the electrode portion of the element is deposited to cover the second contact hole portion a thin conductive film pattern </ RTI> covering the opening portion and the sealing gate: =: a film pattern is formed in the sealing line portion and the liquid crystal display device according to the item 27, a further including a barrier portion formed in the first and second contact holes, and interposed between the halogen component 1 (1 domain and the electrode __ and the non-polar region of the pixel portion) Between the electrode patterns. ^32265 1曰 dumplings (more) replacement page I 29. The liquid film system described in item 2S of the patent application is formed by tumbling film. U clothing is placed in which the barrier gold 30. The source electrode pattern of the liquid crystal display device (5) according to claim 27, the pixel element, and the electrode of the transparent conductive film are formed by a transparent conductive film. The source electrode of the pole pad portion and the pixel portion of the pixel portion are formed of a metal film. The liquid crystal display device includes: - Insulating substrate, which is defined as - Chaxi a closed-pole pad, - a poor seal line - a bonded film transistor region, - a mountain phase and a circuit portion, Wherein - η channel thin film thunder; a* F 4 is divided into bamboo (four) Γ domain and - p channel thin film transistor region 4 = 卩 is disposed in the pixel portion of the _ transistor _ and the idle pole 塾, the singer, the younger brother, the third active layer, and the third active layer, which are located on the substrate, respectively covering the thin film transistor region, the n-channel thin film transistor region, and the P a channel thin film transistor region; the pixel-free electrode and one of the circuit portion first and second interrogating electrodes are formed on the first, third and second active layers, respectively a source region and a one-pole region of the pixel portion are formed in the first active layer, and are respectively located on both sides of the electrode of the pixel portion, and a second source region of the circuit portion and The circuit portion, the ~th portion, and the pole region are formed in the second active layer, and are respectively located on the two sides of the second portion of the circuit portion, and on both sides of the closed electrode, and the portion of the circuit portion A first-^ source region and the Leilu Qiudi and polar regions are formed in the third. road. The first gate electrode H of the Ρ ' portion is located on both sides of the first gate electrode of the package portion; the protective film is formed on the substrate, which includes _--, and the second: The first in the first infinite region of the sea = 'excepting the = region and the sixth connection of the element portion respectively: the second source region of the circuit portion: the buckle of the element portion, the circuit portion The first source region, and the second non-polar region of the b portion; and the first drain of the circuit portion of the pixel portion - the source of the pixel / the pixel deposition to cover the first a contact hole; the source electrode of the book is a vibrating electrode of a sequence portion, which is sequentially deposited to cover the dancing electrode pattern/the pixel-second source electrode pattern/the portion of the circuit portion; The circuit portion covers the third hole; the L- and n-series of the circuit portion are sequentially deposited with one of the second rotating poles, and are sequentially deposited and fed: 7_ case/one of the circuit portion The _ case / the circuit portion - / called the contact hole] the circuit portion to cover the fifth _ hole; and the circuit portion of the ~ source electrode, the sequential deposition portion of the width _. / 今 + 卑 &amp; electrodes, deposited in order to cover the road /, the 'the gate pad's - transparent. Conductive security, 1 hole' line and the 谤 gate pad outside the profile. It is formed in the seal, such as the liquid crystal display year and clothing set, which is quoted in the 31st section of the application. It also includes the formation of a 46 32. '-Ά 翻 翻 金属 金属 金属 金属 , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , , In the outer _ and the sixth contact hole, the source electrode of the dragon and the gossip, the third, the fourth, and the fifth element, and the source region of the continuation portion and the 汲 electrode pattern, Reading power: the drain region of the surface and the pixel portion, the electrode pattern, the source region, and the second electrode pattern of the circuit portion _, _ j immersion region and the circuit portion The first source region of the portion of the circuit and the first source region of the circuit portion of the circuit portion and the first drain region of the circuit portion A- Λ ^ 图水间. For example, the 32th item of the patent scope is formed by _., &quot;&quot; liquid crystal display device, wherein the barrier gold (four) please patent scope ～ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ The driving of the (four) pole/professional part and the first source electrode A °33 of the circuit part are not formed by electrodes, and are formed by metal crucibles.
TW095149352A 2006-06-30 2006-12-27 Liquid crystal display and method for fabricating the same TWI332265B (en)

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