TW201137478A - TFT array substrate and LCD panel - Google Patents

Abstract

A TFT array substrate includes gate lines, data lines, and first and second common lines. The gate lines are disposed on a transparent substrate. The data lines cross the gate lines. There is no pixel region defined by adjacent two of gate lines and adjacent two of the data lines. There are two pixel regions being left and right pixel region defined by adjacent two of gate lines and adjacent two of the data lines. The first common lines are parallel to the gate lines. The second common lines are parallel to the data lines and electrically connected to the first common lines, wherein each second common line is disposed between the left and right pixel regions.

Description

201137478 VI. Description of the Invention: [Technical Field] The present invention provides a liquid crystal display, in particular, a thin film transistor array substrate 5 of a liquid crystal panel of a liquid crystal display, which has a common line of a mesh structure to reduce resistance, The signal delay effect caused by the electricity valley. [Prior Art] In general, a liquid crystal display (LCD) can provide a light signal corresponding to the data of the surface to the liquid crystal cell (Liquid Crystal Cell) separately, and the light of the liquid crystal cell is 5 weeks. The penetration rate is checked for two defects. The liquid crystal display includes: a liquid crystal panel with a matrix array 2 liquid crystal panel, and an integrated circuit for driving (Integr=ted

Circuit, 1C). The liquid crystal panel further includes: a color filter substrate, a thin film transistor array substrate corresponding to the color filter substrate, and a sandwich between the color light guide substrate and the thin film transistor array substrate Liquid crystal layer. The thin film transistor array substrate comprises: for transmitting the data provided by the data driving integrated circuit 2 . , to the data line of the liquid crystal cell, and the polar line between the scanning cat signals provided by the gate driving circuit, wherein the liquid crystal cell is defined by the data lines and the gate lines which are staggered with each other. Gate 201137478 The pole drive integrated circuit sequentially supplies the scan signal to the interpole line, and sequentially selects the liquid crystal cells one by one. In addition, the data-driven integrated circuit supplies the data signal to the liquid crystal cell of the selected gate line. 5 Referring to Figure 1, which is a layout of a conventional halogen structure, which is also referred to as a storage capacitor on a common line or a common electrode (Cs Qn CQ_n), which is configured And a substrate comprising at least a gate line 10, a data line 11, and a thin film transistor 12. The halogen region 1 〇 $ is defined by the extended gate line and the data line, and the gate line 10 is extended by one and the second direction is extended.

The extension of the younger brother, the same as T 1 - 12 , is formed by a first etching process. On the thunder &gt; into. Power-on 13 electrical connection with the dielectric layer between the halogen electrodes 17. A part of the common line of the lower electrode, _ ^ and with the gate line 10, the idle pole 1: the metal layer is exposed, developed, and the long pole 17 is in contact with the window 18 201137478 "with the data line U, the source 122, the immersion 123 is the same, both: a second metal layer is formed by exposure, development, engraving and other processes. Further, a dummy insulating layer is disposed between the first metal layer and the second metal layer, and a passivation protective layer is disposed between the second metal layer and the halogen electrode 13. 10 15 The second month of the month, which is the matrix of the traditional structure of the prime minister. In the conventional matrix of the matrix, the common lines are arranged along the direction of the younger brother and are electrically connected to each other. Therefore, in the common line in the conventional matrix, the signal delay effect caused by the resistance and capacitance is quite obvious, which makes the quality of the surface low. In summary, it is necessary to propose a thin film transistor array substrate of a liquid crystal panel, which is designed to reduce the resistance-capacitance problem in the prior art, so as to provide a high-quality liquid crystal display of the public. . SUMMARY OF THE INVENTION [In the first to fifth embodiments of the present invention, a thin line, a data line, a first and a second t-plate, and a plurality of idler transparent substrates, "two; inter-polar lines are arranged in &amp; The number of the eight-in-two (five) pole lines is N+1 on the substrate, to the Lin. The number of the tributary line and the inter-polar line intersect when the field is even, the Nth to the second gate 20 201137478 . There is no defined pixel region between the line and the two adjacent data lines. When N is an odd number, two elements are defined between the Nth to N+1th gate lines and the two adjacent data lines. a region, which is a left-handed region and a right-halogen region. The first common line is parallel to the gate line. The second common line is parallel to the data line, and is electrically connected to the first common line, wherein each second common line The second common line of the thin film transistor array substrate is electrically connected to the halogen electrode of the left halogen region and the halogen electrode of the right halogen region. In the first to fifth embodiments, the second common lines of the thin film transistor array substrate are electrically connected to the a first j = line, whereby the first common line and the second common line are formed. The mesh structure, so as to reduce the resistance of the common line The above-mentioned and other objects, features and advantages of the present invention will become more apparent and obvious. The following description of the preferred embodiments, together with the drawings, will be described in detail as follows. The technical content and features of the present invention can be understood and understood by those skilled in the art. [Embodiment] FIG. 3 is an embodiment of the present invention, and FIG. The section of the section line M' is not intended to be shown. Referring to Figure 3, the structure of the elemental electrode includes: a gate 201137478 pole line 30, a data line 3 1 , a first common line 32, a second common line 33 and a thin film transistor 34. The gate line 30 is disposed along a first direction, and the data line 31 is disposed along a second direction, and the second direction is approximately perpendicular to the first direction. The line 32 is parallel to the gate line 30, and the second common line 33 intersects the gate line 30. The thin film transistor 34 includes a gate 340, a channel layer 341, a source 342, and a drain 343. The pole 340 is electrically connected to the gate line 30, and the source 342 and the data line 31 are electrically connected. Connected, the drain 343 is electrically connected to the halogen electrode 35 through the contact hole 36. The gate line 30, the first common line 32 and the gate 340 are exposed, developed, and etched by a first metal layer. Formed, and the data line 31, the second common line 33, the source 342 and the drain 343 are formed by exposing, developing, and engraving a second metal layer. The interlayer 15 insulating layer 42 is disposed on the first metal layer and The first common line 32 and the second common line 33 are electrically connected through a conductive element 37, which is made of Indium Tin Oxide (ITO) and oxidized ( Indium Zinc Oxide, IZO), zinc-doped Zinc Oxide, and transparent conductive materials such as Gallium-Doped Zinc Oxide. The passivation protective layer 44 is disposed on the second common line, and has a first through hole 381 and a second through hole 201137478, such as 'the first through hole 381 corresponds to the first common line %, and the second through hole 382 Corresponding to the second common line 33. Therefore, the conductive element 37 is connected to the second common hole 33 through the first through hole 382 and the second common line 33. Fig. 4 is a schematic cross-sectional view taken along line u of Fig. 3. Therefore, it can be seen that the manufacturer of the liquid crystal display device provided by the present invention first provides a substrate 4 〇 which can be a glass substrate or a second anti-' secondly forming a gate 340, a gate line 30 10 15 ', and a through line. 32 is fastened to the substrate 3, the gate 340 is electrically connected to 'the first common line 32 is approximately the same as the gate line 30«a, ^. Ten. The gate 34〇, the gate line 30 and the first line, and the through line 32 belong to the same metal layer of the same &amp; 邳丨j, that is, the first metal layer is formed by exposure first. 42. On the substrate 4', a gate insulating layer η inter-electrode line 30 and the first common line 42 are formed to form a pass-through: a human, in the inter-electrode insulating channel layer 341, and In the surface of the channel layer 341, the south Guo W-ohmic contact layer (not shown), the source of the channel layer 341 and the next 343 electrical connection, such as the immersive data line 31 and The two ping gates of the insulating layer 42 are V, β, and 7, and the next ones are formed at, ^, ..., and the source 342 and the bungee 343 are located at the "layer 341 ^." 20 201137478 The line 33, the source 342 and the drain (4) (4) are formed in the same second metal layer, that is, formed by exposing, developing, and etching the second full layer. The source 342 is electrically connected to the data line 31 and the channel layer 341. The source 342 and the gate 343 form a thin film transistor 34. After the data line 31, the second common line 33, and the source (4) 10 15 =1343 are formed, a passivation layer is formed on the substrate 40 to cover the layer etched by the second metal layer, and then The passivation protective layer 44 and the passivation layer 42 are formed to correspond to the first and second common lines 32, and the passivation protective layer 44' is formed to form a - /Hai two common line The second through hole 382 of 33. Next, on the passivation protective layer 44, a hard conductive material is formed by a transparent conductive material = conductive element 37, which is permeable to the first via hole, and the conductive element 37 is made of indium tin oxide and conductive. Material made by 1 quotation gallium and other permeable basin matrix ~ cloth? 5, which is a schematic diagram of the structure of the present invention, the line 33:. The first common line 32 and the second common structure 1 are electrically connected to each other through the conductive element 37, and have a common structure to reduce the resistance-capacitance of the common line. 20 201137478 Fig. 6 is a schematic view showing the layout of the unitary structure of the present invention, and Fig. 7 is a schematic cross-sectional view showing the line κ_κ. For the sake of clearing, Fig. 6's structure includes: a free line 6〇, a data line 61, a first common line 62, a second common, a Yuan 63 and a thin film transistor 64. The gate line is disposed along a first direction, and the data line 61 is disposed along a second direction and the second direction is approximately perpendicular to the first direction. The 10th common line 62 is parallel to the gate line 6〇, and the second common line 63 intersects the closed line 60. The thin germanium transistor 64 includes a gate channel layer 641, a source (4), and a drain 643 ° closed pole 640 electrically connected to the gate line 60. The source 642 is electrically connected to the data line 61, and the pure 643 is The pixel electrode 65 is electrically connected through the contact hole 66. In the present embodiment, the gate, line 6 is composed of a first portion = and a second portion 602. The second common line 〇 only crosses the phase line 60, that is, traverses the first portion 6 〇 第 — - part 6 〇 2 between or traverses the first portion 6 0! The first portion 6〇1 is electrically connected to the second portion 6〇2, = the over-conducting conductive member 67, which is oxidized by the second? : Zinc, zinc oxide doping and zinc oxide doping. The gate line 60, the first common 62 first common line 63 and the gate 640 are formed by exposure 20 201137478 development, and a first metal layer is formed, and the data line 61 pole and the drain 643 are exposed, Development, money engraving: the formation of two genera. The passivation protective layer 74 is disposed on the [pass, spring, as shown in Fig. 7, and 681盥-筮一, s 丨 <00 \ Weidi-through hole flute-: one through hole 682, respectively corresponding to the gate The brother of the polar line 60 - 邛 ό ο ι and the second part 6 〇 2. Therefore, the 67 is formed by the first via 681 and the first vias 10 15 and 4 on the substrate 70 to form a gate insulating layer 72, which covers the interpole 640, the first portion 〇1, and the second portion. The brother-common line 62 and the second common line 63 are one. Next, on the interpole insulating layer 72, the shape = on the surface of the channel layer 641, and then a -European/妾 contact layer (not shown) is formed to enhance the channel layer 641 and the source 642 formed next. Electrical contact with 643 poles. The data line 61 is formed immediately above the gate insulating layer 72, and the source 642 and the drain 643 are located just above the channel layer 641. The data line 61, the source 642 and the drain 64/ are: the same second metal layer is formed by exposing, developing, etching the first metal layer of the meter, and the source 642 is electrically connected to the data line. . . The interpole _, the channel layer 641, the source 642 and = 643 constitute a thin film transistor 64. After forming the data line 61, the source 642 and the drain 6 of 20 201137478 , the second metal protective layer 74 is further covered on the substrate 7 to cover the structure of the material. Next, the voltage _74 and the gate insulating layer 72 are formed to correspond to the first portion 6 曰乂 corresponding to the second portion 6. 2 == 8 ? - in the passivation protective layer 74 The conductive element of the first, the second is made of a transparent conductive material, the second through hole, the electrical connection = the first through hole 681 and the branch 602. Among them, the b is divided into 6〇1 and the second part 10 15 20 indium zinc, and the oxidized word is made of emulsified indium tin and oxygen conductive material. Wei zinc is doped with gallium and the like, see the eighth «, which is another schematic diagram of the eight-matrix layout of the present invention. The first common line 62 and the first structure are electrically connected to each other and together form a mesh. The structure is used to reduce the resistance of the common line to the delay of the capacitance signal. Fig. 9 is a plan view of the thin film: crystallographic (TFT) array substrate 2 according to the first embodiment of the present invention. The thin film transistor array substrate 2 includes a --induced substrate 4 〇, a plurality of gate lines 2 〇, a plurality of data lines 2, a plurality of halogen electrodes 25, a plurality of first common lines 22, and a plurality of copies of the first common line Line 23 is connected to a thin film transistor. The transparent substrate 40 can be a glass substrate or a plastic substrate. The gates 12 201137478: two IT on the transparent substrate 40. The closed-poles (4) are sequentially: two '1st to N+1th gate lines 20 some of the information green ^ 5 透明 transparent substrate 4 ,, and N is a positive number. The t 1 intersects the gate lines 20, and the virtual line is closed. When &quot; even, the Nth; Dihai St. +1 idle line 3 0 and two adjacent # line 2! are not fixed between 10 15 I f any of the areas. When N is an odd number, the Nth 2nd N+1th gate line 2〇 and the two adjacent data lines 2丨 have two prime regions 41' which are left-handed regions 41a and =昼★ Prime region 41b. For example, at the time, between the second line of the second article f and the two adjacent data lines 21, there was no ambiguous area. When N is 】, the 1st to 2nd idle poles, the line 2〇 and the two adjacent data lines ^ are determined to have two halogen regions 41 'which are left-handed regions... and right: prime regions 41 b. The rest of the section can be deduced by analogy. The two gates, 'spring 20, are located between two adjacent halogen regions 41 arranged in the upper and lower positions, and are therefore referred to as dual gate line type quartz structures. - The first common line 22 is parallel to the gate line 2〇. The second = pass line 23 is parallel to the data line 21 and is electrically connected to the first common line 22. No data line is located between the left alum region 41a and the right alum region 41b, so each second pass, '23 can be located between the left alum region 41a and the right alum region 201137478 41b. This whole area is within 4!. - Each of the pen electrodes 25 is disposed at the respective 昼. The 汲 pole has a 汲-pole connection. The pixel with the port % and the electric field of the halogen electrode 25 is located in the pixel of the left chevron region electrode 25, and the pixel is between the adjacent elements. Having the 苐10 15 佥::spring 23, and having the capacitance between two adjacent 25 lts of the second common line 23 (ca---less than the capacitor without. The two adjacent pixel electrodes of::::? Between 25: the effect of the (c〇upling) between the denier electrodes 25 is smaller than the coupling effect of the 'two adjacent halogen electrodes 25 having the first common line 23 of D.' The effect between the pixel electrodes 25 can solve the problem of the bright line (bHghtline) and the dark line ((4) llnO. In the first embodiment, the gate lines 20 and the first common line 22 are exposed, developed, and etched. a first metal layer ^i) is formed, and the data lines 21 and the second common lines 23 are formed by exposing, developing, and etching a second metal layer (Μ2). The gate insulating layer (not shown) Between the first metal layer and the third metal layer, a passivation protective layer (not shown) is disposed on the second common line 23. The plurality of first through holes 2si are shaped 14 20 201137478 ::::: The pole insulation layer and the transition protection layer are respectively corresponding to the opening ^=-common line and the plurality of second through holes are added to the inside of her protective layer' and respectively correspond to the second, the through line 23. Each - The conductive element 27 is used to electrically (four) the second common line 23 via the whistle, the s, the secret, the through hole 281 and the second through hole 282. The conductive element 27 and the 昼 =:; Made of a transparent conductive material. In other words: Dan Guang: 2: 27 and the halogen electrode 25 can be formed simultaneously by the same exposure and display, so that the process time is not increased, and the data lines 21 and the second common line are further increased. 23 borrowed from the same two metal layers (M 2) and formed at the same time, so the 15 second series 23 can be located in the same layer. Double gate - ..." between the first common line 23 and the data line 21 The capacitance is smaller than the capacitance between the second common line and the data line of the conventional structure (ie, the non-double-pole line structure), and the second common line 23 and the Z line of the gate-lined halogen structure are replaced. The | coupling effect between 21 is smaller than the coupling effect between the common line and the data line of the conventional pixel structure. In the case of the conventional 昼 昼 即 即 即 即 即 即 区域 区域 区域 ap ap ap ap ap ap ap ap ap ap ap ap ap ap ap ap ap ap ap ap ap In the same way, when the second L-spring is added, 23%, the double-gate linear-type pixel structure of the alizarin region 15 20 201137478 sweat percentage (aperture rati〇) will also decrease. However, the ratio of the decrease in the aperture ratio of the pixel region 41 of the double-gate, 'spring-type halogen structure is smaller than the decrease ratio of the aperture ratio of the pixel region 41 of the conventional halogen structure, because the second common line 23 is located on the left Between the halogen region 41a and the right halogen region 41b, that is, the second common line 23 does not occupy the halogen region 41. Fig. 10 is a plan view showing a thin film transistor (TFT) array substrate 5 according to a first aspect of the second embodiment of the present invention. The thin film transistor array substrate 5 of the second embodiment is substantially similar to the thin film transistor array substrate 2 of the first embodiment, and elements similar to t are denoted by like reference numerals. The thin film transistor array substrate 5 comprises a transparent substrate 40, a plurality of gate lines 50', a plurality of data lines 5, a plurality of halogen electrodes 5, 15 a plurality of first common lines 52, and a plurality of second common lines. Magic and film transistor 54. The first common line 52 is parallel to the gate line 5〇. The second common line 53 is parallel to the data line 51 and is electrically connected to the first common line 52. None of the data lines are located between the left alum region 41a and the right alum region 41b, and each of the second hill lines 53 may be located between the left alum region 4ia and the right alum region. The halogen electrodes 55 are disposed in the halogen regions 41, respectively. Specifically, the second common line 53 is located between the pixel electrode 55 of the left pupil region 41a. and the 201137478 pixel electrode 55 of the right halogen region 41b. The coupling effect between the cylinders of the two adjacent pixel electrodes 55, which are right-handed through the L^8 and the 5th brother's common line 53, is smaller than that of the two adjacent elements without the second common line 53. Light human 5 effect between electrodes 55. Reduce the effect between two adjacent halogen electrodes 55; can solve the bright line (bright Hne) and dark line (_

question. J ... please refer to FIG. 10 again, in the first embodiment of the second embodiment, the difference between the thin film transistor array bases of the first and first embodiments is "the interpolar lines 50, the first The common line 52: 1〇*2 common line 53 is formed by exposing, developing, etching a first metal layer (M1), and the data lines 51 are exposed, shadowed, and etched by a second metal layer (M2). ) formed. An interpole insulating layer (not shown) is disposed between the first metal layer and the second gold layer. The gate line 50 includes - a portion 50a and a -15 a second portion 50b. A plurality of first via holes 581 are formed in the gate insulating layer and respectively correspond to the first portions 5 〇 a. The plural 侗, $2 are formed in the § Hai closed-pole insulation layer and are respectively inclined to the second part 50b of the ϋ海. Each of the conductive elements 57 is used to electrically connect the first portion 5〇3 of the 3H to the second portion 5〇b via the first through hole 581 and the second through hole 582. A conductive crucible 57 located between the first portion 5〇a and the second portion 50b of the gate f line 5〇 intersects the second common line 53. The electric conductor 57 and the halogen electrode 55 are made of a transparent conductive material. In other words, the conductive element 57 and the halogen electrode 55 can be formed by the same exposure, development, and engraving process, so that the process time and cost are not increased. 10, in the second aspect of the second embodiment, the gate lines 50, the first common line 52, and the second common line 53 are also exposed, developed, and etched. The metal layer (M1) is formed, and the data lines 5丨 are also formed by exposure, and the first metal layer (M2) is inscribed. A gate insulating layer (not shown) is also disposed between the first metal layer and the second metal layer. The difference between the second and first aspects of the film transistor array substrate of the second embodiment is that the second common line 53 includes a first portion 53a and a second portion 53b.

15 20 γ u" ϋ 1 is formed on the gate and the layer, and the sub-portions correspond to the first portion 53a. A plurality of two via holes 582' are formed in the gates corresponding to the second portions, respectively. Each of the conductive elements ^: the first portion 53a is electrically connected to the second portion via the first pass. Bit: ::, the first part of the line 53 and the second part of the guide: the electric...7, intersecting the idle line 5〇: 'and the pixel electrode 55 is made of transparent conductive and clothing m, the Conductive element 57, and halogen electrode

18 201137478 The same exposure, development, and etching processes can be used without increasing process time and cost. According to the third embodiment of the present invention, the thin film transistor array substrate 7 of the conventionally applied embodiment of the TFT array substrate 7 is substantially larger than the first Thin 9 ^ / pancreatic transistor array substrate of one embodiment

At the same time, similar elements such as t 10 are labeled with similar reference numerals. The thin film electric circuit board 7 includes a transparent substrate 4Q, a plurality of closed electrodes, a spring 70, a plurality of data lines 71, a plurality of halogen electrodes 75, a plurality of first common lines 72, and a plurality of second The common line is a thin film transistor 74. A first common line 72 is parallel to the gate line 70. The first line is parallel to the data line 71 and electrically connected to the line 73. Hai first common line 72. There is no data line between the left pixel 15 region 41a and the right pixel region 41b, so each second common line 73 can be located between the left halogen region 41a and the right halogen region 41b. The halogen electrodes 75 are disposed in the respective pixel regions 41. Specifically, the second common line 73 is located between the halogen electrode 75 of the left halogen region 41a and the halogen electrode 75 of the right halogen region 41b 20. The coupling effect between the two adjacent pixel electrodes 75 having the second common line 73 is smaller than the coupling effect between the two adjacent pixel electrodes 75 having the second common line 73. Reduce the effect between two adjacent halogen electrodes 7 5 201137478 should solve the problem of bright line and dark line. Referring to FIG. 12 again, in the first sadness of the third embodiment, the difference between the thin film transistor array substrate of the third embodiment and the first embodiment is "the gate lines 7 are exposed, developed, and cooked. The first metal layer (M1) is formed, and the data lines 71, the first common line 72, and the second common line 73 are formed by exposing, developing, and etching a second metal layer (M2). A passivation protective layer (not shown) is disposed between the first metal layer and the first metal layer. The data line 71 includes a first portion 71a and a second portion 71b. A plurality of first via holes 781 are formed in the passivation protective layer ' and correspond to the first portions 71a, respectively. A plurality of first vias 782 are formed in the passivation protective layer and are respectively applied to the second portions 71b. Each of the conductive elements 77 is electrically connected to the second portion 71b via the first through hole 718 and the second through hole 782. The conductive member 77 located between the first portion 71a and the second portion 71b of the line 71 intersects the first common line 72. The conductive element 77 and the halogen electrode 75 are made of a transparent conductive material, and the conductive element 77 and the halogen electrode 75 can be simultaneously formed by the same exposure, development, and etching processes, so that the process time and cost are not increased. . 20 201137478, please refer to FIG. 13 , in the second aspect of the third embodiment, the gate lines 70 are also formed by exposing, developing, etching a first metal layer (Μ 1), and the The data line 71, the first common line 72, and the second common line 73 are also formed by exposure, 5 development, and etching of a second metal layer (M2). A purification protective layer (not shown) is also disposed between the first metal layer and the second metal layer. The difference between the second and first aspects of the thin film transistor array substrate of the third embodiment is that the first common line 72 includes a first portion 72a and a second portion 72b. A plurality of first through holes 78 are formed in the passivation protective layer and respectively correspond to the first portions 72a. A plurality of second via holes 782' are formed in the passivation protective layer and respectively correspond to the second portions 72b. Each of the conductive elements 77' is used to electrically connect the first portion 72a to the second portion 72b via the first through hole 781' and the second through hole 782'. A conductive element 77' located between the first portion 72a and the second portion 72b of the first common line 72 intersects the data line 71. The conductive member 77' and the halogen electrode 75 are made of a transparent conductive material. In other words, the conductive element 77' and the halogen electrode 75 20 can be simultaneously formed by the same exposure, development, and etching processes, so that the process time and cost are not increased. Fig. 14 is a plan view showing a thin film transistor (TFT) array substrate 8 according to a fourth embodiment of the present invention. The thin film transistor array substrate 8 of the second embodiment of the 201137478 is substantially similar to the thin film transistor array substrate 2 of the first embodiment, wherein like elements are not labeled with similar reference numerals. The thin film transistor array substrate 8 includes a transparent substrate 40, a plurality of interrogation lines 8〇, ς5 number of data lines 81, a plurality of pixel electrodes 85, a plurality of first common lines 82, and a plurality of second common lines. 83 with a film Christine crystal 84. The first common line 82 is parallel to the gate line 8〇. The second common line 83 is parallel to the data line 81 and electrically connected to the first common line 82. No data line is located between the left-handed region 41a and the right-pixel region 4ib, so each second common line 83 can be located between the left-hand pixel region 41a and the right-pixel region = 41 b. The halogen electrodes 85 are disposed in the respective pixel regions 41. In particular, the second common line 83 is located between the pixel electrode 85 of the left-dwell region 41a and the halogen electrode 85 of the right-halogen region 41b. The coupling effect between two adjacent pixel electrodes 85 having the second common line 83 is smaller than the coupling effect between two adjacent pixel electrodes 85 having no second common line 83. Reducing the coupling effect between two adjacent pixel electrodes 85 should solve the problem of bright lines (briSht Hne) and dark lines. In the fourth embodiment, the difference between the thin film transistor array substrate of the fourth embodiment and the first embodiment is that the gate lines 8〇22 201137478 and the second common line 83 are exposed, developed, and etched. A metal layer (M1) is formed, and the data lines 81 and the first common lines 82 are formed by exposure, development, and a second metal layer (M2). A gate insulating layer (not shown) is disposed between the 5 first metal layer and the second metal layer. A purified protective layer (not shown) is disposed on the first common line 82. The first common line 82 includes a first portion 82a and a second portion 82b, and the second common line 83 includes a third portion 83a and a fourth portion 83b. 1〇 A plurality of first via holes 881 are formed in the passivation protective layer and respectively correspond to the first portions 82a. A plurality of second via holes 882 are formed in the passivation protective layer and respectively correspond to the second portions 82b. Each of the conductive elements 87a is electrically connected to the first portion 82a via the first through hole 881 and the second through hole 882 to the second portion 82b. A conductive element 87a located between the first portion 82a and the second portion 82b of the first common line 82 intersects the data line 81. A plurality of third via holes 883 are formed in the gate insulating layer and respectively correspond to the third portions 83a. A plurality of twenty-four through holes 884 are formed in the gate insulating layer and respectively correspond to the fourth portions 83b. Each of the conductive elements 87b is electrically connected to the third portion 83a via the third through hole 883 and the fourth through hole 884 to the fourth portion 83b. Located at this 201137478, the conductive element 87b between the third portion 83a and the fourth portion 83b of the common common line 83 intersects the gate line 8A. A plurality of fifth via holes 885 are formed in the passivation protective layer and respectively correspond to the first common lines 82. A plurality of sixth via holes 886 are formed in the gate insulating layer and correspond to the second common lines 83, respectively. Each of the conductive elements 8 is electrically connected to the second common line 83 via the fifth through hole 885 and the sixth through hole 886. The conductive members 87a, 87b, 87c and the halogen electrode 85 are made of a transparent material. In other words, the conductive members 87a, 87b, and the halogen electrode δ5 can be formed simultaneously by the same exposure, development, and etching, so that the process time and cost are not increased. Fig. 15 is a plan view showing a thin film transistor (TFT) array substrate 9 according to a fifth embodiment of the present invention. The thin film transistor array substrate 9 of the fifth embodiment is substantially similar to the thin film transistor array substrate 8 of the fourth embodiment, wherein like elements are designated by like reference numerals. The thin film transistor array substrate 9 includes a transparent substrate 40, a plurality of gate lines 9〇, a plurality of data lines 91, a plurality of halogen electrodes 95, a plurality of second common lines 92, and a plurality of second common lines. 93 and a thin germanium transistor 94. The first common line 92 is parallel to the gate line 9〇. The first common line 93 is parallel to the data line 91 and is electrically connected to 24 201137478 «ο • the first common line 92. There is no data line between the left sputum., the area 41a and the right sulphate area 41b, so each second . #通线93 can be located between the left 昼 区域 area and the right 昼 区域 area. The monocyte electrodes % are disposed in the respective germanium regions 41. Specifically, the second common line 93 is located between the pixel electrode % of the left-handed region 41a and the halogen electrode 95 of the right-handed region 4ib. The coupling effect between the two electrodes having the second common line 93 is smaller than the coupling effect between the two adjacent pixel electrodes 95 having no first common line 93. Reducing the coupling effect between two adjacent halogen electrodes 95 can solve the problems of bright lines and dark lines. - In the fifth embodiment, the difference between the thin film transistor array substrates of the fifth and fourth embodiments is "the first common line 15 92 is located in the two adjacent pixel regions 41 arranged in the upper and lower positions." Between the gate lines 90. The first common line 92 includes a first portion 92a and a second portion 92b, and the second common, 'spring%' includes a second portion 93a and a fourth portion 93b. A plurality of first through holes 981 are formed in the passivation protection layer 20 and correspond to the first portions 92a, respectively. A plurality of first via holes 982 are formed in the purification protective layer and respectively correspond to the second portions 92b. Each of the conductive elements 97a is electrically connected to the first portion 92a via the first through hole 981 and the second 25 201137478 and the through hole 982 to the second portion 92b. A conductive element 97a located between the first portion 92a and the second portion 92b of the first common line 92 intersects the data line 91. A plurality of third via holes 983 are formed in the gate insulating layer 5 and correspond to the third portions 93a, respectively. A plurality of fourth via holes 984 are formed in the gate insulating layer and respectively correspond to the fourth portions 93b. Each of the conductive elements 97b is electrically connected to the third portion 93a via the third through hole 983 and the fourth through hole 984 to the fourth portion 93b. The conductive member 97b located between the third portion 93a and the fourth portion 93b of the second common line 93 intersects the gate line 90. A plurality of fifth via holes 985 are formed in the passivation protective layer and respectively correspond to the first common lines 92. The conductive element 97b is also used to electrically connect the first common line 92 to the second common line 93 via the third through hole 15 983, the fourth through hole 984 and the fifth through hole 985. The conductive members 97a, 97b and the germanium electrode 95 are made of a transparent conductive material. In other words, the conductive elements 97a, 97b and the halogen electrode 95 can be formed simultaneously by the same exposure, development, and silver engraving process, so that the process time and cost are not increased. Referring to Fig. 16, there is shown a circuit diagram of a thin film transistor (TFT) array substrate 2 of the first embodiment. The thin film transistor array substrate 2 includes the gate lines 20, the data lines 201137478, the μ, the halogen electrodes 25, the first common lines 22, the second common lines - 23, and the thin film transistors 24. The second common lines 23 are electrically connected to the first common lines 22. Therefore, Fig. 17 shows that the first common line 22 and the second common line 23 constitute a mesh structure of the first embodiment of the present invention. Similarly, in the second to fifth embodiments, the first common lines of the thin film transistor (TFT) array substrate are electrically connected to the first common lines, whereby the first common lines are Forming a mesh structure with the second common line, thereby reducing the resistance-capacitance signal delay effect of the common line. 10 Referring to Fig. 18', a liquid crystal panel 200 is shown. The thin film transistor array substrate 2 of the first embodiment can be applied to the liquid crystal panel 200. The liquid crystal panel 2 includes the thin film transistor array substrate 2', a color filter substrate 2, and a liquid crystal layer 2', the liquid crystal layer 21, which is located on the color filter substrate 2, 15 and the thin film. Between the crystal array substrates 2. The color filter substrate 2 includes a black matrix layer 28, a color filter, a light layer 22', and a transparent electrode 24, which are sequentially formed on the other transparent substrate 26. The black matrics 28' must correspond to the gate lines 20, the data lines 21, 20, and the second common line 23 to avoid light leakage. I. Figure 19 shows a liquid crystal display. The liquid crystal panel 2 of the first embodiment can be applied to the liquid crystal display 2000. The liquid crystal display 2 includes a front frame 27 201137478 202, a far liquid crystal panel 200 and a backlight module 2〇4. The backlight module 204 is configured to provide a light source into the liquid crystal panel 200, and the front panel 202 is coupled to the front panel 202 to combine the liquid crystal panel 200 and the moonlight module 204 into the liquid crystal display panel. Although the present invention has been disclosed in the above preferred embodiments, the present invention is not intended to limit the invention, and it is possible to make a few changes without departing from the spirit and scope of the invention. With retouching, therefore the invention 10 15

The scope of protection is subject to the definition of the scope of the patent application. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic plan view of a conventional halogen structure; Fig. 2 is a schematic plan view of a conventional halogen structure matrix; Fig. 3 is an embodiment of the present invention, and a plan view of a halogen structure schematic diagram;

Figure 4 is a cross-sectional view taken along line 1-1 of Fig. 3; Fig. 5 is a schematic plan view of the matrix of Fig. 3; ^6 is another embodiment of the present invention, and a schematic view of the structure of the element; . ^Dj is a schematic plan view of the matrix; Figure 2 is a schematic plan view of the matrix of Fig. 6; 2^^-implementation - 28 20 201137478 The first view is a plan view of the thin film transistor array substrate according to the first aspect of the second embodiment of the present invention. FIG. 11 is a top plan view of a thin film transistor array substrate according to a second aspect of the second embodiment of the present invention; FIG. 12 is a first embodiment of a thin film power according to a third embodiment of the present invention. FIG. 13 is a top plan view of a thin film transistor array substrate according to a second aspect of the third embodiment of the present invention; and FIG. 14 is a thin film power according to a fourth embodiment of the present invention. FIG. 15 is a top plan view of a thin film transistor array substrate according to a fifth embodiment of the present invention; FIG. 16 is a circuit diagram of a thin film transistor array substrate according to a first embodiment of the present invention; 15 shows that the first common line and the second common line constitute a mesh structure of the first embodiment of the present invention; FIG. 18 is a liquid of the first embodiment of the present invention. Panel in a schematic exploded perspective; 20 an exploded perspective schematic view of a first embodiment of the liquid crystal 19 of the graph display of the present embodiment of the invention. [Explanation of main component symbols] 10, 20, 30, 50, 60, 70, 80, 90 Gate lines 11, 21, 31, 51, 61, 71, 81, 91 Information line 29 201137478 12, 24, 34, 54 , 64, 74, 84, 94 Thin Film Transistor 120, 340, 640 Gate 5 121, 341, 641 Channel Layer 122, 342, 642 Source 123, 343, 643 Bungee 13, 25, 35, 55, 65, 75, 85, 95 Alizarin Electrode 14, 18, 26, 36, 66 Contact window 15 Lower electrode 10 16 Storage capacitor 17 Upper electrode 200 Liquid crystal panel 2000 Liquid crystal display 202 Front frame 204 Backlight module 15 2, 5, 7, 8, 9 Thin film transistor array substrate 2 'Color filter substrate 21' liquid crystal layer 22' color filter layer 22, 32, 52, 62, 72, 82, 92 first common line 23, 33, 53, 63, 73, 83, 93 second common line 24' transparent electrode 26' transparent substrate 27, 37, 57, 57, 67, 77, 77, 87a, 87b, 87c, 97a, 97b conductive element 201137478 28' black matrix layer 281, 381, 581, 681, 781, 781, 881, 981 first through hole 282, 382, 582, 682, 782, 782, 882, 982 second through hole 40, 70 substrate 5 41, 41a, 41b halogen region 42, 72 gate Pole insulating layers 44, 74 passivation protective layers 50a, 53a, 601, 71a 72a, 82a, 92a first part 50b, 53b, 602, 71b, 72b, 82b, 92b second part ίο 83a, 93a third part 83b, 93b fourth part 883, 983 third through hole 884, 984 fourth through hole 885, 985 Five-way hole 15 886 sixth through hole

Claims (1)

201137478 VII, the scope of the patent: _ l - a thin film transistor array substrate, comprising: a transparent substrate; _ a plurality of gate lines 'on the transparent substrate; 5 a plurality of data lines, and the gates The line intersects, wherein two adjacent gate lines and two adjacent data lines define two halogen regions, which are a left halogen region and a right halogen region; _ a plurality of first common lines, parallel to the a plurality of idle lines; and a plurality of second common lines parallel to the data lines and connected to the first common lines, wherein each of the second common L, springs is located in the area Between the halogen element and the halogen electrode of the right pixel region. 2. According to the patent scope of the application, the thin film transistor array base 15 board, wherein: the number of the gate lines is N+1, the i-th to the N+1th gate lines are in order Arranged on the transparent substrate, and n is a positive number; when N is an even number, the Nth to N+1 inter-pole line 2〇 and the two adjacent data lines are not defined with any element 32 32 201137478 When N is an odd number, two pixel regions are defined between the 帛N to the inter-deviating strip and the two adjacent data lines, which are the left-salvin region and the right-halogen region. 3. According to the patented film range i, the thin film transistor array base plate, wherein no data line is located between the left albino region and the right halogen region. 4. The thin film transistor array substrate according to claim 1, wherein the gate lines and the first common lines are formed by exposing, developing, etching-first metal layer, and the data is 10 lines and The second common line is formed by exposing, developing, and etching a second metal layer. 5. The thin film transistor array substrate according to claim 4, further comprising: a plurality of first through holes respectively corresponding to the first common 15 lines; and a plurality of second through holes corresponding to the plurality of a second common line; and a plurality of conductive elements, each of the conductive elements for electrically connecting the first common line to the second common line via the first through hole and the second through hole. 6' Thin film transistor array base according to patent application scope 33 201137478 The polar line is exposed to 1 second line, the first common line and the second common line, and the minute, '4 shirts, etching a first metal layer and forming a shape line into the lean line are exposed, developed, etched- The first to the genus is formed. 7. According to the patent application board, wherein: the film transistor array base of the sixth item and The thin film transistor array substrate further includes: 10 a flute, a through hole corresponding to the first portion; a second through hole corresponding to the second portion; and::: to: pass the first portion through The sub-via and the second via are electrically connected to the second 15 8. According to the 7th 申请 patent application scope, JL consists of 7 members of the monumental transistor array. Among them, the conductive element between the idle line, the fisherman's first-hill, the s knife and the 罘一口Μ 9 hai The brothers crossed the line together. • Apply for the sixth paragraph of the patent scope &gt; board, t: negative entertainment crystal array J 2〇 The second common line includes a first part and i points, · and 1 knife and one brother 34 201137478 The thin film transistor array substrate includes: a first through hole corresponding to the first portion of the second through hole corresponding to the portion; and a segment 1 〇· according to the patent application scope 9th, 哒p + plate, basin The first part of the fUtZ common line in the portion 10 of the binding plate of the ^ item and the first: the conductive element between the files intersects the gate line. The thin film transistor array-3 according to the first aspect of the patent range; the interpolar lines are exposed, developed, etched - and *1: formed ' and the data lines, the first common metal; :: The exposure, development, engraving - second base m (four) (four) 11 transistor array and ° Hai data line include a first part and a second part; 5 溥 溥 film transistor array substrate further comprises: - first through hole Corresponding to the first portion; the second pass, corresponding to the second portion; and a conductive member of 35 20 for passing the first pass through the first hole and the through hole Electrically connected to the second part of the application, the 12th work of the patent range is less than 5 substrates, which are located between the data edge and the conductivity of the array of electrodes... ίτ points and the second part 14 匕, &quot; Brother-common line intersects. According to the scope of the patent application, the + substrate, wherein: 、, the transistor array 10, the first common line includes a first minute; and the first knife and the second two of the film The transistor array substrate further includes: a first through hole corresponding to the first a portion; a second through hole corresponding to the second portion; and 15 for electrically connecting the first portion to the second portion via the first portion to the second portion The thin film transistor array of the second part: f/bit: the first part of the first common line and the power-receiving element of the first knives J intersect with the data line. 16· 依申眼 patent 筋 ιψι @, 扎围The base line of the die-connecting transistor array of the "1" is formed by exposure, 36 20 201137478 development, and a first metal layer is formed, and the data lines and the first common line are formed. Then, it is formed by exposing, developing, and etching a second metal layer. 17. The thin film transistor array 5 substrate of claim 16, wherein: the first common line includes a first portion and a second portion; the second common line includes a third portion and a fourth portion; And the thin film transistor array substrate further includes: a first through hole corresponding to the first portion; a second through hole corresponding to the second portion; a first conductive element for passing the first portion The first through hole and the second through hole are electrically connected to the second 15th portion and a third through hole corresponding to the third portion; a fourth through hole corresponding to the fourth portion; a second conductive member The third portion is electrically connected to the fourth portion through the third through hole and the fourth through hole; [SI a fifth through hole corresponding to the first common line; 37 201137478 - a six-via hole corresponding to the second common line; and three conductive elements for electrically connecting the first common line to the second common line via the second through hole and the fourth through hole. According to the application (4), the thin film transistor core substrate of the seventh item, wherein the first conductive element between the first portion and the second portion of the first common line crosses the data (4) and is located at the second common line Part III and Section 10 The second conductive element between the turns intersects the gate line and turns. J. The second embodiment of the thin film transistor array according to claim 16, wherein the first common line is located between two gate lines in two adjacent pixel regions arranged in the upper and lower positions. 15 2〇.· According to the scope of application for patents, item 19, of which is a thin film transistor array The first common line includes a first portion and a portion; the second common line includes a third portion of the knife-fourth portion and the thin film transistor array substrate further includes: a first through hole corresponding to the first portion 38 201137478, a second through hole corresponding to the second portion; a first conductive element for electrically connecting the first portion to the second portion via the first through hole and the second through hole a third through hole corresponding to the third portion; a fourth through hole corresponding to the fourth portion; a fifth through hole corresponding to the first common line; and a second conductive element for The third portion is electrically connected to the fourth portion via the third through hole, the fourth through hole and the fifth through hole, and the first common line is passed through the third through hole and the fourth through hole And a fifth via hole electrically connected to the second common line. The thin film transistor array substrate of claim 20, wherein the first conductive element between the first portion and the 15th portion of the first common line intersects the data line and is located at the second The second conductive element between the third portion and the fourth portion of the common line intersects the gate line. 22. A liquid crystal panel comprising: a second color filter substrate; a thin film transistor array substrate comprising: 201137478 a transparent substrate; and: a plurality of gate lines disposed on the transparent substrate; The data line 'crosses the gate lines, and the two-north region between the eight-two gate line and the two adjacent data lines defines a left-dimensional region and a right-sentence region; - a plurality of a common line parallel to the gate lines; and 10 a plurality of second common lines parallel to the data lines and electrically connected to the first common lines, wherein each second common line is located at the left a liquid crystal layer disposed between the color filter substrate and the thin film transistor array substrate; wherein the color filter substrate includes a The black matrix layer 'which corresponds to the second common lines. 15