CN102237355A - TFT array substrate and LCD panel - Google Patents
TFT array substrate and LCD panel Download PDFInfo
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- CN102237355A CN102237355A CN 201010243210 CN201010243210A CN102237355A CN 102237355 A CN102237355 A CN 102237355A CN 201010243210 CN201010243210 CN 201010243210 CN 201010243210 A CN201010243210 A CN 201010243210A CN 102237355 A CN102237355 A CN 102237355A
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Abstract
A TFT (thin film transistor) array substrate includes a transparent substrate, gate lines, data lines, and first and second common lines. The gate lines are disposed on the transparent substrate. The data lines cross the gate lines. There are two pixel regions defined between the two adjacent gate lines and the two adjacent data lines, and the two pixel regions are a left pixel region and a right pixel region. The first common lines are parallel to the gate lines. The second common lines are parallel to the data lines and electrically connected to the first common lines, wherein each second common line is disposed between the pixel electrode of the left pixel region and the pixel electrode of the right pixel region.
Description
Technical field
The invention provides the thin-film transistor array base-plate of the liquid crystal panel of a kind of LCD, particularly a kind of LCD, it has cancellated common wire (common line), to reduce the signal delay effect that resistance, electric capacity were caused.
Background technology
Generally speaking, LCD (Liquid Crystal Display, LCD) can by provide respectively corresponding to the data-signal of picture data to liquid crystal cell (Liquid Crystal Cell), adjust the light transmittance of liquid crystal cell with display picture data.LCD then comprises: have the liquid crystal panel of arranged liquid crystal cell, and the integrated circuit that is used to drive (Integrated Circuit, IC).
Liquid crystal panel also comprises: colored filter substrate; Thin-film transistor array base-plate corresponding to this colored filter substrate; And be sandwiched in liquid crystal layer between this colored filter substrate and this thin-film transistor array base-plate.Thin-film transistor array base-plate comprises: be used to transmit the data-signal that provided by the data-driven integrated circuit data wire to liquid crystal cell, and be used to transmit the gate line that scans signal that provides by grid-driving integrated circuit, wherein liquid crystal cell is defined by data wire interlaced with each other and gate line.Grid-driving integrated circuit provides in order and scans signal to gate line, follows a ground with one and selects liquid crystal cell in regular turn.In addition, data-driven integrated circuit then provides data-signal the liquid crystal cell to selected gate line.
See also Fig. 1, Fig. 1 is the schematic layout pattern of existing dot structure, this kind dot structure structure of storage capacitors on common wire or public electrode that be otherwise known as, it is disposed on the substrate, and comprises at least: gate line 10, data wire 11 and thin-film transistor 12.Pixel region is defined by gate line and data wire, and gate line 10 extends along first direction, and 11 of data wires extend along second direction, and this second direction is perpendicular to this first direction.Thin-film transistor 12 comprises: grid 120, channel layer 121, source electrode 122 and drain electrode 123, and grid 120 is electrically connected to gate line 10, and source electrode 122 is electrically connected to data wire 11, drains 123 by contact window 14 electric connection pixel electrodes 13.
The storage capacitors 16 of pixel comprises: bottom electrode 15, top electrode 17 and be sandwiched in dielectric layer between this bottom electrode 15 and this top electrode 17.Bottom electrode 15 is the parts that are configured in the common wire in the pixel region, and it is basically parallel to gate line 10, and identical with gate line 10, grid 120, is formed by steps such as exposure, development, etchings by the first metal layer.Top electrode 17 electrically connects by contact window 18 and pixel electrode 13, and is identical with data wire 11, source electrode 122, drain electrode 123, formed by steps such as exposure, development, etchings by second metal level.In addition, dispose gate insulator between the first metal layer and second metal level, then dispose the passivation protection layer between second metal level and the pixel electrode 13.
See also Fig. 2, Fig. 2 is the matrix layout schematic diagram of existing dot structure, and in existing picture element matrix, common wire disposes along first direction, and electrically connects each other.Therefore, the common wire in existing picture element matrix, the signal delay effect that its resistance, electric capacity caused is quite obvious, makes image quality reduce.
In sum, be necessary to propose a kind of thin-film transistor array base-plate of liquid crystal panel of LCD, it reduces the problem of resistance-capacitance signal delay effect in the prior art by special common wire design, so that the LCD with good image quality to be provided.
Summary of the invention
In first to the 5th embodiment of the present invention, a kind of thin-film transistor array base-plate comprises transparency carrier, a plurality of gate line, data wire, first common wire and second common wire.Gate line is disposed on the transparency carrier, and the quantity of wherein said gate line is the N+1 bar, and the 1st is arranged on this transparency carrier in regular turn to N+1 bar gate line, and N is a positive number.Data wire and gate line intersect to be crossed over.When N is even number, between N bar to the N+1 bar gate line and two adjacent data lines and undefined any pixel region arranged.When N was odd number, definition had two pixel regions between N bar to the N+1 bar gate line and two adjacent data lines, and it is left pixel region and right pixel region.First common wire is parallel to gate line.Second common wire is parallel to data wire, and is electrically connected to first common wire, and wherein each second common wire is between the pixel electrode of the pixel electrode of left pixel region and right pixel region.
In first to the 5th embodiment, second common wire of this thin-film transistor array base-plate is electrically connected at first common wire, constitutes network structure by first common wire and second common wire, to reduce the resistance-capacitance signal delay effect of common wire.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, preferred embodiment cited below particularly, and conjunction with figs., be described in detail below, so that the those of ordinary skill in the display technology field can be understood and cognitive technology contents of the present invention and feature.
Description of drawings
Fig. 1 is the schematic top plan view of existing dot structure;
Fig. 2 is the schematic top plan view of existing dot structure matrix;
Fig. 3 is the schematic top plan view of the dot structure of one embodiment of the present of invention;
Fig. 4 is the generalized section of Fig. 3 along hatching line I-I ';
Fig. 5 is the matrix schematic top plan view of Fig. 3;
Fig. 6 is the schematic top plan view of the dot structure of an alternative embodiment of the invention;
Fig. 7 is the generalized section of Fig. 6 along hatching line K-K ';
Fig. 8 is the matrix schematic top plan view of Fig. 6;
Fig. 9 is the schematic top plan view according to the thin-film transistor array base-plate of the first embodiment of the present invention;
Figure 10 is the schematic top plan view of the thin-film transistor array base-plate of first form according to a second embodiment of the present invention;
Figure 11 is the schematic top plan view of the thin-film transistor array base-plate of second form according to a second embodiment of the present invention;
Figure 12 is the schematic top plan view of thin-film transistor array base-plate of first form of a third embodiment in accordance with the invention;
Figure 13 is the schematic top plan view of thin-film transistor array base-plate of second form of a third embodiment in accordance with the invention;
Figure 14 is the schematic top plan view of the thin-film transistor array base-plate of a fourth embodiment in accordance with the invention;
Figure 15 is the schematic top plan view of thin-film transistor array base-plate according to a fifth embodiment of the invention;
Figure 16 is the circuit diagram of the thin-film transistor array base-plate of the first embodiment of the present invention;
Figure 17 shows that first common wire and second common wire constitute the network structure of the first embodiment of the present invention;
Figure 18 is the exploded perspective schematic diagram of the liquid crystal panel of the first embodiment of the present invention; And
Figure 19 is the exploded perspective schematic diagram of the LCD of the first embodiment of the present invention.
The main element symbol description
10,20,30,50,60,70,80,90 gate lines
11,21,31,51,61,71,81,91 data wires
12,24,34,54,64,74,84,94 thin-film transistors
120,340,640 grids
121,341,641 channel layers
122,342,642 source electrodes
123,343,643 drain electrodes
13,25,35,55,65,75,85,95 pixel electrodes
14,18,26,36,66 contact windows
15 bottom electrodes
16 storage capacitors
17 top electrodes
200 liquid crystal panels
2000 LCD
Frame before 202
204 modules backlight
2,5,7,8,9 thin-film transistor array base-plates
2 ' colored filter substrate
21 ' liquid crystal layer
22 ' chromatic filter layer
22,32,52,62,72,82,92 first common wires
23,33,53,63,73,83,93 second common wires
24 ' transparency electrode
26 ' transparency carrier
27,37,57,57 ', 67,77,77 ', 87a, 87b, 87c, 97a, 97b conducting element
28 ' black-matrix layer
281,381,581 ', 681,781,781 ', 881,981 first through holes
282,382,582 ', 682,782,782 ', 882,982 second through holes
40,70 substrates
41,41a, 41b pixel region
42,72 gate insulators
44,74 passivation protection layers
50a, 53a, 601,71a, 72a, 82a, 92a first
50b, 53b, 602,71b, 72b, 82b, 92b second portion
83a, the 93a third part
83b, 93b the 4th part
883,983 third through-holes
884,984 fourth holes
885,985 fifth holes
886 the 6th through holes
Embodiment
Fig. 3 is the schematic layout pattern of the dot structure of one embodiment of the present of invention, and Fig. 4 then is the section schematic diagram along hatching line I-I '.
See also Fig. 3, pixel electrode structure comprises: gate line 30, data wire 31, first common wire 32, second common wire 33 and thin-film transistor 34.Gate line 30 is along the first direction configuration, and data wire 31 is then along the second direction configuration, and this second direction is vertical with this first direction basically.It is crossing with this gate line 30 that first common wire 32 is parallel to 33 of gate line 30, the second common wires.Thin-film transistor 34 comprises: grid 340, channel layer 341, source electrode 342 and drain 343.Grid 340 electrically connects with data wire 31 with gate line 30 electric connections, source electrode 342, drains 343 by contact hole 36 and pixel electrode 35 electric connections.
Fig. 4 is the generalized section of Fig. 3 along hatching line I-I '.Hence one can see that, the manufacture method of LCD provided by the present invention comprises: substrate 40 at first is provided, it can be glass substrate or plastic substrate, next forms grid 340, gate line 30 and first common wire 32 on this substrate 340, grid 340 electrically connects with gate line 30, and first common wire 32 is then parallel with gate line 30 basically.Grid 340, gate line 30 and first common wire 32 all belong to identical the first metal layer, are promptly all formed by exposure, development, this first metal layer of etching.
Then on substrate 40, form gate insulator 42 again, with the structure of first metal levels such as cover gate 340, gate line 30 and first common wire 32.Secondly, on gate insulator 42, form channel layer 341, and on the surface of channel layer 341, form the ohmic contact layer (not shown) again, to promote channel layer 341 and electrical contact of the source electrode 342 that next forms with 343 of drain electrodes.
And then the data wire 31 and second common wire 33 are formed on the gate insulator 42, and source electrode 342 and drain electrode 343 are positioned at the top of channel layer 341 just.Data wire 31, second common wire 33, source electrode 342 belong to the second identical metal level with 343 of drain electrodes, are promptly all formed by exposure, development, this second metal level of etching, and source electrode 342 is electrically connected at data wire 31.Grid 340, channel layer 341, source electrode 342 constitute thin-film transistor 34 with drain electrode 343.
Forming data wire 31, second common wire 33, source electrode 342 and draining after 343, on substrate 40, form passivation protection layer 44 again, above-mentioned to cover by the etched structure of second metal level.Then, this passivation protection layer of etching 44 and this gate insulator 42 again, forming first through hole 381 corresponding to this first common wire 32, and this passivation protection layer 44 of etching, to form second through hole 382 corresponding to this second common wire 33.Secondly, on this passivation protection layer 44, form by the made conducting element 37 of transparent conductive material, it can pass through first through hole 381 and second through hole 382, electrically connects first common wire 32 and second common wire 33.Wherein, conducting element 37 is made by transparent conductive materials such as tin indium oxide, indium zinc oxide, Zinc oxide doped aluminium and Zinc oxide doped galliums.
See also Fig. 5, Fig. 5 is the schematic diagram of the matrix layout of dot structure of the present invention.First common wire 32 and second common wire 33 electrically connect by conducting element 37 each other, and constitute network structure jointly, to reduce the resistance-capacitance signal delay effect of common wire.
Fig. 6 is the schematic layout pattern of the dot structure of another embodiment of the present invention, and Fig. 7 then is the section schematic diagram along its hatching line K-K '.
See also Fig. 6, dot structure comprises: gate line 60, data wire 61, first common wire 62, second common wire 63 and thin-film transistor 64.Gate line 60 is along the first direction configuration, and data wire 61 is then along the second direction configuration, and this second direction is vertical with this first direction basically.It is crossing with this gate line 60 that first common wire 62 is parallel to 63 of gate line 60, the second common wires.Thin-film transistor 64 comprises: grid 640, channel layer 641, source electrode 642 and drain 643.Grid 640 electrically connects with data wire 61 with gate line 60 electric connections, source electrode 642, drains 643 by contact hole 66 and pixel electrode 65 electric connections.
In the present embodiment, gate line 60 is made of with second portion 602 first 601.Second common wire 63 is crossed over this gate line 60, promptly crosses between first 601 and the second portion 602, or crosses between first 601 and the second portion 602.First 601 and second portion 602 electrically connect by conducting element 67, and it is made by transparent conductive materials such as tin indium oxide, indium zinc oxide, Zinc oxide doped aluminium and Zinc oxide doped galliums.Gate line 60, first common wire 62, second common wire 63 form by exposure, development, etching the first metal layer with grid 640, and data wire 61, source electrode 642 and drain electrode 643 are then formed by exposure, development, etching second metal level.Passivation protection layer 74 is configured on second common wire, as shown in Figure 7, and has first through hole 681 and second through hole 682, corresponds respectively to the first 601 and second portion 602 of gate line 60.Therefore, conducting element 67 electrically connects first 601 and second portion 602 by first through hole 681 and second through hole 682.
Then on substrate 70, form gate insulator 72, with the structure of first metal levels such as cover gate 640, first 601, second portion 602, first common wire 62 and second common wire 63.Secondly, on gate insulator 72, form channel layer 641, and on the surface of channel layer 641, form the ohmic contact layer (not shown) again, to promote channel layer 641 and electrical contact of the source electrode 642 that next forms with 643 of drain electrodes.
And then data wire 61 is formed on the gate insulator 72, and source electrode 642 and drain electrode 643 are positioned at the top of channel layer 641 just.Data wire 61, source electrode 642 belong to the second identical metal level with 643 of drain electrodes, are promptly all formed by exposure, development, this second metal level of etching, and source electrode 642 is electrically connected to data wire 61.Grid 640, channel layer 641, source electrode 642 constitute thin-film transistor 64 with drain electrode 643.
Forming data wire 61, source electrode 642 and draining after 643, on substrate 70, form passivation protection layer 74 again, above-mentioned to cover by the etched structure of second metal level.Then, this passivation protection layer of etching 74 and this gate insulator 72 again are to form first through hole 681 corresponding to this first 601, with second through hole 682 corresponding to this second portion 602.Secondly, on this passivation protection layer 74, form by the made conducting element 67 of transparent conductive material, it can electrically connect first 601 and second portion 602 by first through hole 681 and second through hole 682.Wherein, conducting element 67 is made by transparent conductive materials such as tin indium oxide, indium zinc oxide, Zinc oxide doped aluminium and Zinc oxide doped galliums.
See also Fig. 8, it is the schematic diagram of the matrix layout of another dot structure of the present invention.First common wire 62 and second common wire 63 are electrically connected to each other and constitute network structure jointly, to reduce the resistance-capacitance signal delay effect of common wire.
Fig. 9 is thin-film transistor (thin film transistor, TFT) schematic top plan view of array base palte 2 according to the first embodiment of the present invention.This thin-film transistor array base-plate 2 comprises transparency carrier 40, a plurality of gate line 20, a plurality of data wire 21, a plurality of pixel electrode 25, a plurality of first common wire 22, a plurality of second common wire 23 and thin-film transistor 24.This transparency carrier 40 can be glass substrate or plastic substrate.Described gate line 30 is disposed on this transparency carrier 40.The quantity of described gate line 20 is the N+1 bar, and the 1st is arranged on this transparency carrier 40 in regular turn to N+1 bar gate line 20, and N is a positive number.Described data wire 21 intersects with described gate line 20 to be crossed over, and vertical with described gate line 20.When N is even number, between N bar to the N+1 bar gate line 30 and two adjacent data lines 21 and undefined any pixel region arranged.When N was odd number, definition had two pixel regions 41 between N bar to the N+1 bar gate line 20 and two adjacent data lines 21, and it is left pixel region 41a and right pixel region 41b.For example, when N is 2, between the 2nd to the 3rd gate line 20 and two adjacent data lines 21 and undefined any pixel region arranged.When N was 1, definition had two pixel regions 41 between the 1st to the 2nd gate line 20 and two adjacent data lines 21, and it is left pixel region 41a and right pixel region 41b.Remainder can the rest may be inferred.Therefore two gate lines 20 are called as double grid polar curve (dual gate line) type dot structure between two adjacent pixel regions 41 of arranging with upper-lower position.
This first common wire 22 is parallel to this gate line 20.This second common wire 23 is parallel to this data wire 21, and is electrically connected at this first common wire 22.Between left pixel region 41a and right pixel region 41b, so each second common wire 23 can be between left pixel region 41a and right pixel region 41b without any data line bit.Described pixel electrode 25 is disposed at respectively in the described pixel region 41.Each thin-film transistor 24 has drain electrode, and this drain electrode electrically connects with this pixel electrode 25 by contact window 26.
Especially, this second common wire 23 is between the pixel electrode 25 of the pixel electrode 25 of left pixel region 41a and right pixel region 41b.Have this second common wire 23 between two adjacent pixel electrodes 25, and have electric capacity (capacitance) between two adjacent pixel electrodes 25 of this second common wire 23 less than the electric capacity between two adjacent pixel electrodes 25 that do not have this second common wire 23.In other words, has coupling (coupling) effect between two adjacent pixel electrodes 25 of this second common wire 23 less than the coupling effect between two adjacent pixel electrodes 25 that do not have this second common wire 23.Reduce the problem that coupling effect between two adjacent pixel electrodes 25 can solve bright line (bright line) and concealed wire (dark line).
In first embodiment, the described gate line 20 and first common wire 22 all form by exposure, development, etching the first metal layer (M1), and the described data wire 21 and second common wire 23 then form by exposure, development, etching second metal level (M2).The gate insulator (not shown) is configured between this first metal layer and second metal level.Passivation protection layer (not shown) is configured on this second common wire 23.A plurality of first through holes 281 are formed in this gate insulator and the passivation protection layer, and correspond respectively to described first common wire 22.A plurality of second through holes 282 are formed in this passivation protection layer, and correspond respectively to described second common wire 23.Each conducting element 27 is used for this first common wire 22 via this first through hole 281 and second through hole 282 and be electrically connected to this second common wire 23.This conducting element 27 and pixel electrode 25 are made by transparent conductive material.In other words, this conducting element 27 can be formed by identical exposure, development, etching step simultaneously with pixel electrode 25, so can not increase the time and the cost of step.
Moreover described data wire 21 forms by identical second metal level (M2) simultaneously with second common wire 23, and therefore the described data wire 21 and second common wire 23 can be positioned at same one deck.Second common wire 23 of bigrid line style dot structure and the electric capacity between the data wire 21 are less than second common wire of existing dot structure (being non-bigrid line style dot structure) and the electric capacity between the data wire.In other words, second common wire 23 of bigrid line style dot structure and the coupling effect between the data wire 21 are less than second common wire of existing dot structure and the coupling effect between the data wire.
In addition, when increasing second common wire newly, the pixel region aperture opening ratio (aperture ratio) of existing dot structure (being non-bigrid line style dot structure) can reduce.In like manner, when increasing second common wire 23 newly, pixel region 41 aperture opening ratios of bigrid line style dot structure also can reduce.But, the minimizing ratio of pixel region 41 aperture opening ratios of bigrid line style dot structure is less than the minimizing ratio of pixel region 41 aperture opening ratios of existing dot structure, itself because be second common wire 23 between left pixel region 41a and right pixel region 41b, promptly second common wire 23 can not occupy pixel region 41.
Figure 10 is the schematic top plan view of thin-film transistor (TFT) array base palte 5 of first form according to a second embodiment of the present invention.The thin-film transistor array base-plate 5 of this second embodiment is similar to the thin-film transistor array base-plate 2 of this first embodiment substantially, and wherein similar elements indicates similar label.This thin-film transistor array base-plate 5 comprises transparency carrier 40, a plurality of gate line 50, a plurality of data wire 51, a plurality of pixel electrode 55, a plurality of first common wire 52, a plurality of second common wire 53 and thin-film transistor 54.
This first common wire 52 is parallel to this gate line 50.This second common wire 53 is parallel to this data wire 51 and is electrically connected at this first common wire 52.Between left pixel region 41a and right pixel region 41b, and each second common wire 53 can be between left pixel region 41a and right pixel region 41b without any data line bit.Described pixel electrode 55 is disposed at respectively in the described pixel region 41.Especially, this second common wire 53 is between the pixel electrode 55 of the pixel electrode 55 of left pixel region 41a and right pixel region 41b.Has coupling effect between two adjacent pixel electrodes 55 of this second common wire 53 less than the coupling effect between two adjacent pixel electrodes 55 that do not have this second common wire 53.Reduce the problem that coupling effect between two adjacent pixel electrodes 55 can solve bright line (bright line) and concealed wire (dark line).
Refer again to Figure 10, in first form of this second embodiment, the difference of the thin-film transistor array base-plate of second and first embodiment is: described gate line 50, first common wire 52 and second common wire 53 all form by exposure, development, etching the first metal layer (M1), and described data wire 51 then forms by exposure, development, etching second metal level (M2).The gate insulator (not shown) is configured between this first metal layer and second metal level.This gate line 50 comprises 50a of first and second portion 50b.
A plurality of first through holes 581 are formed on this gate insulator, and correspond respectively to the described 50a of first.A plurality of second through holes 582 are formed in this gate insulator, and correspond respectively to described second portion 50b.Each conducting element 57 is used for the 50a of this first via this first through hole 581 and second through hole 582 and be electrically connected to this second portion 50b.50a of first and the conducting element between the second portion 50b 57 at this gate line 50 intersect leap with this second common wire 53.This conducting element 57 and pixel electrode 55 are made by transparent conductive material.In other words, this conducting element 57 can be formed by identical exposure, development, etching step simultaneously with pixel electrode 55, so can not increase the time and the cost of step.
Please refer to Figure 11, in second form of this second embodiment, described gate line 50, first common wire 52 and second common wire 53 all form by exposure, development, etching the first metal layer (M1), and described data wire 51 then forms by exposure, development, etching second metal level (M2).The gate insulator (not shown) is configured between this first metal layer and second metal level.The difference of the thin-film transistor array base-plate of second and first form of this second embodiment is: this second common wire 53 comprises 53a of first and second portion 53b.
A plurality of first through holes 581 ' are formed on this gate insulator, and correspond respectively to the described 53a of first.A plurality of second through holes 582 ' are formed in this gate insulator, and correspond respectively to described second portion 53b.Each conducting element 57 ' is used for the 53a of this first via this first through hole 581 ' and second through hole 582 ' and be electrically connected to this second portion 53b.53a of first and the conducting element between the second portion 53b 57 ' at this second common wire 53 intersect leap with this gate line 50.This conducting element 57 ' and pixel electrode 55 are made by transparent conductive material.In other words, this conducting element 57 ' can be formed by identical exposure, development, etching step simultaneously with pixel electrode 55, so can not increase the time and the cost of step.
Figure 12 is the schematic top plan view of thin-film transistor array base-plate 7 of first form of a third embodiment in accordance with the invention.The thin-film transistor array base-plate 7 of this second embodiment is similar to the thin-film transistor array base-plate 2 of this first embodiment substantially, and wherein similar elements indicates similar label.This thin-film transistor array base-plate 7 comprises transparency carrier 40, a plurality of gate line 70, a plurality of data wire 71, a plurality of pixel electrode 75, a plurality of first common wire 72, a plurality of second common wire 73 and thin-film transistor 74.
This first common wire 72 is parallel to this gate line 70.This second common wire 73 is parallel to this data wire 71, and is electrically connected at this first common wire 72.Between left pixel region 41a and right pixel region 41b, so each second common wire 73 can be between left pixel region 41a and right pixel region 41b without any data line bit.Described pixel electrode 75 is disposed at respectively in the described pixel region 41.Especially, this second common wire 73 is between the pixel electrode 75 of the pixel electrode 75 of left pixel region 41a and right pixel region 41b.Has coupling effect between two adjacent pixel electrodes 75 of this second common wire 73 less than the coupling effect between two adjacent pixel electrodes 75 that do not have this second common wire 73.Reduce the problem that coupling effect between two adjacent pixel electrodes 75 can solve bright line (bright line) and concealed wire (dark line).
Refer again to Figure 12, in first form of the 3rd embodiment, the difference of the thin-film transistor array base-plate of the 3rd and first embodiment is: described gate line 70 forms by exposure, development, etching the first metal layer (M1), and described data wire 71, first common wire 72 and second common wire 73 then all form by exposure, development, etching second metal level (M2).Passivation protection layer (not shown) is configured between this first metal layer and second metal level.This data wire 71 comprises 71a of first and second portion 71b.
A plurality of first through holes 781 are formed on this passivation protection layer, and correspond respectively to the described 71a of first.A plurality of second through holes 782 are formed in this passivation protection layer, and correspond respectively to described second portion 71b.Each conducting element 77 is used for the 71a of this first via this first through hole 781 and second through hole 782 and be electrically connected to this second portion 71b.71a of first and the conducting element between the second portion 71b 77 at this data wire 71 intersect leap with this first common wire 72.This conducting element 77 and pixel electrode 75 are made by transparent conductive material.In other words, this conducting element 77 can be formed by identical exposure, development, etching step simultaneously with pixel electrode 75, so can not increase the time and the cost of step.
Please refer to Figure 13, in second form of the 3rd embodiment, described gate line 70 forms by exposure, development, etching the first metal layer (M1), and described data wire 71, first common wire 72 and second common wire 73 then all form by exposure, development, etching second metal level (M2).Passivation protection layer (not shown) is configured between this first metal layer and second metal level.The difference of the thin-film transistor array base-plate of second and first form of the 3rd embodiment is: this first common wire 72 comprises 72a of first and second portion 72b.
A plurality of first through holes 781 ' are formed on this passivation protection layer, and correspond respectively to the described 72a of first.A plurality of second through holes 782 ' are formed in this passivation protection layer, and correspond respectively to described second portion 72b.Each conducting element 77 ' is used for the 72a of this first via this first through hole 781 ' and second through hole 782 ' and be electrically connected to this second portion 72b.72a of first and the conducting element between the second portion 72b 77 ' at this first common wire 72 intersect leap with this data wire 71.This conducting element 77 ' and pixel electrode 75 are made by transparent conductive material.In other words, this conducting element 77 ' can be formed by identical exposure, development, etching step simultaneously with pixel electrode 75, so can not increase the time and the cost of step.
Figure 14 is the schematic top plan view of thin-film transistor (TFT) array base palte 8 of a fourth embodiment in accordance with the invention.The thin-film transistor array base-plate 8 of this second embodiment is similar to the thin-film transistor array base-plate 2 of this first embodiment substantially, and wherein similar elements indicates similar label.This thin-film transistor array base-plate 8 comprises transparency carrier 40, a plurality of gate line 80, a plurality of data wire 81, a plurality of pixel electrode 85, a plurality of first common wire 82, a plurality of second common wire 83 and thin-film transistor 84.
This first common wire 82 is parallel to this gate line 80.This second common wire 83 is parallel to this data wire 81 and is electrically connected at this first common wire 82.Between left pixel region 41a and right pixel region 41b, so each second common wire 83 can be between left pixel region 41a and right pixel region 41b without any data line bit.Described pixel electrode 85 is disposed at respectively in the described pixel region 41.Especially, this second common wire 83 is between the pixel electrode 85 of the pixel electrode 85 of left pixel region 41a and right pixel region 41b.Has coupling effect between two adjacent pixel electrodes 85 of this second common wire 83 less than the coupling effect between two adjacent pixel electrodes 85 that do not have this second common wire 83.Reduce the problem that coupling effect between two adjacent pixel electrodes 85 can solve bright line (bright line) and concealed wire (dark line).
In the 4th embodiment, the difference of the thin-film transistor array base-plate of the 4th and first embodiment is: the described gate line 80 and second common wire 83 all form by exposure, development, etching the first metal layer (M1), and the described data wire 81 and first common wire 82 then all form by exposure, development, etching second metal level (M2).The gate insulator (not shown) is configured between this first metal layer and second metal level.Passivation protection layer (not shown) is configured on this first common wire 82.This first common wire 82 comprises 82a of first and second portion 82b, and this second common wire 83 comprises third part 83a and the 4th part 83b.
A plurality of first through holes 881 are formed in this passivation protection layer, and correspond respectively to the described 82a of first.A plurality of second through holes 882 are formed in this passivation protection layer, and correspond respectively to described second portion 82b.Each conducting element 87a is used for the 82a of this first via this first through hole 881 and second through hole 882 and be electrically connected to this second portion 82b.The 82a of first and the conducting element 87a between the second portion 82b and this data wire 81 crossing leaps at this first common wire 82.A plurality of third through-holes 883 are formed in this gate insulator, and correspond respectively to described third part 83a.A plurality of fourth holes 884 are formed in this gate insulator, and correspond respectively to described the 4th part 83b.Each conducting element 87b is used for this third part 83a via this third through-hole 883 and fourth hole 884 and be electrically connected to the 4th part 83b.Third part 83a and the conducting element 87b between the 4th part 83b and this gate line 80 crossing leaps at this second common wire 83.A plurality of fifth holes 885 are formed in this passivation protection layer, and correspond respectively to described first common wire 82.A plurality of the 6th through holes 886 are formed in this gate insulator, and correspond respectively to described second common wire 83.Each conducting element 87c is used for this first common wire 82 via this fifth hole 885 and the 6th through hole 886 and be electrically connected to this second common wire 83.This conducting element 87a, 87b, 87c and pixel electrode 85 are made by transparent conductive material.In other words, this conducting element 87a, 87b, 87c and pixel electrode 85 can be formed simultaneously by identical exposure, development, etching step, so can not increase the time and the cost of step.
Figure 15 is the schematic top plan view of thin-film transistor array base-plate 9 according to a fifth embodiment of the invention.The thin-film transistor array base-plate 9 of the 5th embodiment is similar to the thin-film transistor array base-plate 8 of the 4th embodiment substantially, and wherein similar elements indicates similar label.This thin-film transistor array base-plate 9 comprises transparency carrier 40, a plurality of gate line 90, a plurality of data wire 91, a plurality of pixel electrode 95, a plurality of first common wire 92, a plurality of second common wire 93 and thin-film transistor 94.
This first common wire 92 is parallel to this gate line 90.This second common wire 93 is parallel to this data wire 91 and is electrically connected at this first common wire 92.Between left pixel region 41a and right pixel region 41b, so each second common wire 93 can be between left pixel region 41a and right pixel region 41b without any data line bit.Described pixel electrode 95 is disposed at respectively in the described pixel region 41.Especially, this second common wire 93 is between the pixel electrode 95 of the pixel electrode 95 of left pixel region 41a and right pixel region 41b.Has coupling effect between two adjacent pixel electrodes 95 of this second common wire 93 less than the coupling effect between two adjacent pixel electrodes 95 that do not have this second common wire 93.Reduce the problem that coupling effect between two adjacent pixel electrodes 95 can solve bright line (bright line) and concealed wire (dark line).
In the 5th embodiment, the difference of the thin-film transistor array base-plate of the 5th and the 4th embodiment is: between two gate lines 90 of this first common wire 92 in two adjacent pixel regions 41 of arranging with upper-lower position.This first common wire 92 comprises 92a of first and second portion 92b, and this second common wire 93 comprises third part 93a and the 4th part 93b.
A plurality of first through holes 981 are formed in this passivation protection layer, and correspond respectively to the described 92a of first.A plurality of second through holes 982 are formed in this passivation protection layer, and correspond respectively to described second portion 92b.Each conducting element 97a is used for the 92a of this first via this first through hole 981 and second through hole 982 and be electrically connected to this second portion 92b.The 92a of first and the conducting element 97a between the second portion 92b and this data wire 91 crossing leaps at this first common wire 92.A plurality of third through-holes 983 are formed in this gate insulator, and correspond respectively to described third part 93a.A plurality of fourth holes 984 are formed in this gate insulator, and correspond respectively to described the 4th part 93b.Each conducting element 97b is used for this third part 93a via this third through-hole 983 and fourth hole 984 and be electrically connected to the 4th part 93b.Third part 93a and the conducting element 97b between the 4th part 93b and this gate line 90 crossing leaps at this second common wire 93.A plurality of fifth holes 985 are formed in this passivation protection layer, and correspond respectively to described first common wire 92.This conducting element 97b is used for this first common wire 92 is electrically connected to this second common wire 93 via this third through-hole 983, fourth hole 984 and fifth hole 985.This conducting element 97a, 97b and pixel electrode 95 are made by transparent conductive material.In other words, this conducting element 97a, 97b can be formed by identical exposure, development, etching step simultaneously with pixel electrode 95, so can not increase the time and the cost of step.
Please refer to Figure 16, it shows the circuit diagram of the thin-film transistor array base-plate 2 of first embodiment.This thin-film transistor array base-plate 2 comprises described gate line 20, data wire 21, pixel electrode 25, first common wire 22, second common wire 23 and thin-film transistor 24.Described second common wire 23 is electrically connected at described first common wire 22.Therefore, Figure 17 shows that described first common wire 22 and second common wire 23 constitute the network structure of the first embodiment of the present invention.In like manner, in second to the 5th embodiment, described second common wire of this thin-film transistor array base-plate is electrically connected at described first common wire, constitutes network structure by described first common wire and second common wire, so to reduce the resistance-capacitance signal delay effect of common wire.
With reference to Figure 18, it has shown liquid crystal panel 200.The thin-film transistor array base-plate 2 of this first embodiment can be applicable to this liquid crystal panel 200.This liquid crystal panel 200 comprises this thin-film transistor array base-plate 2, colored filter substrate 2 ' and liquid crystal layer 21 '.This liquid crystal layer 21 ' is positioned between this colored filter substrate 2 ' and this thin-film transistor array base-plate 2.This colored filter substrate 2 ' comprises black-matrix layer (black matrix layer) 28 ', chromatic filter layer 22 ' and transparency electrode 24 ', and it is formed on another transparency carrier 26 ' in regular turn.This black matrix" (black matrix) 28 ' must be corresponding to described gate line 20, data wire 21, pixel electrode 25 and second common wire 23, to avoid light leak.
With reference to Figure 19, it has shown LCD 2000.The liquid crystal panel 200 of this first embodiment can be applicable to this LCD 2000.This LCD 2000 comprises preceding frame 202, this liquid crystal panel 200 and module backlight 204.This module 204 backlight is to be used to provide light source to enter this liquid crystal panel 200, and is bonded to each other with this preceding frame 202 and this liquid crystal panel 200 and module backlight 204 are combined into this LCD 2000.
Though the present invention discloses as above with preferred embodiment; so it is not to be used to limit the present invention; any the technical staff in the technical field of the invention without departing from the spirit and scope of the present invention; can make change and change, so protection scope of the present invention should be as the criterion with claim institute restricted portion.
Claims (22)
1. thin-film transistor array base-plate, this thin-film transistor array base-plate comprises:
Transparency carrier;
Be disposed at a plurality of gate lines on this transparency carrier;
A plurality of data wires of intersect crossing over described gate line, wherein defining between two adjacent gate polar curves and two adjacent data lines has two pixel regions, and these two pixel regions are left pixel region and right pixel region;
A plurality of first common wires that are parallel to described gate line; And
A plurality of second common wires, these a plurality of second common wires are parallel to described data wire and are electrically connected at described first common wire, and wherein each second common wire is between the pixel electrode of the pixel electrode of described left pixel region and described right pixel region.
2. thin-film transistor array base-plate according to claim 1, wherein:
The quantity of described gate line is the N+1 bar, and the 1st is arranged on the described transparency carrier in regular turn to N+1 bar gate line, and N is a positive number;
When N is even number, between N bar to the N+1 bar gate line and two adjacent data lines and undefined any pixel region arranged; And
When N was odd number, definition had two pixel regions between N bar to the N+1 bar gate line and two adjacent data lines, and these two pixel regions are left pixel region and right pixel region.
3. thin-film transistor array base-plate according to claim 1, wherein without any data line bit between described left pixel region and described right pixel region.
4. thin-film transistor array base-plate according to claim 1, wherein said gate line and described first common wire all form by exposure, development, etching the first metal layer, and described data wire and described second common wire then form by exposure, development, etching second metal level.
5. thin-film transistor array base-plate according to claim 4, this thin-film transistor array base-plate also comprises:
Correspond respectively to a plurality of first through holes of described first common wire;
Correspond respectively to a plurality of second through holes of described second common wire; And
A plurality of conducting elements, each conducting element are used for described first common wire via described first through hole and described second through hole and be electrically connected to described second common wire.
6. thin-film transistor array base-plate according to claim 1, wherein said gate line, described first common wire and described second common wire all form by exposure, development, etching the first metal layer, and described data wire then forms by exposure, development, etching second metal level.
7. thin-film transistor array base-plate according to claim 6, wherein:
This gate line comprises first and second portion; And
This thin-film transistor array base-plate also comprises:
First through hole corresponding to described first;
Second through hole corresponding to described second portion; And
Conducting element is used for described first via described first through hole and described second through hole and be electrically connected to described second portion.
8. thin-film transistor array base-plate according to claim 7 wherein intersects at the first of described gate line and the conducting element between the second portion and described second common wire and crosses over.
9. thin-film transistor array base-plate according to claim 6, wherein:
Described second common wire comprises first and second portion; And
Described thin-film transistor array base-plate also comprises:
First through hole corresponding to described first;
Second through hole corresponding to described second portion; And
Conducting element is used for described first via this described first through hole and described second through hole and be electrically connected to described second portion.
10. thin-film transistor array base-plate according to claim 9 wherein intersects at the first of described second common wire and the conducting element between the second portion and described gate line and crosses over.
11. thin-film transistor array base-plate according to claim 1, wherein said gate line forms by exposure, development, etching the first metal layer, and described data wire, described first common wire and described second common wire then all form by exposure, development, etching second metal level.
12. thin-film transistor array base-plate according to claim 11, wherein:
This data wire comprises first and second portion; And
This thin-film transistor array base-plate also comprises:
First through hole corresponding to described first;
Second through hole corresponding to described second portion; And
Conducting element is used for described first via described first through hole and described second through hole and be electrically connected to described second portion.
13. thin-film transistor array base-plate according to claim 12 wherein intersects at the first of described data wire and the conducting element between the second portion and described first common wire and crosses over.
14. thin-film transistor array base-plate according to claim 11, wherein:
Described first common wire comprises first and second portion; And
Described thin-film transistor array base-plate also comprises:
First through hole corresponding to described first;
Second through hole corresponding to described second portion; And
Conducting element is used for described first via described first through hole and described second through hole and be electrically connected to described second portion.
15. thin-film transistor array base-plate according to claim 14 wherein intersects at the first of described first common wire and the conducting element between the second portion and described data wire and crosses over.
16. thin-film transistor array base-plate according to claim 1, wherein said gate line and described second common wire all form by exposure, development, etching the first metal layer, and described data wire and described first common wire then all form by exposure, development, etching second metal level.
17. thin-film transistor array base-plate according to claim 16, wherein:
Described first common wire comprises first and second portion;
Described second common wire comprises third part and the 4th part; And
Described thin-film transistor array base-plate also comprises:
First through hole corresponding to described first;
Second through hole corresponding to described second portion;
First conducting element is used for described first via described first through hole and described second through hole and be electrically connected to described second portion;
Third through-hole corresponding to described third part;
Corresponding to described tetrameric fourth hole;
Second conducting element is used for described third part via described third through-hole and described fourth hole and be electrically connected to described the 4th part;
Fifth hole corresponding to described first common wire;
The 6th through hole corresponding to described second common wire; And
The 3rd conducting element is used for described first common wire via described third through-hole and described fourth hole and be electrically connected to described second common wire.
18. thin-film transistor array base-plate according to claim 17, wherein intersect and cross over, and intersect leap with described gate line at the third part and second conducting element between the 4th part of described second common wire at the first of described first common wire and first conducting element between the second portion and described data wire.
19. thin-film transistor array base-plate according to claim 16 is between two gate lines of wherein said first common wire in two adjacent pixel regions of arranging with upper-lower position.
20. thin-film transistor array base-plate according to claim 19, wherein:
This first common wire comprises first and second portion;
This second common wire comprises third part and the 4th part; And
This thin-film transistor array base-plate also comprises:
First through hole corresponding to described first;
Second through hole corresponding to described second portion;
First conducting element is used for described first via described first through hole and described second through hole and be electrically connected to described second portion;
Third through-hole corresponding to described third part;
Corresponding to described tetrameric fourth hole;
Fifth hole corresponding to described first common wire; And
Second conducting element, be used for described third part is electrically connected to described the 4th part via described third through-hole, described fourth hole and described fifth hole, and described first common wire is electrically connected to described second common wire via described third through-hole, described fourth hole and described fifth hole.
21. thin-film transistor array base-plate according to claim 20, wherein intersect and cross over, and intersect leap with described gate line at the third part and second conducting element between the 4th part of described second common wire at the first of described first common wire and first conducting element between the second portion and described data wire.
22. a liquid crystal panel comprises:
Colored filter substrate;
Thin-film transistor array base-plate, this thin-film transistor array base-plate comprises:
Transparency carrier;
Be disposed at a plurality of gate lines on this transparency carrier;
A plurality of data wires of intersect crossing over described gate line, wherein defining between two gate lines and two adjacent data lines has two pixel regions, and these two pixel regions are left pixel region and right pixel region;
A plurality of first common wires that are parallel to described gate line; And
A plurality of second common wires, these a plurality of second common wires are parallel to described data wire and are electrically connected at described first common wire, and wherein each second common wire is between the pixel electrode of the pixel electrode of described left pixel region and described right pixel region; And
Liquid crystal layer, liquid crystal layer are disposed between described colored filter substrate and the described thin-film transistor array base-plate;
Wherein said colored filter substrate comprises black-matrix layer, and this black-matrix layer is corresponding to described second common wire.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/771,633 | 2010-04-30 | ||
| US12/771,633 US8035765B2 (en) | 2006-11-13 | 2010-04-30 | TFT array substrate, LCD panel and liquid crystal display |
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| CN102237355A true CN102237355A (en) | 2011-11-09 |
| CN102237355B CN102237355B (en) | 2012-12-26 |
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| CN 201010243210 Active CN102237355B (en) | 2010-04-30 | 2010-07-28 | TFT array substrate and LCD panel |
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Also Published As
| Publication number | Publication date |
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| TWI408476B (en) | 2013-09-11 |
| TW201137478A (en) | 2011-11-01 |
| CN102237355B (en) | 2012-12-26 |
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