KR101318436B1 - Thin Film Transistor Substrate and Method thereof - Google Patents

Abstract

The present invention relates to a thin film transistor substrate on which a low resistance wiring and an electrode are formed, and a method of manufacturing the same.

The thin film transistor substrate according to the present invention comprises: a first buffer layer formed on the substrate; A gate pattern formed on the first buffer layer and including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; A semiconductor pattern formed on the gate insulating layer covering the gate pattern to form a channel; A second buffer layer formed on the semiconductor pattern; A data pattern formed on the second buffer layer and including a data line, a source electrode connected to the data line, a drain electrode facing the source electrode with a channel interposed therebetween, and a data pad lower electrode; A passivation layer covering the data pattern and formed with a plurality of contact holes; And a transparent electrode pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode respectively connected to the drain electrode, the gate pad lower electrode, and the data pad lower electrode through the contact hole.

Description

Thin Film Transistor Substrate and Method for Manufacturing the Same

1 is a plan view of a thin film transistor substrate according to the present invention.

2 is a cross-sectional view of a thin film transistor substrate according to the present invention taken along lines II ′, II-II ′, and III-III ′.

FIG. 3 is an enlarged cross-sectional view of region A shown in FIG. 2.

4 is an enlarged cross-sectional view of region B shown in FIG. 2;

5A and 5B are a plan view and a cross-sectional view of a thin film transistor substrate having a first buffer layer and a gate pattern according to the present invention.

6A to 6D are process diagrams illustrating a process of forming a first buffer layer and a gate pattern according to the present invention.

7A and 7B are a plan view and a cross-sectional view of a thin film transistor substrate on which a semiconductor pattern, a second buffer layer, and a data pattern are formed.

8A to 8I are process diagrams illustrating a process of forming a semiconductor pattern, a second buffer layer, and a data pattern according to the present invention.

9A to 9B are plan and cross-sectional views of a thin film transistor substrate on which a passivation film having a plurality of contact holes is formed according to the present invention.

10A and 10B are process diagrams illustrating a process of forming a protective film having a plurality of contact holes according to the present invention.

11A and 11B are a plan view and a cross-sectional view of a thin film transistor substrate having a conductive pattern according to the present invention.

12A and 12B are process diagrams illustrating a process of forming a conductive pattern according to the present invention.

         <Explanation of symbols for the main parts of the drawings>

100 liquid crystal display device 101 substrate

110: first buffer layer 110a: first protective layer

120: gate pattern 120a: gate metal layer

121: gate line 123: gate electrode

125: gate pad 127: gate pad lower electrode

129: gate pad upper electrode 130: gate insulating film

140 semiconductor pattern 142 active layer

144: ohmic contact layer 150: second buffer layer

150a: second protective layer 160: data pattern

160a: data metal layer 161: data line

163: source electrode 164: drain electrode

165: data pad 167: data pad lower electrode

169: data pad upper electrode 170: protective film

171: first contact hole 172: second contact hole

173: third contact hole 174: fourth contact hole

180: pixel electrode 185: pixel region

190: storage capacitor 191: storage electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and more particularly, to a thin film transistor substrate having a low resistance wiring and an electrode and a method of manufacturing the same.

Recently, with the arrival of the information society, the importance of an image display device that performs dynamics as a transmission medium for providing various information to users has been emphasized more than ever.

The cathode ray tube or the cathode ray tube, which has been the mainstream of such an image display device, has a problem of weight and volume, and various kinds of flat panel displays have been developed to solve such problems. have.

The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electroluminescence (EL). Most of these are commercially available and commercially available.

Among them, the liquid crystal display device can satisfy the trend of light and short and short of electronic products, and the acidity is improved, and thus, the cathode ray tube or the cathode ray tube is rapidly replaced in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption, and secures the latest mass production technology. As a result of research and development, it is rapidly developing into larger size and higher resolution.

The conventional liquid crystal display device as described above displays an image by adjusting the light transmittance of the liquid crystal using an electric field. To this end, a liquid crystal display device includes a liquid crystal panel in which liquid crystal cells are arranged in a matrix form, and a driving circuit for driving the liquid crystal panel.

The liquid crystal display includes a thin film transistor substrate and a color filter substrate facing each other, a spacer positioned to maintain a constant cell gap between the two substrates, and a liquid crystal filled in the cell gap.

The thin film transistor substrate includes a gate line, a data line crossing the gate line to define a pixel region, a thin film transistor formed at an intersection of the gate line and the data line, a pixel electrode formed in liquid crystal cell units and connected to the thin film transistor, and coated thereon. Composed of aligned alignment films.

The thin film transistor may include a gate electrode electrically connected to a gate line, a gate insulating film covering the gate electrode, a semiconductor layer formed on the gate insulating film to form a channel and an ohmic resistor, a source electrode and a channel electrically connected to the data line. It is composed of a drain electrode facing the source electrode with the gap therebetween.

The color filter substrate includes a color filter formed in units of liquid crystal cells, a black matrix for distinguishing between color filters and reflecting external light, a common electrode supplying a reference voltage to the liquid crystal cells in common, and an alignment layer applied thereon.

Here, the liquid crystal display device is completed by separately manufacturing a thin film transistor substrate and a color filter substrate, and then injecting and encapsulating a liquid crystal.

In the liquid crystal display device as described above, the wirings and electrodes constituting the liquid crystal display device are formed mainly using copper (Cu) or the like, which is a low resistance metal having a low material terminal.

In this case, the copper (Cu) constituting the wiring and the electrode has a problem that peeling phenomenon occurs in which the wiring and the electrode are peeled off from the substrate as the electron mobility is good while the adhesion to the substrate is decreased.

In addition, when copper (Cu) is exposed to a humid external environment, there is also a problem in that electrical conductivity is degraded as an oxide film is generated on the surface due to oxidation.

Therefore, the conventional liquid crystal display device has a limitation in forming a wiring and an electrode by using a low resistance metal such as copper (Cu) due to the above problems.

SUMMARY OF THE INVENTION In order to solve the conventional problems as described above, an object of the present invention is to provide a thin film transistor substrate having a wiring and an electrode formed of a low resistance metal and a method of manufacturing the same.

SUMMARY OF THE INVENTION The present invention provides a thin film transistor substrate and a method of manufacturing the same, by forming a buffer layer of a molybdenum-zinc alloy on a substrate and then depositing wiring and electrodes, thereby increasing adhesion of the wiring and the electrode to the substrate and the insulating film. The purpose is.

According to the present invention, a zinc metal constituting the buffer layer is diffused to the surface of the wiring and the electrode to form a protective layer for oxidation prevention, thereby preventing the oxidation of the wiring and the electrode to lower the contact resistance between the transparent electrode and the terminal electrode. And the purpose is to provide a method for producing the same.

An object of the present invention is to provide a thin film transistor substrate having a large area and a high definition by forming a low resistance wiring and an electrode through a buffer layer formed on the substrate, and a method of manufacturing the same.

In order to achieve the above object, the thin film transistor substrate 101 constituting the liquid crystal display device according to the present invention, the first buffer layer 110 formed on the substrate 101; A gate pattern 120 formed on the first buffer layer 110 and including a gate line 121, a gate electrode 123 connected to the gate line 121, and a gate pad lower electrode 127; A semiconductor layer 140 formed on the gate insulating layer 130 covering the gate pattern 120 to form a channel; A second buffer layer 150 formed on the semiconductor layer 140; A data line 161, a source electrode 163 connected to the data line 161, a drain electrode 164 facing the source electrode 163 with a channel interposed therebetween, and formed on the second buffer layer 150. A data pattern 160 including a pad lower electrode 167; A passivation layer 170 covering the data pattern 160 and formed with a plurality of contact holes 171, 172, 173, and 174; And a pixel electrode 180, a gate pad upper electrode 129, and a data pad upper electrode 169 connected to the drain electrode 164, the gate pad lower electrode 127, and the data pad lower electrode 167 through contact holes, respectively. It characterized in that it is composed of a transparent electrode pattern including.

Here, the thin film transistor substrate according to the present invention, the gate line 121; And a storage capacitor 190 including a storage electrode 191 formed to overlap the gate line 121 via the gate insulating layer 130 and the passivation layer 170, wherein the storage electrode 191 is formed as a second electrode. It is formed on the buffer layer 150.

The gate pattern 120 turns constituting the thin film transistor substrate according to the present invention may be formed of a low resistance metal including copper (Cu).

The data pattern 160 constituting the thin film transistor substrate according to the present invention is formed of a low resistance metal including copper (Cu).

The first buffer layer 110 constituting the thin film transistor substrate according to the present invention is characterized in that the molybdenum-zinc alloy (Mn-Zn alloy).

When depositing the gate pattern 120 on the first buffer layer 110 according to the present invention, the zinc of the first buffer layer 110 is diffused to the surface of the gate pattern 120 to block the contact with the external environment It is characterized by forming a protective layer (110a).

The second buffer layer 150 constituting the thin film transistor substrate according to the present invention is characterized in that the molybdenum-zinc alloy (Mn-Zn alloy).

When depositing the data pattern 160 on the second buffer layer 150 according to the present invention, the zinc of the second buffer layer 150 is diffused to the surface of the data pattern 160 to block contact with the external environment. It is characterized by forming a protective layer (150a).

When depositing the storage electrode 191 on the second buffer layer 150 according to the present invention, the zinc of the second buffer layer 150 is diffused to the surface of the storage electrode 191 to block the contact with the external environment The second protective layer 150a is also formed.

In addition, the method for manufacturing a thin film transistor substrate according to the present invention includes forming a first buffer layer 110 on a substrate 101; Forming a gate pattern 120 including a gate line 121, a gate electrode 123 connected to the gate line 121, and a gate pad lower electrode 127 on the first buffer layer 110; Forming a semiconductor pattern 140 constituting a channel on the gate insulating layer 130 covering the gate pattern 120; Forming a second buffer layer 150 on the semiconductor pattern 140; On the second buffer layer 150, a data line 161, a source electrode 163 connected to the data line 161, a drain electrode 164 facing the source electrode 163 through a channel, and a data pad lower electrode Forming a data pattern 160 comprising 167; Forming a passivation layer 170 covering the data pattern 160 and having a plurality of contact holes 171, 172, 173, and 174; And a pixel electrode 180, a gate pad upper electrode 129, and a data pad upper electrode 169 connected to the drain electrode 164, the gate pad lower electrode 127, and the data pad lower electrode 167 through contact holes, respectively. Forming a transparent electrode pattern comprising a) characterized in that it comprises a.

Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment according to the present invention.

First, the configuration and operation of a thin film transistor substrate according to the present invention will be described with reference to FIGS. 1 and 2. 1 is a plan view of a thin film transistor substrate according to the present invention, and FIG. 2 is a cross-sectional view of the thin film transistor substrate taken along lines II ′, II-II ′, and III-III ′ of FIG. 1.

1 and 2, the thin film transistor substrate according to the present invention may include a first buffer layer 110 formed on the substrate 101, a gate line 121 formed on the first buffer layer 110, and a gate line 121. ), The gate insulating layer 130 covering the gate insulating layer 130, the second buffer layer 150 formed on the gate insulating layer 130, and the data intersecting the gate line 121 on the second buffer layer 150 to define the pixel region 185. The passivation layer 170 and the passivation layer 170 covering the thin film transistor T formed at each intersection of the line 161, the gate line 121, and the data line 161, and the thin film transistor T formed on the gate insulating layer 130. The pixel electrode 180 is connected to the thin film transistor T through a contact hole penetrating through the transistor, and a storage capacitor 190 formed at an overlapping portion of the gate line 121 and the pixel electrode 180.

The thin film transistor T further includes a gate pad 165 connected to the gate line 121, and a data pad 165 connected to the data line 161.

The first buffer layer 110 is formed on the substrate 101 and includes a metal oxide (Mn-Mn) layer (Mn) including a metal which is rapidly oxidized compared to copper (Cu), which is a low resistance metal constituting the gate line 121 or the like. -Zn alloy layer).

Here, in the case of depositing the gate metal layer to form the gate pattern 120 including the gate line 121 and the like on the first buffer layer 110, as shown in FIG. Zinc (Zn) included in the first buffer layer 110 diffuses to the surface of the gate metal layer by the heat.

In this case, zinc (Zn) included in the first buffer layer diffused into the gate metal layer forms the first protective layer 110a that blocks the gate metal layer from the external environment.

The gate line 121 transfers a gate signal supplied from a gate driver (not shown) connected to the gate pad 165 to the gate electrode 123 constituting the thin film transistor T.

In this case, the gate line 121 is formed on the first buffer layer 110 through a deposition method such as sputtering using copper (Cu), which is a low resistance metal.

Here, the surface of the gate line 121 is covered with a first protective layer 110a formed by zinc (Zn) diffused from the first buffer layer 110 by heat generated in a deposition process such as sputtering, and the first protection The layer 110a serves to prevent the surface of the gate line 121 from oxidizing.

The second buffer layer 150 is formed on the gate insulating layer 130, and includes a metal that is rapidly oxidized compared to copper (Cu), which is a low resistance metal constituting the data line 161. -Zn alloy layer).

Here, in the case of depositing the data metal layer to form the data pattern 160 including the data line 161 and the like on the second buffer layer 150, as shown in FIG. Zinc (Zn) included in the second buffer layer 150 diffuses to the surface of the data metal layer by heat.

In this case, zinc (Zn) included in the second buffer layer 150 diffused into the data metal layer forms a second protective layer 150a that blocks the data metal layer from the external environment.

The data line 161 includes a source electrode 163 and a drain constituting the thin film transistor T by interlocking a data signal supplied from a data driver (not shown) connected to the data pad 165 with ON / OFF of the gate electrode. It serves to transfer to the electrode 164.

In this case, the data line 161 is formed on the second buffer layer 150 through a deposition method such as sputtering using copper (Cu), which is a low resistance metal.

Here, the surface of the data line 161 is covered with a second protective layer 150a formed by zinc (Zn) diffused from the second buffer layer 150 by heat generated in a deposition process such as sputtering, and the second protection The layer 150a serves to prevent the surface of the data line 161 from oxidizing.

The thin film transistor T serves to charge the pixel electrode 180 of the data line 161 to the pixel electrode 180 in response to the gate signal of the gate line 121. The thin film transistor T is connected to the gate line 121. Pixels through a first contact hole 171 facing the source electrode 163 with the electrode 123, the source electrode 163 connected to the data line 161, and a channel interposed therebetween, and penetrating the passivation layer 170. A drain electrode 164 connected to the electrode 180 is provided.

Here, the thin film transistor T overlaps the gate electrode 123 with the gate insulating layer 130 interposed therebetween, and forms an active layer 142 and an ohmic that forms a channel between the source electrode 163 and the drain electrode 164. The semiconductor pattern 140 further includes a contact layer 144.

Here, the active layer 142 is also formed to overlap with the data pad lower electrode 165. In this case, an ohmic contact layer 144 for ohmic contact with the source electrode 163, the drain electrode 164, and the data pad lower electrode 165 is further formed on the active layer 142.

At this time, the gate electrode 123 connected to the gate line 121 is covered with a first protective layer 110a formed of zinc (Zn) diffused from the first buffer layer 110, and the first protective layer. 110a serves to prevent the surface of the gate electrode 123 from being oxidized.

In addition, the surface of the drain electrode 164 facing the source electrode 163 with the source electrode 163 electrically connected to the data line 161 and the channel therebetween may have zinc diffused from the second buffer layer 150. The second protective layer 150a is formed of Zn), and the second protective layer 150a serves to prevent the surfaces of the source electrode 163 and the drain electrode 164 from being oxidized.

The passivation 170 covers the thin film transistor T formed on the gate insulating layer 130, and at the same time, the active layer 142 and the pixel region 185 forming the channel may be exposed to moisture or scratches. protects against scratches.

The passivation layer 170 may include a gate insulating layer 130 by sputtering or PECVD using an inorganic insulating material such as silicon nitride, an organic organic compound such as acryl-based organic compound, BCB (benzocyclobutene), or PFCB (perfluorocyclobutane). Is deposited on the substrate.

In this case, the first to fourth contact holes 171, 172, 173, and 174 are formed in the passivation layer 170 through a photolithography process and an etching process using a mask. Here, the first contact hole 171 passes through the passivation layer 170 to expose the drain electrode 164, and the second contact hole 172 passes through the passivation layer 170 to expose the storage electrode 191. The third contact hole 173 penetrates the passivation layer 170 and the gate insulating layer 130 to expose the gate pad lower electrode 125, and the fourth contact hole 174 penetrates the passivation layer 170 to lower the data pad. The electrode 167 is exposed.

The pixel electrode 180 is connected to the drain electrode 164 of the thin film transistor T through the first contact hole 171 passing through the passivation layer 170 and is formed in the pixel region 185. In this case, an electric field is formed between the pixel electrode 180 supplied with the pixel signal through the thin film transistor T and a common electrode (not shown) supplied with the reference voltage.

Therefore, the liquid crystal molecules filled between the substrates are rotated by dielectric anisotropy by the electric field formed between the pixel electrode 180 and the common electrode, and the light transmittance of the liquid crystal molecules passing through the pixel region 185 depends on the degree of rotation of the liquid crystal molecules. By changing, the gray scale is realized.

The storage capacitor 190 has a shape in which the storage electrode 191 and the previous gate line 121 overlap each other with the gate insulating layer 130 and the passivation layer 170 interposed therebetween. The storage electrode 191 is electrically connected to the pixel electrode 180 through the second contact hole 172 formed in the passivation layer 170.

The storage capacitor 190 configured as described above serves to stably maintain the pixel signal charged in the pixel electrode 180 until the next pixel signal is charged.

The gate pad 125 is connected to a gate driver (not shown) to supply a gate signal to the gate line 121.

The gate pad 125 may include a third contact hole 173 and a third contact hole 173 penetrating the gate pad lower electrode 127, the gate insulating layer 130, and the passivation layer 170 extending from the gate line 121. And a gate pad upper electrode 129 connected to the gate pad lower electrode 127 through the.

In this case, the gate pad lower electrode 127 is covered with a first passivation layer 110a formed of zinc (Zn) diffused from the first buffer layer 110, and the first passivation layer 110a is formed under the gate pad. It serves to prevent the surface of the electrode 125 is oxidized.

The data pad 165 is connected to a data driver (not shown) to supply a data signal to the data line 161.

The data pad 165 may have a data pad lower electrode 167 extending from the data line 161, a fourth contact hole 174 penetrating through the passivation layer 170, and a lower portion of the data pad through the fourth contact hole 174. The data pad upper electrode 169 is connected to the electrode 167.

At this time, the lower surface of the data pad electrode 167 is covered with a second protective layer 150a formed of zinc (Zn) diffused from the second buffer layer 150, and the second protective layer 150a is disposed below the data pad. It serves to prevent the surface of the electrode 165 is oxidized.

Hereinafter, a method of manufacturing a thin film transistor substrate according to the present invention will be described in detail with reference to the accompanying drawings.

First, a process of forming a buffer metal layer and a gate pattern constituting the thin film transistor substrate according to the present invention will be described.

5A and 5B, the first buffer layer 110, the gate line 121, the gate electrode 123, and the gate pad lower electrode 127 are formed on the substrate 101 using the first mask process. A gate pattern 120 including the ()) is formed.

More specifically, as shown in FIG. 6A, the first buffer layer 110 including the Mn-Zn alloy layer is formed on the substrate 101.

Thereafter, as illustrated in FIG. 6B, the gate metal layer 120a is formed on the first buffer layer 110 through a deposition method such as sputtering. Here, the gate metal layer 120a may be formed of copper (Cu) having a low resistance value, but is not limited thereto. Other low-resistance metals may be used in forming the gate metal layer 120a.

At this time, as shown in Figure 6c, the zinc (Zn) component constituting the first buffer layer 110 by the heat generated when the gate metal layer 120a is deposited through a deposition method such as sputtering is formed of the gate metal layer 120a Diffusion to the surface forms a first protective layer 110a that blocks the gate metal layer 120a from the external environment.

Thereafter, the first protective layer 120a, the gate metal layer 120a, and the first buffer layer 120 are patterned through a photolithography process and an etching process using the first mask, as shown in FIG. 6D. A gate pattern 120 including a gate line 121, a gate electrode 123 connected to the gate line 121, and a gate pad lower electrode 127 is formed.

As described above, after the first buffer layer 110 and the gate pattern 120 are formed on the substrate 101, the semiconductor pattern 140, the second buffer layer 150, and constituting the thin film transistor substrate according to the present invention; The data pattern 160 is formed.

As shown in FIGS. 7A and 7B, a semiconductor pattern including a gate insulating layer 130, an active layer 142 for forming a channel, and an ohmic contact layer 144 may be formed on a substrate 101 using a second mask process. 140, two buffer layers 150, and a data pattern 160 are formed.

In more detail, as illustrated in FIG. 8A, the gate insulating layer 130 is entirely deposited on the substrate 101 on which the first buffer layer 110 and the gate pattern 120 are formed. The gate insulating layer 130 is formed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

Subsequently, as shown in FIG. 8B, the active layer 142, the ohmic contact layer 144, the second buffer layer 150, and the data metal layer 160a are deposited on the gate insulating layer 130 by a deposition method such as PECVD or sputtering. Are deposited sequentially.

Here, the active layer 142 is composed of an amorphous silicon layer 134a, the ohmic contact layer 144 is composed of an n + amorphous silicon layer, and the second buffer layer 150 is the same as that of the first buffer layer 110. It consists of an alloy layer (Mn-Zn alloy layer).

In this case, as shown in FIG. 8C, the zinc (Zn) component constituting the second buffer layer 150 is formed by the heat generated when the data metal layer 160 is deposited through a deposition method such as sputtering. A second passivation layer 150a is formed to diffuse to the surface of the second blocking layer to block the data metal layer 160a from the external environment.

Subsequently, as shown in FIG. 8D, a photoresist pattern having a predetermined shape is formed on the data metal layer 160a through a photolithography process using a second mask. At this time. By using a diffraction exposure mask having a diffraction exposure portion in the channel region of the thin film transistor T as the second mask, the photoresist pattern formed in the channel region is formed to have a lower height than other regions.

After the photoresist pattern PR is formed on the data metal layer 160a as described above, as shown in FIG. 8E, the wet etching of the data metal layer 160a exposed by the photoresist pattern PR is performed. etching).

Subsequently, by removing the photoresist pattern PR covering the channel region through an ashing process using an oxygen (O ₂ ) plasma, as illustrated in FIG. 8F, the data metal layer 160a formed in the channel region is removed. Expose

Then, as shown in FIG. 8G, the exposed data metal layer 160a is removed by dry etching, thereby allowing the data line 161, the source electrode 163 connected to the data line 161, and A data pattern 160 including a drain electrode 164, a data pad lower electrode 167, and a storage electrode 191 facing the source electrode 163 is formed through the channel region.

In this case, as the source electrode 163 and the drain electrode 164 constituting the data pattern 160 are separated, the ohmic contact layer 144 formed on the channel region is exposed to the outside.

Thereafter, the exposed ohmic contact layer 144 is removed by dry etching, and as shown in FIG. 8H, a channel between the source electrode 163 and the drain electrode 164 of the thin film transistor T is removed. Open the active layer 142 to form a.

Next, as shown in FIG. 8I, the photoresist pattern PR remaining on the data pattern 160 is finally removed.

After the semiconductor pattern 140, the second buffer layer 150, and the data pattern 160 are formed as described above, the passivation layer 170 constituting the thin film transistor substrate according to the present invention is formed.

9A and 9B, a passivation layer 170 having first to fourth contact holes 171, 172, 173, and 174 is formed on the substrate 101 by using a third mask process.

In more detail, as shown in FIG. 10A, the passivation layer 170 is entirely formed on the gate insulating layer 130 on which the data pattern 160 is formed through a deposition method such as PECVD.

Thereafter, by performing a photolithography process and an etching process on the passivation layer 170 using the third mask, as shown in FIG. 10B, the first to fourth contact holes 171, 172, 173, 174 are formed on the passivation layer 170. Is formed.

Here, the first contact hole 171 passes through the passivation layer 170 to expose the drain electrode 164, and the second contact hole 172 passes through the passivation layer 170 to expose the storage electrode 191. The third contact hole 173 penetrates the passivation layer 150 and the gate insulating layer 130 to expose the gate pad lower electrode 127, and the fourth contact hole 174 penetrates the passivation layer 150 to lower the data pad. The electrode 167 is exposed.

After the protective film 170 having the plurality of contact holes is formed as described above, a transparent electrode pattern constituting the thin film transistor substrate according to the present invention is formed.

11A and 11B, a transparent electrode pattern including a pixel electrode 180, a gate pad upper electrode 129, and a data pad upper electrode 169 is formed on the passivation layer 170 through a fourth mask process. Form.

More specifically, as illustrated in FIG. 12A, the transparent electrode material ITO is deposited on the entire surface of the passivation layer 170 on which the plurality of contact holes are formed through a deposition method such as sputtering.

In this case, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) may be used as the transparent electrode material.

Subsequently, the transparent electrode material ITO is patterned through a photolithography process and an etching process using a fourth mask, so that the pixel electrode 180 and the gate pad are formed on the passivation layer 170 as shown in FIG. 12B. A transparent electrode pattern including an upper electrode 129 and a data pad upper electrode 169 is formed.

Here, the pixel electrode 180 is electrically connected to the drain electrode 164 of the thin film transistor T through the first contact hole 171 formed in the passivation layer 170 and at the same time through the second contact hole 172. It is electrically connected to the storage electrode 191.

In addition, the gate pad upper electrode 129 is electrically connected to the gate pad lower electrode 127 through the third contact hole 173 formed in the passivation layer 170, and the data pad upper electrode 169 is connected to the fourth contact hole. It is electrically connected to the data pad lower electrode 167 through 174.

As described above, the present invention has the effect of providing a large area and a high definition for the thin film transistor substrate by forming a wiring and an electrode using a low resistance metal.

In addition, the present invention has the effect of increasing the adhesion of the wiring and the electrode to the substrate and the insulating film by depositing the wiring and the electrode after forming a buffer layer composed of a molybdenum alloy on the substrate.

In addition, according to the present invention, the zinc metal constituting the buffer layer is diffused to the surface of the wiring and the electrode to form an oxidation protection protective layer, thereby preventing the oxidation of the wiring and the electrode to lower the contact resistance between the transparent electrode and the terminal electrode. Has

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.

Claims (27)

In a thin film transistor constituting a liquid crystal display device, A first buffer layer formed on the substrate; A gate pattern formed on the first buffer layer and including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; A semiconductor layer formed on the gate insulating layer covering the gate pattern to form a channel; A second buffer layer formed on the semiconductor layer; And A data pattern formed on the second buffer layer and including a data line, a source electrode connected to the data line, a drain electrode facing the source electrode with the channel interposed therebetween, and a data pad lower electrode; And a first passivation layer formed by diffusing zinc ions contained in the first buffer layer onto a surface of the gate pattern. The method of claim 1, The gate line; Further comprising a storage capacitor comprising a storage electrode formed to overlap the gate line via the gate insulating film and the protective film, And the storage electrode is formed on the second buffer layer. The method of claim 1, A passivation layer covering the data pattern and formed with a plurality of contact holes; And And a transparent electrode pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode connected to the drain electrode, the gate pad lower electrode, and the data pad lower electrode, respectively, through the contact hole. Board. The method of claim 1, At least one of the gate pattern and the data pattern is formed of a low resistance metal including copper (Cu). delete delete delete The method of claim 1, At least one of the first buffer layer and the second buffer layer is a thin film transistor substrate, characterized in that the molybdenum-zinc alloy (Mn-Zn alloy). delete delete The method of claim 2, And a second passivation layer formed by diffusing zinc ions contained in the second buffer layer onto the surface of the data pattern. The method of claim 11, The second protective layer is a thin film transistor substrate, characterized in that the diffusion to the surface of the storage electrode. In the manufacturing method of a thin film transistor substrate constituting a liquid crystal display device Forming a first buffer layer on the substrate; Forming a gate pattern on the first buffer layer, the gate pattern including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; Forming a semiconductor layer constituting a channel on a gate insulating film covering the gate pattern; Forming a second buffer layer on the semiconductor layer; And Forming a data pattern on the second buffer layer, the data pattern including a data line, a source electrode connected to the data line, a drain electrode facing the source electrode through the channel, and a data pad lower electrode; The forming of the gate pattern on the first buffer layer further includes forming a first passivation layer to diffuse metal ions contained in the first buffer layer onto the surface of the gate pattern. The metal ions forming the first protective layer are zinc ions contained in the first buffer layer. 14. The method of claim 13, The method may further include forming a storage capacitor including a storage electrode overlapping the gate line, the gate insulating layer, and the passivation layer. And the storage electrode is formed on the second buffer layer. 14. The method of claim 13, Forming a passivation layer covering the data pattern and having a plurality of contact holes; And And forming a transparent electrode pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode respectively connected to the drain electrode, the gate pad lower electrode, and the data pad lower electrode through the contact hole. The manufacturing method of a thin film transistor board | substrate. delete 14. The method of claim 13, The forming of the data pattern on the second buffer layer further includes forming a second passivation layer to diffuse metal ions contained in the second buffer layer onto a surface of the data pattern. And a metal ion forming the second protective layer is zinc ion contained in the second buffer layer. 14. The method of claim 13, At least one of the gate pattern and the data pattern is formed of a low resistance metal including copper (Cu). delete delete delete 14. The method of claim 13, At least one of the first buffer layer and the second buffer layer is a method of manufacturing a thin film transistor substrate, characterized in that the molybdenum-zinc alloy (Mn-Zn alloy). delete delete delete 15. The method of claim 14, The forming of the storage electrode on the second buffer layer may include forming a second protective layer that diffuses metal ions contained in the second buffer layer onto a surface of the storage electrode to block contact with an external environment. It is configured to include more And the metal ions forming the second protective layer are zinc ions contained in the second buffer layer. delete

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