KR101285535B1 - Thin Film Transistor Substrate and Method thereof - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate capable of reducing wiring resistance and improving aperture ratio by forming a gate pattern on a substrate etched to a predetermined depth, and a method of manufacturing the same.

A thin film transistor substrate according to the present invention includes a substrate etched to a predetermined depth; A seed metal layer formed along the etch region of the substrate; A gate pattern formed to correspond to the seed metal layer and including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; A semiconductor pattern formed on the gate insulating film covering the gate pattern and forming a channel; And a data pattern formed on the semiconductor pattern and including a data line, a source electrode connected to the data line, a drain electrode facing the source electrode with a channel interposed therebetween, and a data pad lower electrode.

Description

Thin Film Transistor Substrate and Method for Manufacturing the Same

1 is a perspective view of a liquid crystal display device to which the present invention is applied.

2 is a plan view of a conventional thin film transistor substrate.

3 is a cross-sectional view of the thin film transistor substrate illustrated in FIG. 2.

4 is a plan view of a thin film transistor substrate according to an embodiment of the present invention.

FIG. 5 is a cross-sectional view of the thin film transistor substrate taken along lines II ′, II-II ′, and III-III ′ of FIG. 4.

6A and 6B are plan and cross-sectional views of a thin film transistor substrate on which a seed metal layer is formed according to an embodiment of the present invention.

7A to 7D are process diagrams illustrating a process of forming a seed metal layer according to an embodiment of the present invention.

8A and 8B are a plan view and a cross-sectional view of a thin film transistor substrate having a gate pattern according to an embodiment of the present invention.

9A and 9B are plan and cross-sectional views of a thin film transistor substrate on which a semiconductor pattern and a data pattern are formed for channel formation according to an embodiment of the present invention.

10A to 10H are process diagrams illustrating a process of forming a semiconductor pattern and a data pattern according to an embodiment of the present invention.

11A and 11B are plan and cross-sectional views of a thin film transistor substrate on which a passivation layer having a plurality of contact holes is formed, according to an embodiment of the present invention.

12A and 12B are plan and cross-sectional views of a thin film transistor substrate on which a conductive pattern is formed, according to an embodiment of the present invention.

13 is a plan view of a thin film transistor substrate according to another exemplary embodiment of the present invention.

FIG. 14 is a cross-sectional view of the thin film transistor substrate taken along lines II ′, II-II ′, and III-III ′ of FIG. 13.

15A and 15B are a plan view and a cross-sectional view of a thin film transistor substrate on which a seed metal layer is formed, according to another embodiment of the present invention.

16A-16D are process diagrams illustrating a process of forming a seed metal layer according to another embodiment of the present invention.

17A and 17B are a plan view and a cross-sectional view of a thin film transistor substrate on which a gate pattern is formed, according to another exemplary embodiment.

18A to 18D are flowcharts illustrating a process of forming a gate pattern according to another exemplary embodiment of the present invention.

19A and 19B are a plan view and a cross-sectional view of a thin film transistor substrate on which a semiconductor pattern and a data pattern are formed for channel formation according to another embodiment of the present invention.

20A and 20B are plan views and cross-sectional views of a thin film transistor substrate on which a passivation layer with a plurality of contact holes is formed, according to another exemplary embodiment.

21A and 21B are a plan view and a cross-sectional view of a thin film transistor substrate on which a conductive pattern is formed, according to another embodiment of the present invention.

         <Explanation of symbols for the main parts of the drawings>

100,200: thin film transistor substrate 101,201: substrate

110,210: seed metal layer 120,220: gate pattern

122,222: gate line 124,224: gate electrode

130,230 gate insulating film 135,235 semiconductor pattern

137,237: active layer 139,239: ohmic contact layer

140,240: data pattern 142,242: data line

144,244 Source electrode 146,246 Drain electrode

T: thin film transistor 150250: protective film

151,251: First contact hole 152,252: Second contact hole

153,253: third contact hole 154,254: fourth contact hole

160,260 pixel electrode 165,265 pixel area

170270: storage capacitor 172272: storage electrode

180, 280: gate pad 182, 282: gate pad lower electrode

184,284: gate pad upper electrode 190: data pad

192,292: Data pad lower electrode 194,294: Data pad upper electrode

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor substrate and a method of manufacturing the same, and to a thin film transistor substrate and a method of manufacturing the same, which reduce wiring resistance and improve aperture ratio by forming a gate pattern on a substrate etched to a predetermined depth.

Recently, with the arrival of the information society, the importance of an image display device that performs dynamics as a transmission medium for providing various information to users has been emphasized more than ever.

The cathode ray tube or the cathode ray tube, which has been the mainstream of such an image display device, has a problem of weight and volume, and various kinds of flat panel displays have been developed to solve such problems. have.

The flat panel display device includes a liquid crystal display (LCD), a field emission display (FED), a plasma display panel (PDP) and an electroluminescence (EL). Most of these are commercially available and commercially available.

Among these, liquid crystal display devices can satisfy the trend of light and short and short of electronic products and have improved mass productivity, and are rapidly replacing cathode ray tubes or CRTs in many applications.

In particular, an active matrix type liquid crystal display device that drives a liquid crystal cell using a thin film transistor (hereinafter referred to as "TFT") has the advantages of excellent image quality and low power consumption, and secures the latest mass production technology. As a result of research and development, it is rapidly developing into larger size and higher resolution.

A configuration and an operation of the liquid crystal display as described above with reference to FIG. 1 will be described below.

The liquid crystal display device displays an image by adjusting the light transmittance of the liquid crystal using an electric field. As shown in FIG. 1, the thin film transistor substrate 70 and the color filter substrate 80 maintain a constant cell gap between the two substrates. And a liquid crystal 90 filled in the cell gap and a spacer positioned for the purpose.

2 and 3, the thin film transistor substrate 70 includes a gate line 72 and a data line 73 formed to intersect on the substrate 1 with a gate insulating layer 71 interposed therebetween. The pixel electrode 76 connected to the thin film transistor 74 through the thin film transistor 74 formed at the intersection of the 72 and 73 and the contact hole formed in the protective film 75 covering the thin film transistor 74, and And a lower alignment film coated for liquid crystal alignment.

In this case, the thin film transistor 74 includes a source electrode 77 connected to the data line 73, a drain electrode 78 facing the source electrode with a channel therebetween, and a semiconductor pattern 79 forming a channel. . In this case, the semiconductor pattern is in an ohmic contact with the active layer 79a that forms a channel between the source electrode 77 and the drain electrode 78, and is positioned on the active layer 79a to form a source electrode 77 and a drain electrode 78. Ohmic contact layer (79b) to perform the.

The color filter substrate 80 includes a black matrix 81 for preventing light leakage, a color filter 82 for color implementation, a common electrode 83 forming a vertical electric field with the pixel electrode 74, and an upper portion coated for liquid crystal alignment. The alignment film 84 is comprised.

Here, the liquid crystal display device is completed by separately manufacturing a thin film transistor substrate and a color filter substrate, and then injecting and encapsulating a liquid crystal.

Conventionally, in the thin film transistor substrate constituting the liquid crystal display device as described above, as shown in FIG. 3, the gate pattern including the gate line 72 or the like is formed on the substrate through a deposition method such as sputtering. It was formed by vapor deposition on.

In this case, when the gate metal is deposited to form a gate pattern on the substrate, the gate metal is deposited by widening the line width in order to reduce the resistance of the wiring because the deposition speed of the gate metal is low.

As a result, as the line width of the gate pattern formed on the substrate is increased, not only the aperture ratio is decreased but also the signal delay due to the wiring resistance is generated as the panel is larger.

DISCLOSURE OF THE INVENTION In order to solve the conventional problems as described above, it is an object of the present invention to provide a thin film transistor substrate and a method of manufacturing the same that can reduce the gate wiring resistance by forming a gate pattern on the substrate etched to a predetermined depth.

In addition, the present invention is to provide a thin film transistor substrate and a method of manufacturing the same that can improve the aperture ratio by forming a gate pattern on the substrate etched to a predetermined depth to reduce the line width.

In order to achieve the above object, a thin film transistor substrate according to the present invention, a substrate etched to a predetermined depth; A seed metal layer formed along the etch region of the substrate; A gate pattern formed to correspond to the seed metal layer and including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; A semiconductor pattern formed on the gate insulating film covering the gate pattern and forming a channel; And a data pattern formed on the semiconductor pattern and including a data line, a source electrode connected to the data line, a drain electrode facing the source electrode with a channel interposed therebetween, and a data pad lower electrode.

Here, the thin film transistor substrate according to the present invention, the gate line; And a storage capacitor including a storage electrode formed to overlap the gate line through the gate insulating layer and the passivation layer.

In addition, the thin film transistor substrate according to the present invention comprises: a protective film covering a data pattern and formed with a plurality of contact holes; And a transparent electrode pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode respectively connected to the drain electrode, the gate pad lower electrode, and the data pad lower electrode through the contact hole.

At this time, the gate pattern according to the invention is characterized in that formed through the electroplating using the seed metal layer as an electrode.

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Here, the thin film transistor substrate according to the present invention, the gate line; And a storage capacitor including a storage electrode formed to overlap the gate line through the gate insulating layer, the semiconductor pattern, and the passivation layer.

In addition, the thin film transistor substrate according to the present invention comprises: a protective film covering a data pattern and formed with a plurality of contact holes; And a transparent electrode pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode respectively connected to the drain electrode, the gate pad lower electrode, and the data pad lower electrode through the contact hole.

In this case, the gate line constituting the gate pattern according to the present invention is characterized in that formed through the electroplating using the seed metal layer as an electrode.

The gate electrode and the gate pad lower electrode constituting the gate pattern according to the present invention are formed through a vacuum deposition method such as sputtering, and the surface thereof is formed flat.

A method of manufacturing a thin film transistor substrate according to the present invention includes forming a seed metal layer along an etched region of the substrate; Forming a gate pattern formed to correspond to the seed metal layer and including a gate line, a gate electrode connected to the gate line, and a gate pad lower electrode; Forming a semiconductor pattern formed on the gate insulating film covering the gate pattern and forming a channel; And forming a data pattern formed on the semiconductor pattern, the data pattern comprising a data line, a source electrode connected to the data line, a drain electrode facing the source electrode with a channel interposed therebetween, and a data pad lower electrode. do.

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Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.

First, the configuration and operation of a thin film transistor substrate according to an exemplary embodiment of the present invention will be described with reference to FIGS. 4 and 5. 4 is a plan view of a thin film transistor substrate according to the present invention, and FIG. 5 is a cross-sectional view of the thin film transistor substrate taken along lines II ′, II-II ′, and III-III ′ of FIG. 4.

4 and 5, the thin film transistor substrate 100 according to the present invention includes a substrate 101 etched to a predetermined depth and a seed formed along an etched portion of the substrate and serving as an electrode during electroplating. The gate insulating layer 130 via the metal layer 110, the gate pattern 120 formed along the seed metal layer 110, the gate insulating layer 130 covering the gate pattern 120, and the semiconductor pattern 135 forming the channel. Thin film transistors T and gates formed at intersections of the data pattern 140 and the gate line 122 constituting the gate pattern 120 and the data line 142 constituting the data pattern 140. The pixel electrode 160 and the gate line 121 connected to the thin film transistor T through a protective film 150 covering the thin film transistor T formed on the insulating layer 130, and a contact hole penetrating through the protective film 170. Storage capacitor formed in the overlapping portion of the pixel electrode 160 And 170.

The thin film transistor substrate according to the present invention further includes a gate pad 180 connected to the gate line 122 and a data pad 190 connected to the data line 142.

The substrate 101 may include a gate pattern having a predetermined depth through a photolithography process and an etching process using a mask, more specifically, the gate line 122, a gate electrode 124 connected to the gate line 122, and a lower gate pad. Patterned to have the form of a gate pattern 120 including an electrode 182.

That is, when the gate pattern 120 is formed as described above in the state in which the substrate 101 is etched in the form of a gate pattern, even if the line width of the gate pattern 120 is narrow, the thickness thereof can be made larger than in the related art. Therefore, the wiring resistance can be improved while reducing the wiring resistance.

The seed metal layer 110 is formed to correspond to the region etched in the form of the gate pattern 120 on the substrate 101, and to form the gate pattern 120 in the region etched in the form of the gate pattern 120. It serves as an electrode in the electrolytic plating performed.

In this case, the seed metal layer 110 is formed on the photoresist pattern used to etch the substrate 101 in the form of the gate pattern 120, the entire surface of the seed metal, and then the photoresist pattern of the remaining region except the etched region By removing the seed metal formed on the substrate through a lift-off process, it is formed only in the region etched in the form of the gate pattern 120.

The gate pattern 120 is formed only in the substrate region etched in the form of a gate pattern through electroplating using the seed metal layer 110. The gate pattern 120 is connected to the gate line 122 and the gate line 122. And a gate pad lower electrode 182 constituting the gate pad.

Here, the gate line 122 serves to transfer a gate signal supplied from a gate driver (not shown) connected to the gate pad to the gate electrode 124 constituting the thin film transistor T.

The data pattern 140 is formed on the gate insulating layer 130 covering the gate pattern 120 with the semiconductor pattern 135 for channel formation therebetween, and intersects the gate line 122 to form the pixel region 165. And a data line 142, a source electrode 144 constituting the thin film transistor T, and a drain electrode 146.

Here, the data line 142 is a source electrode 144 constituting the thin film transistor T by interlocking a data signal supplied from a data driver (not shown) connected to the data pad with on / off of the gate electrode 124. And transfer to the drain electrode 146.

The thin film transistor T serves to charge the pixel electrode 160 of the data line 142 to the pixel electrode 160 in response to the gate signal of the gate line 122. The thin film transistor T is connected to the gate line 122. And an electrode 124, a source electrode 144 connected to the data line 142, and a drain electrode 146 facing the source electrode 144 via a channel and connected to the pixel electrode 160. .

Here, the thin film transistor T overlaps with the gate electrode 124 with the gate insulating layer 130 interposed therebetween, and the active layer 137 and the ohmic contact forming a channel between the source electrode 144 and the drain electrode 146. The semiconductor pattern 135 further includes a layer 139.

The active layer 137 is formed to overlap the data pad lower electrode 192. In this case, an ohmic contact layer 139 for ohmic contact with the source electrode 144, the drain electrode 146, and the data pad lower electrode 192 is further formed on the active layer 137.

The passivation 150 covers the thin film transistor T formed on the gate insulating layer 130, and at the same time, the active layer 137 and the pixel region 165 forming the channel may be exposed to moisture or scratches that may occur during a subsequent process. protects against scratches.

Here, the passivation layer 150 may be formed of a gate insulating layer 130 by sputtering or PECVD using an inorganic insulating material such as silicon nitride, an organic organic compound such as acryl-based organic compound, benzocyclobutene (BCB), or perfluorocyclobutane (PFCB). Is deposited on the substrate.

In this case, the first to fourth contact holes 151, 152, 153 and 154 are formed in the passivation layer 150 through a photolithography process and an etching process using a mask. Here, the first contact hole 151 penetrates the passivation layer 150 to expose the drain electrode 146, and the second contact hole 152 penetrates the passivation layer 150 to expose the storage electrode 172. The third contact hole 153 penetrates the passivation layer 150 and the gate insulating layer 130 to expose the gate pad lower electrode 182, and the fourth contact hole 154 penetrates the passivation layer 150 to lower the data pad. The electrode 192 is exposed.

The pixel electrode 160 is formed in the pixel region 165 in a state of being connected to the drain electrode 146 of the thin film transistor T through the first contact hole 151 passing through the passivation layer 150. In this case, an electric field is formed between the pixel electrode 160 supplied with the pixel signal through the thin film transistor T and the common electrode (not shown) supplied with the reference voltage.

Therefore, the liquid crystal molecules filled between the substrates are rotated by dielectric anisotropy by the electric field formed between the pixel electrode 160 and the common electrode, and the light transmittance of the liquid crystal molecules passing through the pixel region 165 varies depending on the degree of rotation of the liquid crystal molecules. By changing, the gray scale is realized.

The storage capacitor 170 is configured such that the storage electrode 172 and the previous gate line 122 overlap each other with the gate insulating layer 130 and the passivation layer 150 interposed therebetween. The storage electrode 172 is electrically connected to the pixel electrode 160 through the second contact hole 152 formed in the passivation layer 150.

The storage capacitor 170 configured as described above serves to stably maintain the pixel signal charged in the pixel electrode 160 until the next pixel signal is charged.

The gate pad 180 is connected to a gate driver (not shown) to supply a gate signal to the gate line 122.

The gate pad 180 may have a third contact hole 153 and a third contact hole 153 penetrating the gate pad lower electrode 182, the gate insulating layer 130, and the passivation layer 150 extending from the gate line 122. The gate pad upper electrode 184 is connected to the gate pad lower electrode 182 through the.

In this case, the gate pad lower electrode 182 is formed by electroplating using the seed metal layer 110 formed along the etched region in the form of a gate pattern.

Therefore, even if the line width of the gate pad lower electrode 182 is made narrow, the thickness can be made larger than in the related art, thereby reducing the wiring resistance and improving the aperture ratio.

The data pad 190 is connected to a data driver (not shown) to supply a data signal to the data line 142.

The data pad 190 has a data pad lower electrode 192 extending from the data line 142, a fourth contact hole 154 and a fourth contact hole 154 passing through the passivation layer 150. The data pad upper electrode 194 is connected to the electrode 192.

Hereinafter, a method of manufacturing a thin film transistor substrate according to an exemplary embodiment of the present invention configured as described above with reference to the accompanying drawings will be described in detail.

First, a seed metal layer is formed on a region etched in the form of a gate pattern on a substrate according to the present invention.

As shown in FIGS. 6A and 6B, the seed metal layer 110 which performs an electrode role during electroplating is formed on the region 103 etched in the form of a gate pattern in the substrate 101 by using a first mask process. Form.

In more detail, the photoresist pattern PR for exposing the region on which the gate pattern is to be formed is exposed by performing a photolithography process using a mask after the entire surface of the photoresist is coated on the substrate. To form.

Thereafter, the region exposed by the photoresist pattern PR is etched using a predetermined nicking liquid, thereby forming the region 103 etched in the form of a gate pattern having a predetermined depth, as shown in FIG. 7B. .

Next, as shown in FIG. 7C, the seed metal material 110a for forming the seed metal layer on the photoresist pattern PR remaining on the substrate is deposited on the entire surface.

Thereafter, the seed metal material 110a formed in the remaining regions other than the photorest pattern PR and the etched region remaining on the substrate is removed by a lift-off process, as shown in FIG. In the region 103 etched in the form of a gate pattern, a seed metal layer 110 is formed to perform an electrode role when the gate pattern is formed through the electroplating method.

As described above, after forming the seed metal layer 110 in the region 103 etched in the form of a gate pattern, as shown in FIGS. 8A and 8B, the seed metal layer 110 formed on the substrate 101 is electroded. The gate pattern 120 is formed by using an electroplating method.

As shown in FIGS. 8A and 8B, the gate line 122 is formed along the seed metal layer by performing electroplating using the seed metal layer 110 formed on the region 103 etched in the form of a gate pattern on the substrate as an electrode. A gate pattern 120 including the gate electrode 124 and the gate pad lower electrode 182 connected to the gate line 122 is formed.

In more detail, after forming the seed metal layer 110 in the region 103 etched in the form of a gate pattern having a predetermined depth on the substrate, the substrate on which the seed metal layer 110 is formed is formed into a predetermined gate metal material. It is immersed in this melted electrolytic plating solution.

Thereafter, electrolytic plating is performed using the seed metal layer 110 as an electrode, thereby plating a gate metal material on the seed metal layer 110 to connect the gate line 122 and the gate electrode 124 connected to the gate line 122. And a gate pattern 120 including the gate pad lower electrode 182.

After forming the gate pattern through electroplating using the seed metal layer 110 as described above, as shown in FIGS. 9A and 9B, a semiconductor pattern and a data pattern forming a channel on the gate insulating layer covering the gate pattern. To form.

9A and 9B, the gate insulating layer 120 is formed on the substrate 101 on which the gate pattern 120 is formed, and then formed of an active layer 137 and an ohmic contact layer 139 for channel formation. A source electrode connected to the data line 142 and the data line 142 that are formed to intersect the semiconductor pattern 135 and the gate insulating layer 130 and intersect the gate line 122 to define the pixel region 165. The data pattern 140 including the drain electrode 146 facing the source electrode 144 is formed through the channel 144 and the channel.

In more detail, as illustrated in FIG. 10A, the gate insulating layer 130 is entirely deposited on the substrate 101 on which the gate pattern 120 is formed. The gate insulating layer 130 is formed of an inorganic insulating material such as silicon oxide (SiOx) or silicon nitride (SiNx).

Thereafter, as illustrated in FIG. 10B, the active layer 137, the ohmic contact layer 139, and the data metal layer 140a are sequentially deposited on the gate insulating layer 130 by a deposition method such as PECVD or sputtering.

Here, the active layer 137 is composed of an amorphous silicon layer, and the ohmic contact layer 139 is composed of an n + amorphous silicon layer.

Thereafter, as illustrated in FIG. 10C, a photoresist pattern PR having a predetermined shape is formed on the data metal layer 140a through a photolithography process using a second mask. At this time. By using a diffraction exposure mask having a diffraction exposure portion in the channel region of the thin film transistor T as the second mask, the photoresist pattern formed in the channel region is formed to have a lower height than other regions.

After forming the photoresist pattern PR on the data metal layer 140a as described above, as shown in FIG. 10D, the wet etching of the data metal layer 140a exposed by the photoresist pattern PR is performed. etching).

Subsequently, by removing the photoresist pattern PR covering the channel region through an ashing process using an oxygen (O ₂ ) plasma, as illustrated in FIG. 10E, the data metal layer 140a formed in the channel region is removed. Expose

Next, as shown in FIG. 10F, the exposed data metal layer 140a is removed by dry etching, thereby allowing the data line 142, the source electrode 144 connected to the data line 142, and the like. A data pattern 140 including a drain electrode 146 facing the source electrode 144, a data pad lower electrode 192, and a storage electrode 172 is formed through the channel region.

In this case, as the source electrode 144 and the drain electrode 146 constituting the data pattern 140 are separated, the ohmic contact layer 139 formed on the channel region is exposed to the outside.

Thereafter, the exposed ohmic contact layer 139 is removed by dry etching, and as shown in FIG. 10G, a channel between the source electrode 144 and the drain electrode 146 of the thin film transistor T is removed. Open the active layer 137 to form a.

Next, as shown in FIG. 10H, the semiconductor pattern 135 and the data pattern 140 for channel formation are finally formed by finally removing the photoresist pattern PR remaining on the data pattern 140. do.

After the semiconductor pattern 135 and the data pattern 140 are formed as described above, as shown in FIGS. 11A and 11B, the passivation layer 150 covering the thin film transistor T formed on the substrate 101 is formed. Form.

In more detail, the passivation layer 150 is entirely formed on the gate insulating layer 130 on which the data pattern 140 is formed by a deposition method such as PECVD.

Subsequently, the protective film 150 in which the first to fourth contact holes 151, 152, 153 and 154 are formed is finally formed by performing a photolithography process and an etching process using a mask.

Here, the first contact hole 151 penetrates the passivation layer 150 to expose the drain electrode 146, and the second contact hole 152 penetrates the passivation layer 150 to expose the storage electrode 172. The third contact hole 153 penetrates the passivation layer 150 and the gate insulating layer 130 to expose the gate pad lower electrode 182, and the fourth contact hole 154 penetrates the passivation layer 150 to lower the data pad. The electrode 192 is exposed.

After the protective film 170 having the plurality of contact holes is formed as described above, as shown in FIGS. 12A and 12B, a transparent conductive pattern made of a transparent conductive material is formed on the protective film.

As shown in FIGS. 12A and 12B, the entire surface of the transparent conductive material is formed on the passivation layer, followed by a photolithography process and an etching process using a mask, thereby forming the pixel electrode 160 and the gate pad upper electrode 184 on the passivation layer. And a transparent conductive pattern including the data pad upper electrode 194.

In more detail, the transparent conductive material (ITO) is deposited on the entire surface of the protective film 170 having the plurality of contact holes by sputtering or the like.

In this case, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) may be used as the transparent electrode material.

Subsequently, the photolithography and etching processes for the transparent conductive material must be performed using a mask to include the pixel electrode 160, the gate pad upper electrode 184, and the data pad upper electrode 194 on the passivation layer 150. A transparent conductive pattern is formed.

Here, the pixel electrode 160 is electrically connected to the drain electrode 146 of the thin film transistor T through the first contact hole 151 formed in the passivation layer 150 and at the same time through the second contact hole 152. It is electrically connected to the storage electrode 172.

In addition, the gate pad upper electrode 184 is electrically connected to the gate pad lower electrode 182 through the third contact hole 153 formed in the passivation layer 150, and the data pad upper electrode 194 is the fourth contact hole. The data pad is electrically connected to the lower electrode 192 through 175.

Hereinafter, a configuration and an operation of a thin film transistor substrate according to another exemplary embodiment of the present invention will be described with reference to FIGS. 13 and 14. Here, the description of the contents duplicated with the contents described in the embodiment of the present invention will be omitted and only the different parts will be described in detail.

The thin film transistor substrate 200 according to another exemplary embodiment of the present invention has a planar surface morphology of the gate electrode 224 formed by electroplating, as shown in FIGS. 13 and 14. After the seed metal layer 210 is formed in the region of the substrate 201 etched in the form of the gate line 222 through the method as described above, only the gate line 222 constituting the gate pattern 220 is formed as the seed metal layer ( 210 is formed by electroplating.

Thereafter, the gate electrode 224 and the gate pad lower electrode 282 constituting the gate pattern 220 are connected to the gate line 222 through a deposition method such as sputtering to form a gate electrode having a flat surface structure ( 224 and the gate pad lower electrode 282 are formed.

As described above, the gate electrode 224 and the gate pad lower electrode 282 having the flat surface structure are formed by the deposition method such as sputtering, thereby improving the interface characteristics between the gate insulating film 130 and the semiconductor pattern 135. As a result, the performance of the thin film transistor T may be improved.

Hereinafter, a method of manufacturing a thin film transistor substrate according to another exemplary embodiment of the present invention will be described in detail.

First, a seed metal layer is formed in a region etched in the form of a gate line on a substrate according to the present invention.

As shown in FIGS. 15A and 15B, a seed metal layer 210 which performs an electrode role during electroplating is formed on a region 203 etched in the form of a gate line in the substrate 201 using a first mask process. Form.

In more detail, a photolithography process using a mask is performed after the entire surface of the photoresist is applied onto the substrate, thereby exposing a substrate region on which the gate line 222 is to be formed, as shown in FIG. 16A. The resist pattern PR is formed.

Subsequently, the substrate region exposed by the photoresist pattern PR is etched using a predetermined nicking liquid, thereby etching the region 203 in the form of a gate line 222 having a predetermined depth, as shown in FIG. 16B. ).

Next, as shown in FIG. 16C, the seed metal material 210a for forming the seed metal layer on the photoresist pattern PR remaining on the substrate 201 is deposited on the entire surface.

Subsequently, the seed metal material 210a formed in the remaining regions other than the etched region and the photorest pattern PR remaining on the substrate is removed by a lift-off process, as shown in FIG. 16D, thereby providing the substrate 201. The seed metal layer 210 is formed in the region 203 etched in the form of the gate line 222 to serve as an electrode when the gate line 222 is formed through the electroplating method.

After the seed metal layer 210 is formed in the region 203 etched in the form of the gate line 222 as described above, as shown in FIGS. 17A and 17B, the seed metal layer 210 formed on the substrate 201 is formed. ), A gate pattern including a gate line 222, a gate electrode 224 connected to the gate line 222, and a gate pad lower electrode 282.

In more detail, after forming the seed metal layer 210 in the region 203 etched in the form of a gate line having a predetermined depth in the substrate 201, the substrate on which the seed metal layer 210 is formed is predetermined. Is immersed in the electrolytic plating solution in which the gate metal material is melted.

Thereafter, electroplating using the seed metal layer 210 as an electrode is performed to plate the gate metal material on the seed metal layer 210, thereby growing to a predetermined height along the seed metal layer 210 as shown in FIG. 18. The gate line 222 is formed.

After forming the gate line 222 through electroplating using the seed metal layer 210 as described above, as shown in FIG. 18B, the gate metal material 220a such as sputtering is entirely formed on the substrate 201. do.

Thereafter, as shown in FIG. 18C, the photoresist pattern PR for exposing the gate metal material 220a is formed through a photolithography process using a mask.

Next, by performing an etching process on the gate metal 220a exposed by the photoresist pattern PR using a etch solution, as shown in FIG. 18D, the gate line 222 formed along the seed metal layer 210. The gate pattern 220 including the gate electrode 224 and the gate pad lower electrode 282 connected to the () is finally formed.

After the gate pattern 220 is formed as described above, as shown in FIGS. 19A and 19B. The semiconductor pattern 235 and the data pattern 240 forming a channel are formed on the gate insulating layer 230 covering the gate pattern 220.

As shown in FIGS. 19A and 19B, the gate insulating layer 230 is formed on the substrate 201 on which the gate pattern 220 is formed, and then the active layer 237 and the ohmic contact layer 239 for channel formation are formed. A source electrode connected to the data line 242 and the data line 242 formed of the semiconductor pattern 235 and the gate insulating film 230 intersecting the gate line 222 to define the pixel region 265. A data pattern 240 including the source electrode 244 and the drain electrode 246 facing the source electrode 244 is formed through the channel 244 and the channel.

After the semiconductor pattern 235 and the data pattern 240 are formed as described above, as shown in FIGS. 20A and 20B, the passivation layer 250 covering the thin film transistor T formed on the substrate 201 is formed. Form.

In more detail, the passivation layer 250 is entirely formed on the gate insulating layer 230 on which the data pattern 240 is formed through a deposition method such as PECVD.

Subsequently, the protective film 250 having the first to fourth contact holes 251, 252, 253 and 254 formed thereon is finally formed by performing a photolithography process and an etching process using a mask.

Here, the first contact hole 251 penetrates the passivation layer 250 to expose the drain electrode 246, and the second contact hole 252 penetrates the passivation layer 250 to expose the storage electrode 272. The third contact hole 253 penetrates the passivation layer 250 and the gate insulating layer 230 to expose the gate pad lower electrode 282, and the fourth contact hole 254 penetrates the passivation layer 250 to lower the data pad. The electrode 292 is exposed.

After forming the passivation layer 150 having a plurality of contact holes as described above, as shown in FIGS. 20A and 20B, a transparent conductive pattern made of a transparent conductive material is formed on the passivation layer 250.

As shown in FIGS. 21A and 21B, the entire surface of the transparent conductive material is formed on the passivation layer 150, and then a photolithography process and an etching process using a mask are performed, thereby forming the pixel electrode 260 and the gate pad upper electrode on the passivation layer. A transparent conductive pattern including a 284 and a data pad upper electrode 294 is formed.

In more detail, the transparent conductive material (ITO) is deposited on the entire surface of the passivation layer 250 on which the plurality of contact holes are formed through a deposition method such as sputtering.

In this case, indium tin oxide (ITO), tin oxide (TO), or indium zinc oxide (IZO) may be used as the transparent electrode material.

Thereafter, a photolithography process and an etching process for the transparent conductive material are performed by using a mask to include the pixel electrode 260, the gate pad upper electrode 284, and the data pad upper electrode 294 on the passivation layer 550. A transparent conductive pattern is formed.

Here, the pixel electrode 250 is electrically connected to the drain electrode 246 of the thin film transistor T through the first contact hole 251 formed in the passivation layer 250 and at the same time through the second contact hole 252. It is electrically connected to the storage electrode 271.

In addition, the gate pad upper electrode 284 is electrically connected to the gate pad lower electrode 282 through the third contact hole 253 formed in the passivation layer 250, and the data pad upper electrode 294 is connected to the fourth contact hole. An electrical connection is made to the data pad lower electrode 292 through 254.

As described above, the present invention has the effect of reducing the gate wiring resistance by forming a gate pattern on a substrate etched to a predetermined depth.

In addition, the present invention has the effect that the aperture ratio can be improved by forming a gate pattern on the substrate etched to a predetermined depth to reduce the line width.

It will be apparent to those skilled in the art that various modifications and variations can be made in the present invention without departing from the spirit or scope of the invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification, but should be defined by the claims.

Claims (22)

In the thin film transistor substrate constituting the liquid crystal display device, A substrate etched to a predetermined depth; A seed metal layer formed along the etch region of the substrate; A gate pattern including a gate line formed on the substrate, a gate electrode connected to the gate line, and a gate pad lower electrode; A semiconductor pattern formed on the gate insulating layer covering the gate pattern and forming a channel; And a data pattern formed on the semiconductor pattern and including a data line, a source electrode connected to the data line, a drain electrode facing the source electrode with a channel interposed therebetween, and a data pad lower electrode. The gate line is formed on a seed metal layer formed along the etch region, the gate electrode and the gate pad lower electrode are formed through a deposition method, and the gate line is formed through electrolytic plating using the seed metal layer as an electrode. A thin film transistor substrate, characterized in that. The method of claim 1, The gate line; And And a storage capacitor comprising a storage electrode formed to overlap the gate line through the gate insulating layer and the passivation layer. The method of claim 1, A passivation layer covering the data pattern and formed with a plurality of contact holes; And And a transparent electrode pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode connected to the drain electrode, the gate pad lower electrode, and the data pad lower electrode, respectively, through the contact hole. Board. delete delete delete delete delete The method of claim 1, The gate electrode and the gate pad lower electrode constituting the gate pattern are formed by a vacuum deposition method such as sputtering. The method of claim 9, The thin film transistor substrate of claim 1, wherein a surface of the gate electrode and the gate pad lower electrode is flat. In the manufacturing method of the thin film transistor substrate which comprises a liquid crystal display device, Forming a seed metal layer along the etch region of the substrate; Forming a gate pattern including a gate line formed on the substrate, a gate electrode connected to the gate line, and a gate pad lower electrode; Forming a semiconductor pattern formed on a gate insulating layer covering the gate pattern and forming a channel; And forming a data pattern formed on the semiconductor pattern, the data pattern comprising a data line, a source electrode connected to the data line, a drain electrode facing the source electrode with a channel interposed therebetween, and a data pad lower electrode. The gate line of the gate pattern is formed on a seed metal layer formed along the etching region, the gate electrode and the gate pad lower electrode are formed by a deposition method, and the gate line is formed by using the seed metal layer as an electrode. Method of manufacturing a thin film transistor substrate, characterized in that formed through plating. The method of claim 11, The gate line; And And forming a storage capacitor comprising a storage electrode formed to overlap with the gate line through the gate insulating layer and the passivation layer. The method of claim 11, A passivation layer covering the data pattern and formed with a plurality of contact holes; And And forming a transparent electrode pattern including a pixel electrode, a gate pad upper electrode, and a data pad upper electrode respectively connected to the drain electrode, the gate pad lower electrode, and the data pad lower electrode through the contact hole. A method of manufacturing a thin film transistor substrate. The method of claim 11, Forming the seed metal layer, Forming a photoresist over the substrate; Forming a photoresist pattern exposing the substrate through a predetermined mask process; Nicking the substrate exposed by the photoresist pattern to form a region etched in the form of the gate pattern; Forming a seed metal on the entire surface of the substrate on which the photoresist pattern is formed; And Forming a seed metal layer in the etched region by removing the seed metal formed on the photoresist pattern and the substrate through a lift off process; Method of manufacturing a thin film transistor substrate comprising a. delete delete delete delete The method of claim 11, Forming the seed metal layer, Forming a photoresist over the substrate; Forming a photoresist pattern exposing the substrate through a predetermined mask process; Nicking the substrate exposed by the photoresist pattern to form an etched region in the form of the gate line; Forming a seed metal on the entire surface of the substrate on which the photoresist pattern is formed; And Forming a seed metal layer in the etched region by removing a seed metal formed in addition to the photoresist pattern and the etched region through a lift off process; Method of manufacturing a thin film transistor substrate comprising a. delete The method of claim 11, The gate electrode and the gate pad lower electrode constituting the gate pattern are formed by a vacuum deposition method such as sputtering. 22. The method of claim 21, And the surface of the gate electrode and the gate pad lower electrode are flat.

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