KR20020005152A - Method of patterning Transpatent Conductive Film - Google Patents
Method of patterning Transpatent Conductive Film Download PDFInfo
- Publication number
- KR20020005152A KR20020005152A KR1020000039141A KR20000039141A KR20020005152A KR 20020005152 A KR20020005152 A KR 20020005152A KR 1020000039141 A KR1020000039141 A KR 1020000039141A KR 20000039141 A KR20000039141 A KR 20000039141A KR 20020005152 A KR20020005152 A KR 20020005152A
- Authority
- KR
- South Korea
- Prior art keywords
- sacrificial layer
- pattern
- transparent substrate
- layer
- film
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Liquid Crystal (AREA)
Abstract
Description
본 발명은 투명도전막 패터닝 방법에 관한 것으로서, 특히 투명도전막의 미세 패턴(Pattern)화 할 수 있도록 한 투명도전막 패터닝 방법에 관한 것이다.The present invention relates to a transparent conductive film patterning method, and more particularly, to a transparent conductive film patterning method capable of forming a fine pattern of the transparent conductive film.
액티브 매트릭스(Active Matrix) 구동방식의 액정표시장치는 스위칭 소자로서 박막트랜지스터(Thin Film Transistor : 이하 "TFT"라 함)를 이용하여 자연스러운 동화상을 표시하고 있다. 이러한 액정표시장치는 브라운관에 비하여 소형화가 가능하여 퍼스널 컴퓨터(Personal Computer)와 노트북 컴퓨터(Note Book Computer)는 물론, 복사기 등의 사무자동화기기, 휴대전화기나 호출기 등의 휴대기기까지 광범위하게 이용되고 있다.An active matrix liquid crystal display device displays a natural moving image using a thin film transistor (hereinafter, referred to as TFT) as a switching element. Such liquid crystal display devices can be miniaturized compared to CRTs, and are widely used in personal computers and notebook computers, as well as office automation devices such as photocopiers, mobile devices such as cell phones and pagers. .
액티브 매트릭스 타입의 액정표시장치는 화소들이 게이트라인들과 데이터라인들의 교차부들 각각에 배열되어진 화소매트릭스(Picture Element Matrix 또는 Pixel Matrix)에 텔레비젼 신호와 같은 비디오신호에 해당하는 화상을 표시하게 된다. 화소들 각각은 데이터라인으로 부터의 데이터신호의 전압레벨에 따라 투고 광량을 조절하는 액정셀을 포함한다. TFT는 게이트라인과 데이터라인들의 교차부에 설치되어 게이트라인으로 부터의 스캔신호(게이트 펄스)에 응답하여 액정셀 쪽으로 전송될 데이터신호를 절환하게 된다.In an active matrix type liquid crystal display, an image corresponding to a video signal such as a television signal is displayed on a pixel matrix (Picture Element Matrix or Pixel Matrix) in which pixels are arranged at intersections of gate lines and data lines. Each of the pixels includes a liquid crystal cell that adjusts the amount of light emitted according to the voltage level of the data signal from the data line. The TFT is provided at the intersection of the gate line and the data lines to switch the data signal to be transmitted toward the liquid crystal cell in response to the scan signal (gate pulse) from the gate line.
일반적으로, 액정표시소자는 도 1과 같이 데이터라인(22)과 게이트라인(24)의 교차부에 TFT(30)가 형성되며, 데이터라인(22)과 게이트라인(24)사이의 화소영역에 화소전극들(20)이 매트릭스 형태로 배치된다. TFT(30)는 도 1과 같이 투명기판(2) 상에 형성된다. 이 TFT(30)는 게이트라인(24)에 접속된 게이트전극(4), 데이터라인(22)에 접속된 드레인전극(14) 및 화소전극(20)에 접속된 소오스전극(12)을 포함한다. 게이트전극(4)이 패터닝된 투명기판(2) 상에는 SiNx 등의 무기 유전체로 된 게이트절연막(6)이 전면 증착된다. 이 게이트절연막(6) 위에는 비정질 실리콘(amorphous-Si : 이하 "a-Si"이라 함)으로 된 반도체층(8)과 n+ 이온이 도핑된 a-Si으로 된 오믹접촉층(10)이 게이트 전극(4) 상의 게이트절연막(6)을 덮게끔 순차적으로 형성된다. 오믹접촉층(10) 위에는 금속으로 된 드레인전극(14)과 소오스전극이 형성된다. 드레인전극(14)과 소오스전극(12)은 미리 설정된 채널폭만큼 이격되게 패터닝된다. 이어서, 드레인전극(14)과 소오스전극(12) 사이에 형성된 채널을 따라 오믹접촉층(10)이 에칭되어 반도체층(8)을 노출시키게 된다. 그리고 SiNx, SiOx 등으로 된 보호막(도시하지 않음)이 투명기판(2)상에 전면 증착되어 TFT(30)를 덮게 된다. 소오스전극(12) 상의 보호막(도시하지 않음) 콘택홀(18)이 형성되게끔 에칭에 의해 제거된다. 이 콘택홀(18)을 통하여 소오스전극(12)에 접속되게끔 인듐-틴-옥사이드(Indium-Tin-Oxide)로 된 화소전극(20) 증착된다.In general, in the liquid crystal display device, as illustrated in FIG. 1, the TFT 30 is formed at the intersection of the data line 22 and the gate line 24, and is formed in the pixel region between the data line 22 and the gate line 24. The pixel electrodes 20 are arranged in a matrix form. The TFT 30 is formed on the transparent substrate 2 as shown in FIG. The TFT 30 includes a gate electrode 4 connected to the gate line 24, a drain electrode 14 connected to the data line 22, and a source electrode 12 connected to the pixel electrode 20. . On the transparent substrate 2 on which the gate electrode 4 is patterned, a gate insulating film 6 made of an inorganic dielectric such as SiNx is deposited on the entire surface. On this gate insulating film 6, a semiconductor layer 8 made of amorphous silicon (hereinafter referred to as "a-Si") and an ohmic contact layer 10 made of a-Si doped with n + ions are provided as gate electrodes. It is formed sequentially so as to cover the gate insulating film 6 on (4). A drain electrode 14 and a source electrode made of metal are formed on the ohmic contact layer 10. The drain electrode 14 and the source electrode 12 are patterned to be spaced apart by a predetermined channel width. Subsequently, the ohmic contact layer 10 is etched along the channel formed between the drain electrode 14 and the source electrode 12 to expose the semiconductor layer 8. A protective film (not shown) made of SiNx, SiOx, or the like is deposited on the transparent substrate 2 to cover the TFT 30. The protective film (not shown) contact hole 18 on the source electrode 12 is removed by etching so as to form. The pixel electrode 20 made of indium tin oxide is deposited to be connected to the source electrode 12 through the contact hole 18.
최근, 액티브 매트릭스 타입의 액정표시장치는 개구율을 높이기 위하여 도 1과 같이 게이트라인 또는 데이터라인과 같은 신호배선(도시하지 않음)에 투명전극으로 된 화소전극(20)을 중첩시키는 추세에 있다. 이 경우, 신호배선(도시하지 않음)이 형성된 투명기판(2) 위에는 신호배선(도시하지 않음)과 화소전극(20) 사이의 절연과 기생캐패시턴스를 최소화하기 위하여 유전상수가 낮은 유기절연막(16)이 절연 코팅된다. 이와 같이 화소전극(20)이 신호배선(도시하지 않음)과 중첩되는 액정표시소자는 화소전극(20)과 신호배선(도시하지 않음)이 중첩되지 않고 소정 간격(대략 5~10μm)만큼 이격된 액정표시소자에 비하여 신호배선(도시하지 않음)과 화소전극(20)의 중첩영역만큼 개구율이 증대된다.Recently, in order to increase the aperture ratio, an active matrix type liquid crystal display device has a trend of superposing a pixel electrode 20 made of a transparent electrode on a signal line (not shown) such as a gate line or a data line as shown in FIG. 1. In this case, on the transparent substrate 2 on which signal wiring (not shown) is formed, an organic insulating layer 16 having a low dielectric constant to minimize insulation and parasitic capacitance between the signal wiring (not shown) and the pixel electrode 20. This is coated with insulation. As described above, in the liquid crystal display device in which the pixel electrode 20 overlaps with the signal wiring (not shown), the pixel electrode 20 and the signal wiring (not shown) are spaced apart by a predetermined interval (about 5 to 10 μm) without overlapping. Compared to the liquid crystal display device, the aperture ratio is increased by an overlapping area between the signal wiring (not shown) and the pixel electrode 20.
화소전극(20)의 재료로는 통상 투명 전도성 물질인 인듐-틴-옥사이드로 선택된다. 이 ITO막이 유기절연막(16) 상에 전면 증착된후, 신호배선(도시하지 않음)과 중첩되게끔 패터닝된다. 그러나 ITO막 패터닝시 ITO막의 외곽부는 에천트에 의해 에칭된후 휘어지거나 손상되는 경우가 흔히 발생한다. 이와 같이 유기절연막(16) 상에 형성되는 ITO막의 외곽부가 손상되거나 휘게되면 화소전극(20)과 신호배선의 중첩부의 폭이 좁아지기 때문에 중첩부에서 빚이 새는 현상이 나타나게 된다. 이렇게 ITO막의 패턴불량이 발생되는 원인은 ITO막이 유기절연막(16)과의 계면 접합 특성이 나쁘다는 특성에도 기인하지만 특히, 고농도의 강산이 포함된 에천트에 의해 에칭되고, 에칭속도가 늦다는 것에 기인한다.As the material of the pixel electrode 20, indium tin oxide, which is usually a transparent conductive material, is selected. This ITO film is deposited on the organic insulating film 16 in its entirety and then patterned to overlap with signal wiring (not shown). However, during ITO film patterning, the outer portion of the ITO film is often bent or damaged after being etched by an etchant. As such, when the outer portion of the ITO film formed on the organic insulating layer 16 is damaged or bent, the width of the overlapping portion of the pixel electrode 20 and the signal wiring becomes narrow, resulting in a phenomenon of leaking from the overlapping portion. The reason why the pattern defect of the ITO film is generated is due to the property that the interface bonding property of the ITO film is poor with the organic insulating film 16, but is particularly etched by an etchant containing a high concentration of strong acid, and the etching rate is slow. Is caused.
상세히 하면, 종래의 ITO전극은 도 3a 및 도 3b에 도시된 제조 방법과 같이형성된다. 도 3a와 같이 투명기판(32) 상에 ITO막(36)을 증착하고, 그 위에 포토레지스트(Photo resiste : 이하 "PR" 이라 함)막(도시하지 않음)을 코팅한 후, 포토 마스크(Photo Mask)(도시하지 않음)를 씌운 다음, 습식 에칭(Wet etching)을 사용하여 ITO막(36)을 패터닝하면 도 3b와 같은 ITO(38)막이 패턴된다. 이 와 같은 패턴 방법은 직접 ITO막(36)을 에칭하므로 낮은 에칭 비율(Etching rate)과 패터닝된 ITO막(36)과 포토패터닝된 포토레지스트막(40) 사이에 들뜸이나 ITO막(38)과 투명기판(32) 사이의 들뜸을 유발 시키며, 이로 인해 ITO막(38)을 패턴하는데 있어서 많은 패턴불량이 발생한다.In detail, the conventional ITO electrode is formed as in the manufacturing method shown in Figs. 3A and 3B. As shown in FIG. 3A, an ITO film 36 is deposited on the transparent substrate 32, and a photoresist film (not shown) (not shown) is coated thereon, followed by a photo mask (Photo). After the mask (not shown) is applied, the ITO film 36 is patterned by wet etching to pattern the ITO 38 film as shown in FIG. 3B. Such a pattern method directly etches the ITO film 36, so that it may be lifted between the patterned ITO film 36 and the photopatterned photoresist film 40, and the ITO film 38 may have a low etching rate. It causes the floating between the transparent substrate 32, which causes a large number of pattern defects in patterning the ITO film 38.
이와 같은 ITO막(38)의 패턴불량을 줄이기 위하여, 유기절연막(16)과 ITO막(38)사이의 접착력을 강화하기 위한 유기절연막(16) 상에 HNO3, H2SO4 등의 산을 이용하여 산화막을 형성하는 방법이 있다. 다른 방법으로는 플라즈마 증착을 이용하여 수소(H)를 유기절연막(16)의 표면에 성막하거나 산소(O)를 이온도핑하는 방법 등이 있다. 이렇게 유기 절연막(16)을 표면처리하는 경우에도 에천트가 담긴 챔버 내에 투명기판(2)을 침전 시키는 디핑(Deeping) 방식으로 ITO막을 에칭하게 되면 유기절연막(16)과 ITO막 사이의 계면에 에천트가 침투되면서 전술한 바와 같은 ITO막의 패턴불량이 발생된다. 이 경우에도 ITO막을 에칭하기 위한 에천트는 고농도의 강산을 포함하며, 장시간의 에칭이 진행된다. 실제로, ITO막을 에칭하기 위한 에천트는 C2H2O4 대 디이오나이즈드워터(De-Ionized Water : 이하 "야"라 함)의 비가 1: 10 이하로 산의 농도가 매우 높다. 이와 같은 고농도의 에천트를 이용하여 ITO막을 에칭하는데 소요되는 시간은 대략 1000초 이상이 소요된다.In order to reduce the pattern defect of the ITO film 38, an oxide film is formed by using an acid such as HNO 3, H 2 SO 4, or the like on the organic insulating film 16 to enhance the adhesion between the organic insulating film 16 and the ITO film 38. There is a way to form. Other methods include a method of depositing hydrogen (H) on the surface of the organic insulating layer 16 or ion doping oxygen (O) using plasma deposition. Even when the organic insulating film 16 is surface-treated, when the ITO film is etched by a deeping method of depositing the transparent substrate 2 in the chamber containing the etchant, the interface between the organic insulating film 16 and the ITO film is etched. As the cloth penetrates, a pattern defect of the ITO film as described above occurs. Even in this case, the etchant for etching the ITO film contains a high concentration of strong acid, and the etching is performed for a long time. In fact, the etchant for etching the ITO film has a very high acid concentration with a ratio of C2H2O4 to De-Ionized Water (hereinafter referred to as "ya") of 1:10 or less. The time required for etching the ITO film using such a high concentration of etchant takes approximately 1000 seconds or more.
한편, ITO막은 액정표시장치 이외에도 많은 디스플레이 소자, 잉크젯 헤드등에도 이용되고 있으며, 액티브 매트릭스 액정표시장치와 유사한 구조를 가지는 X선 검출소자의 화소전극으로도 이용된다. 이와 같이 ITO가 이용되는 소자 또는 기기들에 있어서 ITO의 에칭특성이 나쁘기 때문에 ITO가 적용된 투명전극 또는 화소전극 등의 패턴 불량이 쉽게 발생된다. 그 결과 ITO막이 미세 패턴화 될 수 있는 방안이 요구 되고 있다.On the other hand, the ITO film is used not only in the liquid crystal display device but also in many display elements, inkjet heads, etc., and is also used as the pixel electrode of the X-ray detection element having a structure similar to the active matrix liquid crystal display device. As described above, since the etching characteristics of ITO are poor in devices or devices using ITO, pattern defects such as transparent electrodes or pixel electrodes to which ITO is applied are easily generated. As a result, there is a demand for a method to fine pattern the ITO film.
따라서, 본 발명의 목적은 미세한 패턴을 형성하기 위한 투명도전막의 패터닝 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method of patterning a transparent conductive film for forming a fine pattern.
도 1은 액정 표시소자를 나타내는 평면도.1 is a plan view showing a liquid crystal display device.
도 2은 도 1에서 선 " A-A'"를 따라 절취하여 나타내는 단면도.2 is a cross-sectional view taken along the line "A-A '" in FIG.
도 3a 및 도 3b는 도 2에 도시된 종래의 투명도전막의 제조 공정도.3a and 3b is a manufacturing process diagram of the conventional transparent conductive film shown in FIG.
도 4a 내지 도 4f는 본 발명의 실시 예에 따른 투명도전막의 제조 공정도.4A to 4F are manufacturing process diagrams of a transparent conductive film according to an embodiment of the present invention.
도 5는 IPS 모드 방식의 액정표시장치의 단면도.5 is a cross-sectional view of an IPS mode type liquid crystal display device.
< 도면의 주요 부분에 대한 부호의 설명 ><Description of Symbols for Main Parts of Drawings>
2, 32 : 투명기판 4, 34 : 게이트전극2, 32: transparent substrate 4, 34: gate electrode
6 : 게이트절연막 8 : 반도체층6: gate insulating film 8: semiconductor layer
10 : 오믹접촉층 12 : 소오스전극10: ohmic contact layer 12: source electrode
14 : 드레인전극 16 : 유기절연막14 drain electrode 16 organic insulating film
18 : 콘택홀 20 : 화소전극18 contact hole 20 pixel electrode
22 : 데이터라인 24 : 게이트라인22: data line 24: gate line
30 : TFT 36,38,38-a,38-b : ITO30: TFT 36,38,38-a, 38-b: ITO
40,42,42-a : 포토레지스트 44,46 : 희생층40, 42, 42-a: photoresist 44, 46: sacrificial layer
50 : 공통전극 51 : 화소전극50: common electrode 51: pixel electrode
상기 목적을 달성하기 위하여, 본 발명에 따른 투명도전막 패터닝 방법은 투명기판 상에 희생층을 전면 형성하는 단계와, 상기 희생층을 패터닝하는 단계와, 희생층이 패턴되고 나서 그 위에 상기 투명도전막을 전면 증착한 후, 희생층을 에칭하여 희생층 상에 증착된 투명도전막은 제거하고 투명기판 상의 투명도전막만을 패터닝하는 단계를 포함한다.In order to achieve the above object, the transparent conductive film patterning method according to the present invention comprises the steps of forming a sacrificial layer on the transparent substrate, patterning the sacrificial layer, and after the sacrificial layer is patterned on the transparent conductive film After depositing the entire surface, etching the sacrificial layer to remove the transparent conductive film deposited on the sacrificial layer and patterning only the transparent conductive film on the transparent substrate.
본 발명은 액정에 전압을 인가하기 위한 화소전극 및 공통전극이 하판의 배면에 형성되는 인 플랜 스위칭모드의 액정표시장치의 제조방법에 있어서, 상기 화소전극 및 공통전극을 패터닝하는 방법은 상기 하판의 배면에 금속재료 및 수지재료로 구성된 희생층을 형성하는 단계와, 상기 희생층상에 포토레지스트를 도포한 다음 포토 마스크를 이용하여 패터닝하는 단계와, 상기 희생층패턴 상과 상기 투명기판 상에 인듐-틴-옥사이드막을 전면증착하는 단계와, 상기 희생층패턴을 에칭하여 상기 희생층패턴 상의 증착된 상기 인듐-틴-옥사이드막을 제거하여 상기 하판의배면에 인듐-틴-옥사이드막을 패터닝하는 단계를 포함한다.The present invention provides a method of manufacturing a liquid crystal display device in an in-plan switching mode in which a pixel electrode and a common electrode for applying a voltage to a liquid crystal are formed on a rear surface of a lower plate. Forming a sacrificial layer made of a metal material and a resin material on the back surface, applying a photoresist on the sacrificial layer, and then patterning the photoresist using a photo mask; and forming an indium-on the sacrificial layer pattern and the transparent substrate. Epitaxially depositing a tin oxide layer, and etching the sacrificial layer pattern to remove the indium tin oxide layer deposited on the sacrificial layer pattern, thereby patterning an indium tin oxide layer on the bottom surface of the lower plate. .
상기 목적 외에 본 발명의 다른 목적 및 특징들은 첨부도면을 참조한 실시예에 대한 설명을 통하여 명백하게 드러나게 될 것이다.Other objects and features of the present invention in addition to the above objects will become apparent from the description of the embodiments with reference to the accompanying drawings.
이하, 도 4a 내지 도 4f를 참조하여 본 발명의 바람직한 실시예에 대하여 설명하기로 한다.Hereinafter, exemplary embodiments of the present invention will be described with reference to FIGS. 4A to 4F.
도 4a를 참조하면, 본 발명에 따른 ITO막 패터닝 방법은 먼저 투명기판(32) 상에 스퍼터링(Sputtering)방법을 사용하여 희생층(44)을 충분히 두껍게 전면 형성한다. 상기에서 투명기판(32)으로 유리,석영 또는 투명한 플라스틱 등이 사용될 수 도 있으며, 희생층(44) 구성재료로는 금속(Al 등) 또는 수지재료 중 어느 하나를 사용할 수 있다. 이어서 도 4b와 같이 희생층(44) 상에는 포토 레지스트막(42)을 전면 도포한다.Referring to FIG. 4A, the ITO film patterning method according to the present invention first forms the sacrificial layer 44 sufficiently thick on the transparent substrate 32 by using a sputtering method. As the transparent substrate 32, glass, quartz, or transparent plastics may be used, and as the constituent material of the sacrificial layer 44, any one of metal (Al, etc.) or resin material may be used. Subsequently, the photoresist film 42 is entirely coated on the sacrificial layer 44 as shown in FIG. 4B.
도 4c를 참조하면, 도 4b에서 포토 마스크(도시하지 않음)는 도포된 포토 레지스트막(42) 상에 덮여진다. 그리고 포토리쏘그래피 방법에 의해 포토패터닝된다. 그런 다음 도 4d와 같이, 포토레지스터패턴(42-a)된 투명기판(32) 상의 희생층(44)은 습식에칭(wet eching) 또는 건식에칭(dry eching) 중 하나를 선택하여 에칭을 한다. 특히, 건식에칭 때는 등방성 식각이 되도록 하고, 반드시 희생층(44))은 도 4d의 "A"처럼 포토레지스터패턴(42-a) 밑이 오목하게 들어 가게끔 에칭을 해야 한다. 왜냐하면, 희생층(44)을 에칭할시 포토레지스트패턴 밑의 희생층을 오목하게 들어가게 하지않고 포토레지스트패턴(42-a)과 같이 희생층을 수직으로 에칭할 시에는 ITO막(38-a)을 전면 증착 할때에 ITO막(38-a)은 패턴된 희생층(46)위를 타고 올라가 덮히게 된다. 이로인해, ITO막(38-a)을 전면 증착 한 다음 희생층(46)을 제거 할 때에 많은 어려움이있다. 오버에칭(Over etching)은 희생층(46)이 포토레지스터 패턴보다 작아지도록 과도하게 에칭하는 방법이다. 이때, 희생층(46)이 완전히 제거되도록 에칭되어서는 안되며 도 4d처럼 포토레지스터 패턴(42-a)를 지탱하여야 하며 포토레지스터 밑에 완전히 숨어야 한다. 이는 ITO증착시 희생층막을 타고 올라가 완전히 덮어버리는 것을 방지하기 위함이다. 그런 다음 도 4e처럼, ITO막을 전면 증착 하는 방법으로서 포토 레지스터패턴(42-a) 상과 노출된 투명 기판(32) 상에 ITO막(38-a)을 전면증착한다. 이때, 도 4d에서와 같이, 희생층(46)의 오버에칭으로 인해 도 4e와 같이 희생층(46)의 옆부분은 노출된다. 그런 다음, 희생층(46)을 제거하는 에천트용액에 의해 희생층(46)이 제거되는 동시에 희생층(46) 상에 있던 포토레지스터 패턴(42a) 및 ITO막(38a)도 제거된다. 이와같은 단계를 거치면 도 4f와 같이 미세한 ITO막(38b)만 남게 된다.Referring to FIG. 4C, a photo mask (not shown) is covered on the applied photoresist film 42 in FIG. 4B. And it is photopatterned by the photolithography method. Then, as shown in FIG. 4D, the sacrificial layer 44 on the photoresist pattern 42-a transparent substrate 32 is etched by selecting either wet etching or dry etching. In particular, when dry etching, the isotropic etching is performed, and the sacrificial layer 44 must be etched so that the bottom of the photoresist pattern 42-a is recessed as shown in "A" of FIG. 4D. This is because the ITO film 38-a is used to etch the sacrificial layer vertically like the photoresist pattern 42-a without recessing the sacrificial layer under the photoresist pattern when the sacrificial layer 44 is etched. When the entire deposition is performed, the ITO film 38-a is covered by rising on the patterned sacrificial layer 46. Because of this, there are many difficulties in removing the sacrificial layer 46 after the entire surface deposition of the ITO film 38-a. Over etching is a method of excessively etching the sacrificial layer 46 to be smaller than the photoresist pattern. At this time, the sacrificial layer 46 should not be etched to be completely removed and should support the photoresist pattern 42-a as shown in FIG. 4D and completely hide under the photoresist. This is to prevent the cover up completely by riding the sacrificial layer during ITO deposition. Then, as shown in FIG. 4E, the ITO film 38-a is deposited on the photoresist pattern 42-a and the exposed transparent substrate 32 as a method of depositing the ITO film on the entire surface. In this case, as shown in FIG. 4D, the side of the sacrificial layer 46 is exposed as shown in FIG. 4E due to overetching of the sacrificial layer 46. Thereafter, the sacrificial layer 46 is removed by the etchant solution for removing the sacrificial layer 46 and the photoresist pattern 42a and the ITO film 38a on the sacrificial layer 46 are also removed. After such a step, only the fine ITO film 38b remains as shown in FIG. 4F.
이와 같은 ITO막 패터닝 방법은 도 5와 같은 IPS 모드(In-Plane Switching)의 화소전극과 공통전극을 형성하는데 적용가능하다. 이를 상세히 하면 다음과 같다. IPS 모드는 수직전계로 구동되는 모드(예를 들면 TN모드)와 다르게 수평전계로 구동되어 수직전계로 구동되는 모드보다 광시야각을 구현할 수 가있다. 이와 반면에, IPS 모드는 수평전계를 구현하기 위해 하판상에 화소전극(51) 및 공통전극(50)을 형성하여야 만한다. 하지만, ITO막으로 화소전극(51) 및 공통전극(50)을 패턴링하여 하판에 형성하는데는 많은 어려움이 발생하게 된다. 이로인해, 종래에는 화소전극(51) 및 공통전극(50)을 ITO막 대신 금속전극으로 패터닝하여 형성하고 있다. 그러나, 금속전극을 사용하여 화소전극(51) 및 공통전극(50)을 형성하면 금속전극으로 인해 빛이 투과되는 면적이 줄어듬과 아울러 액정을 투과하는 빛의 양도 줄어들게되어 결국에는 휘도가 감소하게 된다. 따라서, 화소전극(51) 및 공통전극(50)을 본 발명에 따른 ITO막 미세패턴방법을 사용하여 ITO막으로 형성하여 금속전극으로 형성된 화소전극(51) 및 공통전극(50)의 문제점을 해결할 수 있다.This ITO film patterning method is applicable to forming the pixel electrode and the common electrode in the IPS mode (In-Plane Switching) as shown in FIG. This is described in detail as follows. Unlike the mode driven by the vertical electric field (for example, TN mode), the IPS mode can realize a wider viewing angle than the mode driven by the horizontal electric field. On the other hand, in the IPS mode, the pixel electrode 51 and the common electrode 50 must be formed on the lower plate to realize the horizontal electric field. However, it is difficult to pattern the pixel electrode 51 and the common electrode 50 with the ITO film to form the lower plate. For this reason, conventionally, the pixel electrode 51 and the common electrode 50 are formed by patterning with a metal electrode instead of the ITO film. However, when the pixel electrode 51 and the common electrode 50 are formed using the metal electrode, the area through which light is transmitted due to the metal electrode is reduced, and the amount of light passing through the liquid crystal is also reduced, resulting in a decrease in luminance. . Therefore, the pixel electrode 51 and the common electrode 50 are formed as an ITO film using the ITO film micropattern method according to the present invention to solve the problems of the pixel electrode 51 and the common electrode 50 formed of metal electrodes. Can be.
상술한 바와 같이, 본 발명에 따른 ITO막 패터닝방법은 희생층을 에칭하므로서 종래의 ITO막의 패턴불량을 최소화하고, 미세하게 ITO막을 패턴할 수 있다. 더나아가, 본 발명은 IPS 모드에서의 화소전극 및 공통전극을 금속전극 대신 투명전극으로 형성하므로써 IPS 모드로 된 제품의 휘도를 증가 시킬 수 있다.As described above, the ITO film patterning method according to the present invention can minimize the pattern defect of the conventional ITO film by etching the sacrificial layer, and can finely pattern the ITO film. Furthermore, the present invention can increase the luminance of the product in the IPS mode by forming the pixel electrode and the common electrode in the IPS mode as a transparent electrode instead of a metal electrode.
이상 설명한 내용을 통해 당업자라면 본 발명의 기술사상을 일탈하지 아니하는 범위에서 다양한 변경 및 수정이 가능함을 알 수 있을 것이다. 따라서, 본 발명의 기술적 범위는 명세서의 상세한 설명에 기재된 내용으로 한정되는 것이 아니라 특허 청구의 범위에 의해 정하여 져야만 할 것이다.Those skilled in the art will appreciate that various changes and modifications can be made without departing from the technical spirit of the present invention. Therefore, the technical scope of the present invention should not be limited to the contents described in the detailed description of the specification but should be defined by the claims.
Claims (4)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000039141A KR20020005152A (en) | 2000-07-08 | 2000-07-08 | Method of patterning Transpatent Conductive Film |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1020000039141A KR20020005152A (en) | 2000-07-08 | 2000-07-08 | Method of patterning Transpatent Conductive Film |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| KR20020005152A true KR20020005152A (en) | 2002-01-17 |
Family
ID=19677002
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1020000039141A KR20020005152A (en) | 2000-07-08 | 2000-07-08 | Method of patterning Transpatent Conductive Film |
Country Status (1)
| Country | Link |
|---|---|
| KR (1) | KR20020005152A (en) |
Cited By (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020041871A (en) * | 2000-11-29 | 2002-06-05 | 이규상 | Manufacturing method of transparent conductive layer of touch panel |
| WO2006107154A1 (en) * | 2005-03-16 | 2006-10-12 | Korea Advanced Institute Of Science And Technology | Integrated thin-film solar cells and method of manufacturing thereof and processing method of transparent electrode for integrated thin-film solar cells and structure thereof, and transparent substrate having processed transparent electrode |
| US8148626B2 (en) | 2005-12-14 | 2012-04-03 | Korea Advanced Institute Of Science & Technology | Integrated thin-film solar cell and method of manufacturing the same |
| US8449782B2 (en) | 2005-12-14 | 2013-05-28 | Korea Advanced Institute Of Science And Technology | See-through-type integrated thin-film solar cell, method of manufacturing the same and method of electrically series connecting unit cells thereof |
| KR20150013603A (en) * | 2012-04-27 | 2015-02-05 | 럭스뷰 테크놀로지 코포레이션 | Method of forming a micro led device with self-aligned metallization stack |
| WO2015127776A1 (en) * | 2014-02-25 | 2015-09-03 | 京东方科技集团股份有限公司 | Preparation method for transparent conductive electrode and array substrate |
| US9463613B2 (en) | 2011-11-18 | 2016-10-11 | Apple Inc. | Micro device transfer head heater assembly and method of transferring a micro device |
| US9620478B2 (en) | 2011-11-18 | 2017-04-11 | Apple Inc. | Method of fabricating a micro device transfer head |
| US9831383B2 (en) | 2011-11-18 | 2017-11-28 | Apple Inc. | LED array |
| US10297712B2 (en) | 2011-11-18 | 2019-05-21 | Apple Inc. | Micro LED display |
-
2000
- 2000-07-08 KR KR1020000039141A patent/KR20020005152A/en not_active Application Discontinuation
Cited By (18)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR20020041871A (en) * | 2000-11-29 | 2002-06-05 | 이규상 | Manufacturing method of transparent conductive layer of touch panel |
| WO2006107154A1 (en) * | 2005-03-16 | 2006-10-12 | Korea Advanced Institute Of Science And Technology | Integrated thin-film solar cells and method of manufacturing thereof and processing method of transparent electrode for integrated thin-film solar cells and structure thereof, and transparent substrate having processed transparent electrode |
| US7927497B2 (en) | 2005-03-16 | 2011-04-19 | Korea Advanced Institute Of Science And Technology | Integrated thin-film solar cells and method of manufacturing thereof and processing method of transparent electrode for integrated thin-film solar cells and structure thereof, and transparent substrate having processed transparent electrode |
| US8153885B2 (en) | 2005-12-14 | 2012-04-10 | Korea Advanced Institute Of Science & Technology | Integrated thin-film solar cell and method of manufacturing the same |
| US8168882B2 (en) | 2005-12-14 | 2012-05-01 | Korea Advanced Institute Of Science & Technology | Integrated thin-film solar cell and method of manufacturing the same |
| US8449782B2 (en) | 2005-12-14 | 2013-05-28 | Korea Advanced Institute Of Science And Technology | See-through-type integrated thin-film solar cell, method of manufacturing the same and method of electrically series connecting unit cells thereof |
| US8148626B2 (en) | 2005-12-14 | 2012-04-03 | Korea Advanced Institute Of Science & Technology | Integrated thin-film solar cell and method of manufacturing the same |
| US10607961B2 (en) | 2011-11-18 | 2020-03-31 | Apple Inc. | Micro device transfer head heater assembly and method of transferring a micro device |
| US9463613B2 (en) | 2011-11-18 | 2016-10-11 | Apple Inc. | Micro device transfer head heater assembly and method of transferring a micro device |
| US9620478B2 (en) | 2011-11-18 | 2017-04-11 | Apple Inc. | Method of fabricating a micro device transfer head |
| US11552046B2 (en) | 2011-11-18 | 2023-01-10 | Apple Inc. | Micro device transfer head assembly |
| US9831383B2 (en) | 2011-11-18 | 2017-11-28 | Apple Inc. | LED array |
| US10121864B2 (en) | 2011-11-18 | 2018-11-06 | Apple Inc. | Micro device transfer head heater assembly and method of transferring a micro device |
| US10297712B2 (en) | 2011-11-18 | 2019-05-21 | Apple Inc. | Micro LED display |
| KR20150013603A (en) * | 2012-04-27 | 2015-02-05 | 럭스뷰 테크놀로지 코포레이션 | Method of forming a micro led device with self-aligned metallization stack |
| US9548332B2 (en) | 2012-04-27 | 2017-01-17 | Apple Inc. | Method of forming a micro LED device with self-aligned metallization stack |
| WO2015127776A1 (en) * | 2014-02-25 | 2015-09-03 | 京东方科技集团股份有限公司 | Preparation method for transparent conductive electrode and array substrate |
| US9659975B2 (en) | 2014-02-25 | 2017-05-23 | Boe Technology Group Co., Ltd. | Fabrication methods of transparent conductive electrode and array substrate |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8148727B2 (en) | Display device having oxide thin film transistor and fabrication method thereof | |
| US9754979B2 (en) | Display device, thin film transistor, array substrate and manufacturing method thereof | |
| JP4967631B2 (en) | Display device | |
| KR20040095045A (en) | Thin film transistor array substrate and fabricating method thereof | |
| US7167217B2 (en) | Liquid crystal display device and method for manufacturing the same | |
| KR20050067934A (en) | Method for forming metal line and method for manufacturing liquid crystal display device using the same | |
| US6500702B2 (en) | Method for manufacturing thin film transistor liquid crystal display | |
| US20180151749A1 (en) | Thin Film Transistor, Array Substrate and Methods for Manufacturing and Driving the same and Display Device | |
| KR20040031370A (en) | Liquid Crystal Display Panel And Fabricating Method Thereof | |
| KR20020005152A (en) | Method of patterning Transpatent Conductive Film | |
| US6330042B1 (en) | Liquid crystal display and the method of manufacturing the same | |
| US8421941B2 (en) | TFT substrate and method of manufacturing the same | |
| CN101017832A (en) | Thin film transistors substrate, manufacture method therefore and display panel having same | |
| US6847413B2 (en) | Liquid crystal display device and method for manufacturing the same | |
| KR20180010655A (en) | Method of manufacturing thin film transistor and method of manufacturing flat panel display device | |
| JP2009093145A (en) | Display device and method of manufacturing same | |
| KR100675937B1 (en) | Method for fabricating array substrate of TFT-LCD | |
| KR20020002516A (en) | Method for forming gate electrode in liquid crystal display device | |
| KR101097675B1 (en) | Thin film transistor and fabricating method thereof | |
| KR101023715B1 (en) | Method for fabricating of Liquid Crystal Display Device | |
| KR101285535B1 (en) | Thin Film Transistor Substrate and Method thereof | |
| KR100492728B1 (en) | A liquid crystal display device having partially removed activation layer in drain region and method of fabricating thereof | |
| KR20040036987A (en) | Thin film transistor array panel for liquid crystal display and manufacturing method of the same | |
| KR101057235B1 (en) | Etchant and manufacturing method of thin film transistor using same | |
| KR0146251B1 (en) | Thin film transistor manufacturing method for liquid crystal device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| WITN | Withdrawal due to no request for examination |