TW200811565A - TFT array substrate and method of manufacturing the same, and display device using the same - Google Patents

Abstract

To provide a display device having excellent display quality and high productivity. A TFT array substrate has on a substrate 110, a gate electrode 1, a gate insulating film 3, a semiconductor layer 23, source and drain electrodes 11b and 11c composed of a transparent conductive film 11 and a pixel electrode 11a extended from the drain electrode 11c. An interlayer dielectric 8 having a source electrode contact hole 27 reaching the source electrode 11b and a source line 22 connected to the source electrode 11b through the source electrode contact hole 27 are formed on the transparent conductive film 11.

Description

200811565 IX. Description of the Invention: [Technical Field] The present invention relates to a thin film transistor array substrate, a method of manufacturing the same, and a display device using the same. [Prior Art] An active matrix type liquid crystal display using a simple type of liquid crystal display device and a switching element is used for an optical optical device using a liquid crystal display (di sp 1 ay ) Device. In particular, in an active matrix type liquid crystal display device, a thin film transistor (TFT)-LCD is widely used for a notebook computer because of its portability and poor quality. In a TFT-LCD, generally, a liquid crystal layer is interposed between a thin film transistor array substrate and a counter substrate. τ{?τ forms an array on the thin film transistor array substrate. A polarizing plate is disposed on each of the thin film transistor array substrate and the opposite side of the opposite substrate. Also, a backlight (back 1 ight) source is provided on one side. In order to reduce the manufacturing cost of the display device, the reduction in the manufacturing cost of the thin film transistor array substrate is also a major issue. By reducing the number of times of the lithography process in the manufacturing process of the thin film transistor array substrate, a technique for simplifying the process has been proposed (licensed documents 1, 2). , revealing a slanting key n for the + n 丨τ structure to perform a five-time lithography process on the enamel transistor array substrate to form an active moment beam

Manufacture of a first-running early-type liquid crystal display device 2185-8937-PF 5 200811565 A method for a thin film transistor array base matrix type liquid crystal display device, in Patent Document 2, a board is disclosed for 4 or 5 lithography The process forms the main manufacturing method. A plan view of a thin film transistor array substrate of a conventional example disclosed in Patent Document 1 is shown in Fig. 11; and a cross-sectional view of a main portion thereof is shown green in Figs. Figure 12 is a cross-sectional view showing the cut portion of Figure η. FIG. 13 and FIG. 4 are typical views showing a cross-sectional structure of a terminal portion of a Tcp (Tape Carrier Package) provided on the outer side of the display region. The Tcp is supplied with a signal potential from the signal potential source of the gate wiring, the source (SGU (10) wiring, the auxiliary capacity wiring, and the common electrode of the opposite substrate to the gate wiring, the source wiring, the auxiliary capacity wiring, and the common electrode. As shown in FIG. 12, the TFT | & μ ^ substrate of the conventional example is a semiconductor covering the gate electrode 1 on the substrate 110, the gate insulating film 3 of the gate electrode 1jL, and the interlayer insulating film 3. The layer 23, the source electrode 7 on the semiconductor layer 23, and the drain (the draiiO electrode 6, the source electrode 7, and the drain electrode 6)

It is formed 'and includes an interlayer insulating film 8 having a COMM hall 9 reaching the gate electrode 6 and a transparent conductive film 11 on the interlayer insulating film 8. The semiconductor layer 23 includes a semiconductor active film 4 and an ohmic contact contact film 5 〇 a gate electrode 1 is a portion of the gate wiring 21 or an electrode which is a terminal which is branched from the gate wiring 21 and connected to each TFT. Further, one portion of the auxiliary capacity wiring 20 is disposed so as to overlap the transparent conductive film u, and a supplementary capacity is formed. In the thin film transistor array substrate described in Patent Document 1, the source

2185-8937-PF 6 200811565 The wiring 22 and the source electrode 7 do not exceed the step of the semiconductor layer 23 in the display portion. Therefore, it is possible to avoid the occurrence of disconnection of the pole wiring 22 and the source electrode 7 due to the step difference of the semiconductor layer 23. Further, a semiconductor layer 23 is provided in the vicinity of the periphery of the transparent conductive film u. However, the transparent conductive film u and the semiconductor layer 23, and the transparent conductive film u and the source wiring 22 are separated by the interlayer insulating film 8. Thereby, the pattern of the semiconductor layer 23 and the source wiring a can be prevented from being defective. Therefore, it is possible to prevent a short circuit between the source wiring 22 and the transparent conductive film 11 or a short circuit when the semiconductor active film 4 is reduced in resistance under light irradiation. However, in the thin film transistor array substrate described in Patent Document 1, when the A1 film is used for the source wiring 22, micro-protrusions (H1U〇ck) are generated on the surface of the A1 film due to heating, and interlayer insulation is not generated. 'Good question. In addition, an oxide layer is formed between the source wiring 2 2 and the transparent conductive film 11, and the contact resistance between the source wiring 2 2 and the transparent conductive film 变 is increased, resulting in display failure. Further, in the case where a single-layer A1 film is used for the metal thin film material of the source wiring 22, in the connection portion of the semiconductor layer 23 electrically connected to the source wiring 22, mutual diffusion of A1 xiao Si is caused, and there is contact. The resistance becomes high and causes a problem of poor display. As disclosed in Patent Document 2, in order to minimize the contact resistance between the halogen electrode and the drain electrode, the gate wiring or the gate electrode is formed as a laminated structure composed of the first layer and the second layer, wherein the jth layer It is composed of an alloy, and the second layer is formed by adding at least one of N, c, and yttrium to the A1 or Al alloy; and the source electrode and the source are formed.

2185-8937-PF 200811565 Wiring and drain electrodes? It is a structure in which a film is formed as a single layer of a Mo alloy or an acoustic layer of an A1 alloy and a Mo alloy. In Patent Document 3, a method of simulating a high melting point metal such as yttrium, p, lanthanum/cr or Mo on the A1 film is disclosed as a barrier to interlayer insulation caused by a microbend 3?4^ and The contact with the transparent conductive film 11 is poor, and Wei, a high-melting point metal is formed under the layer of the A1 film, and a method of preventing contact with the semiconductor layer 23 is prevented. Further, Patent Document 4 discloses a technique in which a source signal line, a source electrode, a drain electrode, and a passivation electrode are formed in a same layer. Thereby, contact failure can be prevented. [Patent Document 2] JP-A-2005-62802, paragraph number 0027 [Patent Document 3] JP-A-2000-284326 [Private Document 4] Special Edition 2000 In the thin film transistor array substrate of the patent document 2, the material of the first metal thin film such as the gate wiring is required to be two or more types. Further, in the thin film transistor array substrate described in the third aspect of the invention, the source wiring material requires two types (A1 and Cr or M〇 high melting point metal) or more. As a result, the cost increase due to an increase in the number of manufacturing processes of film formation and etching is unavoidable. Further, in Patent Document 3, since the source wiring has a three-layer structure, it is difficult to control the cross-sectional shape after processing, and there is a problem that the yield is lowered.

2185-8937-PF 8 200811565 Further, in the thin film transistor array substrate described in Patent Document 4, the source 彳5 line, the source electrode, the drain electrode, and the transmissive element electrode are composed of a transparent conductive film and a metal film. . In the case of I, two or more types of materials are required, and the cost increases due to an increase in the number of manufacturing processes such as film formation and etching. Moreover, since there is no interlayer insulating film between the source signal line and the transmissive element electrode, the source signal line and the transmissive element electrode are short-circuited (Short), which causes problems such as a decrease in yield due to lighting failure. point. On the other hand, in the thin film transistor array substrate described in Patent Document 1, a low-resistance Ag film is used as a wiring material of a metal thin film of the source wiring 22. However, in general, Ag has low plasma resistance and has a problem that Ag in the contact hole disappears when the contact hole is formed. In view of the above background, the present invention provides an apparatus which is excellent in display quality and productive in the south. [Means for Solving the Problem] The thin film transistor array substrate of the present invention includes: a gate electrode provided on the substrate; a gate insulating film formed on the gate electrode; and a semiconductor layer formed on the gate insulating film And disposed on the opposite side of the gate electrode; the source electrode and the drain electrode are composed of a transparent conductive film formed on the semiconductor layer; the pixel is electrically extended from the gate electrode, and the transparent a conductive film composition; an inter-f insulating film formed on the halogen electrode, the source electrode 'and the (four) electrode 'having a contact hole reaching the source electrode; and a source wiring ' formed on the interlayer insulating film And connected to the source electrode via the contact hole. 2185-8937-PF 9 200811565 [Effect of the Invention] Apparatus According to the present invention, it is possible to provide a display having excellent display quality and high productivity. [Embodiment] The brother and the moon can be applied to the embodiment of the present invention. The following description relates to the embodiments of the present invention, but the present invention is not limited to the following embodiments. Embodiment 1. First, an active matrix type display device to which a thin film transistor array substrate of the present invention is applied will be described with reference to Fig. 1 . Fig. 1 is a plan view showing the configuration of a thin film transistor array substrate for a display device. Although the display device of the present invention has been described by taking a liquid crystal display device as an example, only one of them may be used, and a flat display device such as an organic EL display device may be used. The display device of the present invention has a substrate 110. The substrate 11 is, for example, a thin film transistor array substrate. A margin area 丨丨2 is provided on the substrate 11 to surround the display area 111. In the display area 丨i丨, a plurality of gate wirings (the imaginary line "number line" 21 and a plurality of source wirings (display signal lines) 2 2 are formed. The plurality of gate wirings 21 are arranged in parallel. A plurality of source wirings 22 are provided in parallel. The gate wiring 21 and the source wiring 22 are formed to intersect each other. The gate wiring 21 and the source wiring 22 are orthogonal to each other. Further, the adjacent gate wiring 21 and the source are provided. The area surrounded by the wiring 22 is a halogen sheet 7. Therefore, in the substrate 110, the halogen 11 7 is arranged in a matrix. 2185-8937-PF 10 200811565 Moreover, a sweep is provided in the fore edge region 112 of the substrate 110. The tracking signal driving circuit 115 and the display signal driving circuit 116. The gate wiring 21 extends from the display region 111 to the front edge region 112. The gate wiring 21 is connected to the scanning signal driving circuit 115 at the end of the substrate. Similarly, 22 extends from the display region 111 to the fore edge region 112. The source wiring 22 is connected to the display signal drive circuit i6 at the end of the substrate 110. The external wiring 118 is connected in the vicinity of the scan signal drive circuit 丨15. In addition, external wiring 11 9 In the vicinity of the display signal drive circuit 丨丨6, the external wiring 丨丨8, 119 is a wiring board such as a printedFPC (Flexible Print Circuit). Various external signals are supplied to the scan by the external wiring 丨丨8 and 丨丨9. The signal driving circuit 117 and the display signal driving circuit 丨丨6. The scanning signal driving circuit 115 supplies a gate signal (scanning signal) to the gate wiring 21 based on a control signal from the outside. The gate wiring 21 is sequentially selected. The display signal driving circuit 116 supplies a display signal to the source wiring 22 in accordance with control from external control or data display. Thereby, the display voltage corresponding to the display data is supplied to Each of the halogens 117. At least one of the TFTs 12 is formed in the pixel 117 (the TFT 12 is disposed in the vicinity of the intersection of the source wiring 22 and the gate wiring 21. For example, this τρτΐ2〇 supplies the display voltage to the pixel electrode. That is, TFn2 is turned on as a switching element by the gate signal from the gate wiring 21. Thereby, a voltage is not applied from the source wiring 22 to be connected to the drain electrode of the TFT. On day pixel electrode. 1 and, in response to the pixel electrode day display field voltage. Further, formed on the surface of the substrate with 11〇 (not between the electrodes to produce the film

display). 2185-8937-PF 11 200811565 Further, the 'opposing substrate is disposed opposite to the substrate 11'. The counter substrate, for example, a color fiiter substrate, is disposed on the viewing side. A color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed on the opposite substrate. Further, the counter electrode may be disposed on the substrate 110 side. Further, a liquid crystal layer is interposed between the substrate 11 and the opposite substrate. That is, liquid crystal is injected between the substrate 11 and the opposite substrate. Further, a polarizing plate, a phase difference plate, and the like are disposed on the surface of the substrate 11 and the outer surface of the counter substrate. In addition, a backlight unit or the like is disposed on the opposite side of the liquid crystal display panel. The liquid crystal is driven by an electric field between the halogen electrode and the counter electrode. That is to say, the alignment direction of the liquid crystal between the substrates changes. Thereby, the polarization state of the light passing through the liquid crystal layer changes. In other words, the light that passes through the polarizing plate and becomes linearly polarized changes the polarization state by the liquid crystal layer. Specifically, a light from the backlight unit is linearly polarized by a polarizing plate on the array substrate side. Further, the polarization state is changed by the linear polarized light passing through the liquid crystal layer. Therefore, in response to the polarization state, the light i of the polarizing plate on the opposite substrate side is k-ized. In other words, in the transmitted light transmitted from the backlight unit through the liquid crystal display panel, the amount of light passing through the polarizing plate on the viewing side changes. The alignment direction of the liquid crystal changes due to the applied display voltage. Therefore, by controlling the display voltage, the amount of light passing through the polarizing plate on the viewing side can be changed. That is to say, by changing the display voltage at each element, the desired image can be displayed. Next, regarding the configuration of the TFT 120 on the substrate 110, FIG. 2 and

2185-893 7-PF 12 200811565 Figure 3 illustrates. Fig. 2 is a plan view showing the configuration of a main portion of a thin film transistor array substrate according to an embodiment of the present invention. Figure 3 is a cross-sectional view showing the χ- —' portion of the thin film transistor array substrate of Figure 2. A plurality of gate wirings 21 are provided in parallel to the substrate 。. Further, the source wirings 22 are also disposed in parallel. The gate wiring 21 and the source wiring 22 are formed to be mutually intersected. The gate wiring 21 is orthogonal to the source wiring 22. Further, a halogen electrode 11a is formed on a region surrounded by the adjacent gate wiring .21 and the source wiring 22. 1. The gate wiring 21 is connected to the gate electrode 丨. The auxiliary capacity wiring 2 is disposed between the adjacent gate wirings 21. The auxiliary capacity wiring 2 () is formed in parallel with the idle wiring 21 . Further, the auxiliary capacity wiring 2 is opposed to the halogen electrode 11a. Thereby, the subsidized capacity is formed. The difference between the idler wiring and the source wiring 22 is formed as a switching element. The TFT 120 has a semiconductor layer 23 composed of a semiconductor active film 4 and an ohmic contact film $. The semiconductor layer 23 is formed over the gate electrode i. The drain electrode 11c is formed integrally with the pixel electrode Ua, and a drain electrode and a source electrode Ub are formed on the semiconductor layer 23. An interlayer insulating film 8 is formed over the source electrode 11b and the drain electrode. A source wiring 22 is formed on the interlayer insulating film 8. Further, in the layer: 曰: the insulating film 8 forms a source electrode contact hole π which reaches the source electrode m: the source electrode contact hole 27 is finely connected, and the source electrode Ub is electrically connected to the source wiring. The pixel electrode 11a extends from the drain electrode Uc. That is to say, the method of making it. Fig. 4 is a view showing a manufacturing step of the TFT 120 in the present embodiment. and

2185-8937-PF 13 200811565 5 lithography process to manufacture a thin film transistor array substrate. (A) First lithography process (a) First, the substrate u 等 such as a glass substrate is washed with pure water. In this case, it is also possible to use hot sulfuric acid instead of pure water for washing. (b) Next, a first metal thin film for forming the gate electrode 1, the gate wiring 21, and the auxiliary capacity wiring 20 is formed on the substrate 110. (c) In order to pattern the first metal thin film, the first lithography process is performed. Specifically, a photoresist pattern is formed by applying a resist, exposure, and development. In the first metal thin film, it is preferable to use an alloy having a low specific electrical resistance, A1, M?, Cr, or an alloy containing the above materials as a main component. In the present embodiment, an A1Nd alloy in which 2 mol% of Nd is added to A1 can be used. For example, an AINd film having a film thickness of 200 nm is formed by using an Ar (gas) DC magnetron sputtering method. (d) Thereafter, the A1Nd film was wet-etched (wet etchmg) using a conventional solution containing phosphoric acid and bowl acid. (e) Then, the photoresist pattern was peeled off and washed with pure water. The gate electrode 1, the gate wiring 21, and the auxiliary capacity wiring 2 are formed. (B) The second lithography process + (〇, sequentially, a semiconductor active film composed of tantalum nitride (SiN), and an amorphous active film, UmOrphQUS si ! i _), An ohmic contact film 5 composed of n + amorphous, 屯 之 n + amorphous 矽. (g) The first patterned semiconductor active film 4 and the ohmic contact film 5 are subjected to a second port U?. In this case, in addition to the portion including the thin film transistor, the pattern of the source wiring 22 and the gate electrode 11 c formed by the later-described mounting is formed to be large and continuous. In this embodiment, use

2185-8937-PF 14 200811565 vapor deposition method), sequentially forming a 4QGnm thick siN film as the first]: a 150 nm thick amorphous germanium film as a semiconductor active film*, thick and phosphorus (P) The amorphous magnetic film of the impurity is used as an ohmic contact film, and the semiconductor active film 4 and the ohmic junction are etched by dry etching using a fluorine-based gas. (1) Thereafter, the photoresist pattern was peeled off and washed with pure water > r. Thereby, the semiconductor layer 23 composed of the semiconductor active m 4 and the ohmic contacts *, 5 is formed as a semiconductor pattern. Further, the first insulating film serves as the gate insulating film 3. In this case, impurities may also be added after film formation. (C) Third lithography process (1) Next, a transparent conductive film u is formed. (1) The third lithography process is performed to pattern the transparent conductive film η. A drain electrode llc, a halogen electrode 11a, and a source electrode 11b are formed. Further, in the above (4), the gate terminal pad for the signal to be gated in the gate wiring 21 # and the source terminal (four) for the supply of (4) to the secret (four) 22 are simultaneously formed ((4)). Take this implementation. and. Indium oxide (In2〇3) and tin oxide (Sn film is used as the transparent conductive film U. The transparent conductive film u of ιο〇ηω thick is formed by a conventional sputtering method using Ar gas. (1) Then Wet (four) 1 is formed using a conventional solution containing guanidine hydrochloride, forming (four) electricity, Uc, pixel electrode 11a, source electrode 11b, gate terminal lining and source terminal lining. The composition of the lining and the source terminal pad is described later. Further, the ohmic contact film 5 between the source electrode m and the galvanic electrode lc is dry etched using a conventional fluorine-based gas. 00 Next, the photoresist pattern was peeled off and washed with pure water. By this shape

2185-8937-PF 200811565 Source electrode 11 b, drain electrode 11 c, pixel electrode π a, tf T channel portion 26, gate terminal pad, and source terminal pad. In the foregoing, the transparent conductive film u is formed of a ΙΤ0 film. In this case, an amorphous IT tantalum film can also be used. Further, a tin oxide film, an indium oxide film, or a zinc oxide film may be used as the transparent conductive film 11 . Further, a ruthenium film mixed with indium oxide and zinc oxide or an I τ ζ film in which indium oxide is mixed with tin oxide and zinc oxide may also be used. The above transparent conductive film 11 can be etched using a weak acid oxalic acid. Therefore, when etching the transparent conductive film u, since the other wirings and electrodes are not corroded, the yield can be improved. (D) The fourth lithography process () is formed by forming a second insulating film composed of s i N in order to form the interlayer insulating film 8. In the present embodiment, a 300 nm-thick tantalum nitride (SiN) film is formed by a chemical vapor deposition (CVD) method to serve as a second insulating film. (P) Next, the fourth lithography process is performed. After (q), dry etching was performed using a fluorine-based gas of Shichi. (r) At this time, a beton-to-source electrode is formed in the second insulating film! The source electrode of the lb surface contacts the hole 2. Thereafter, the photoresist pattern was peeled off and washed with pure water. Thereby, the interlayer insulating film 8 having the source electrode contact holes 27 is formed. (E) Fifth lithography process (s) Next, a second metal thin film is formed. In the case of the second metal thin film, it is preferred to use an alloy of M or Al. It is also possible to use Cr or a Cr alloy, Mo or M 1 in the present embodiment, by using a conventional Wei method of Ar gas, and forming an AINi alloy film of 20η Λ r-^ into a thickness of 20 ηππ (in Add 2mol to A1

Ni) 0 2185-8937-PF 16 200811565 (t) In order to pattern the second metal thin layer, the fifth lithography is performed and "etching is performed using a conventional solution containing tannic acid and nitric acid. (7) Thereafter, the photoresist pattern is peeled off to pattern the second metal thin film. Thus, the conductive film 19 in the same layer as the source wiring 22 is formed, and the pot-and-pole wiring 22 is connected to the source by the source electrode contact hole 27. , sexual connection (refer to Figure 5, 6). In other words, ^ ^ is also the soul, the conductive film 19 is formed by the metal ruthenium film. Moreover, in the fifth lithography process (8), : the terminal lining pattern 28 and the intermediate terminal pad pattern 29 (see FIG. 5, specifically, as shown in FIG. 5, the closed terminal outline pattern 29 connected by the gate terminal contact hole 31 and the interpole wiring 21 is utilized. The conductive film J9 is formed. Moreover, FIG. 5 is a cross-sectional view of the structure in which the ', ', and ' days are not used to input the closed terminal portion of the gate wiring 21. Moreover, as shown in FIG. The source terminal contacts the hole 32 and is connected to the source terminal. The source is connected to the source and the sub-line is 塾2 8 #南丨田it life j The conductive film 19 is formed. Further, the source terminal pad pattern 28 extends from the source with green, and the spring 22. Figure 6 shows the input for the source wiring 2 2 for the eve, shop #山, ° A cross-sectional view of the composition of the source cake portion. The gate and the source terminal are arranged in the fore edge region 112. The non-gate terminal pad pattern 29 of Figure 5 is designed. The contact hole 33 of the interlayer insulating film 8 is connected to the gate terminal 14 formed of the transparent V film 11. Moreover, the gate „ ^ ^ closed-pole sub-pad pattern 29 is provided by The interlayer insulating film 8 is connected to the gate insulating film (refer to FIG. 5 and FIG. 31). Therefore, the gate wiring 21 and the gate terminal pad 14 are electrically connected by the gate pad pattern 29. Sexual connection. Moreover, the source lining pattern 28 and the source terminal lining _ are set between the layers

2185-8937-PF 17 200811565 The two-source sub-portion contact hole 32 is produced and connected (see Fig. 6). Here, the inter-polar signal and the source signal are respectively supplied to the gate wiring 2 and the source wiring & by the transparent conductive film u ^ sub«, and are set at the extremes + 12, rn^, Each contact hole of the 汲 extreme part is formed in the fourth 制 制 私 (D). In the prior art, an A1 film or a Α1 alloy film is used as a source with A 彳 green, π β + , and! - Under the condition of the source electrode and the drain electrode, it must be separated from the upper layer of the A1 film or the A1 alloy film. (1) The metal is melted with Cr or Mo. By 匕 'preventing the A1 film a 1 , 盥 妓 妓 妓 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人 人As stated by Ren Ruli, it is necessary to stack A1, or A1, gold film, and there is a problem that the number of manufacturing increases. According to the present invention, the transparent tail film 11 is used by the d-electrode electrode 11a (for example, Ττπ, r rr / , , , and the source electrode 11 b and the drain electrode c are formed. Therefore, in ohm The contact film 5 and the source wiring (4) Ni) 22 are sandwiched by a transparent lightning-guide film, and the remaining layer of the film is not required to be stacked. As a result, it is possible to prevent the deterioration of the electrical contact characteristics caused by the mutual diffusion of A1 "1" without adding the I-work number of the galvanic layer due to the above-mentioned laminate. Further, in the prior art, Since ^ ΤΤΛ ^ Τ is directly formed by the Α1 or A1 alloy film (the lower 曰, the IT0 film (upper layer)), and the structure is increased, it is known that it is produced at the contact portion. In the present invention, the 1T0 film is ruthenium, and the A1 or A1 alloy is the upper layer. The electrical contact characteristics of Duguo. - The result is a substantial improvement in Μ and IT. σ electrical contact. 'There will be IT0 hair in the developer solution

2185-8937-PF 18 200811565 The birth of the rot. As a result, it is preferable that the group of the group elements (Ni, Co, Fe, etc.) has a total of A1, a seven-milk (8) film or an A1 alloy film cup of the metal above the 8th 8 m A 表 table. Among the above-mentioned bismuth alloys of metals, (a) elements of Group 8 of the periodic table, middle bismuth, and A1 alloy film of rat. Can provide this can solve this problem and the rate of ancient fine this, ^ Liang Yang 溥 溥 film transistor array substrate. In the present embodiment, the interlayer insulating film 8 is provided between the source wiring 22 and the halogen transparent conductive film 11. Therefore, for example, the source electrode, the electrodeless electrode, and the source electrode disclosed in the Japanese Patent Publication No. 3 are good because the source wiring Μ and the transparent conductive film are formed when the pixel electrode is formed in the same layer. The problem of electrical short circuit or defective lighting is as described above. It is described that the gate electrode lining pattern 29 is formed by the transparent conductive film 11. However, in the case where the transparent conductive film η is not required, as shown in FIG. The gate terminal pad 14 can be formed simultaneously with the second metal film. Further, as shown in FIG. 8, the source terminal pad 18 can be formed by the source wiring 22 and the same layer of the conductive film 19. 2. Next, the configuration of the thin film transistor array substrate for a display device according to the second embodiment of the present invention will be described with reference to Fig. 9 and Fig. 10. Fig. 9 is a thin film transistor array substrate for a liquid crystal display device of the second embodiment. Fig. 1 is a cross-sectional view showing a portion Y-Y' of Fig. 9. In the present embodiment, in addition to the configuration shown in the first embodiment, a halogen reflective electrode 25 is provided. The configuration 'is the same as in the first embodiment For the sake of explanation, the description will be omitted. The difference between the constituents will be described below. 2185-8937-PF 19 200811565 First, an interlayer insulating film having a source electrode contact hole 27 and a halogen contact hole 24 is laminated so as to cover the transparent conductive film 11. 8. The source wiring 22 and the halogen reflection electrode 25 are provided on the interlayer insulating film 8. The halogen electrode 11a is connected to the halogen reflection electrode 25 by the halogen contact hole 24. Thus, the second embodiment is also used. The second metal thin film formed in the first embodiment (E) is used as the pixel reflective electrode 25. In other words, the halogen reflective electrode 25 is provided with the halogen reflective electrode by the source wiring 22 and the same layer forming form 2. The device is formed by the conductive film 19. The semi-transmissive liquid crystal display is also provided with a pixel reflective electrode 25 in which a portion of the elementary reflection electrode 25 of the pixel electrode 11a is not formed as a transmissive portion. In the manufacturing process of the second embodiment, a semi-transmissive liquid crystal display device having a transmissive portion and a reflecting portion in a single denier can be formed by forming the pixel reflective electrode 25. Figure 4 In the present embodiment 2, in addition to the manufacturing steps shown in the first embodiment, v is the i-ray reflective electrode 25 and the halogen contact hole 24. Further, the steps are formed, and the same embodiment is omitted. (D) The fourth lithography process is the same as that of the first embodiment in the step shown in (8) of Fig. 4, that is, in the second embodiment, the gate electrode He is formed to penetrate to The alizarin contact hole 24 on the surface of the extensor electrode Ua. (E) The lithography process of the 5th lithography process is shown in the step shown in (1) of Fig. 4 except for the following points.

2185-8937-PF 20 200811565 The form i is the same. That is, when the pattern of the second metal thin film is formed, the halogen reflective electrode 25 is formed. Further, the pixel reflective electrode 25 is formed so as to be electrically connected to the drain electrode 11c and the halogen electrode 3511a by the halogen contact hole 24. Thereby, the completion of the sound is taken from 0 to the film-forming transistor array substrate for liquid crystal display. In the case of the second metal thin film in which only V is used, it is preferable to use an AINi having a low electrical specific resistance and good electrical contact characteristics and reflection characteristics with the transparent conductive m U . A1Nl is preferably a material having a Ni of 2m 〇 1% in A1. f Stereo Bear In the present embodiment, the point different from the second embodiment is that Ag or an Ag alloy is used for the second metal thin film. Therefore, the description of the contents common to the second embodiment will be omitted. By using 竑 or in the 帛2 metal film

The Ag alloy can provide a thin film transistor array substrate for a transflective liquid crystal display which has low resistance and excellent reflection characteristics and is excellent in optical characteristics and electrical characteristics. Patent Document 1 describes that an Ag film is used for the source wiring 22 and the like. However, when the contact hole is formed, the use of the plasma during dry etching causes the Ag to be damaged and the problem of disappearance. Therefore, it is difficult to use in conventional TFT construction.

Ag and Ag alloys. However, in the present invention, the source wiring 22 is formed after the contact hole is formed. Therefore, the source wiring line located in the upper layer does not suffer from the plasma damage caused by the dry residue, and the deterioration of the electrical characteristics can be prevented. Further, in the case where the second metal thin film is made of an Ag alloy, it is preferably

2185-8937-PF 21 200811565 It is one or more types of Pd, Cu, Mo, Nd, Ru, Ge, Au, and SnOx. Thereby, a source wiring having excellent adhesion and low resistance can be obtained. Further, a halogen reflective electrode excellent in adhesion and reflection characteristics can be formed. (Embodiment) In the present embodiment, a point different from that of the first embodiment is the use of Cu or a Cu alloy in the second metal thin film. Therefore, the description of the contents common to the first embodiment will be omitted. By using a Cu or Cu alloy having a lower electric resistance than A1 in the second metal thin film, it is possible to provide a high-definition and large-faced thin film transistor array substrate. Further, when a CuMo alloy film in which Mo is added to Cu is used, a source wiring having excellent adhesion and low resistance can be formed. In the prior art, since it is difficult to control etching when Cu or a Cu alloy is formed into a thick film, the cross-sectional shape of both sides of the wiring is deteriorated, and it is difficult to form an electric element such as a halogen electrode in the upper layer of the Cu film. . In the present invention, the second metal thin film is formed on the uppermost layer of the thin film transistor array substrate. Thereby, the cross-sectional shape does not affect the yield. The transparent conductive film 11 of the first to fourth embodiments is used as the source electrode 7, the drain electrode 6, the gate terminal pad pattern, and the source terminal pad pattern. Further, in the configuration of the first to fourth embodiments, the source wiring 22 can be made of a single layer, and a display device having high display quality and high productivity can be provided. Further, a transparent conductive film 电 electrically connected to the source wiring 22 may be formed under the source wiring 22. For example, the permeable solar cell film 11 having almost the same shape as the source wiring 22 may be formed under the source wiring 22 via the interlayer insulating film 8. In this case, the interlayer insulating film 8 under the source wiring 2 2 must form an infinite number of contact holes, and the source wiring 22 and

2185-8937-PF 22 200811565

The transparent conductive film 11 is connected. The flat conductive traces of the lower layer of the source wiring 22 and the source wiring 22 are formed flat by the same N-degree. That is, the source wiring 22 and the transparent conductive film (1) under the source wiring 22 are formed in the same pattern shape. Therefore, in the third lithography process (6), when the transparent conductive film 11 is formed, the transparent conductive film 11 is formed in the direction in which the source wiring 22 is placed in the puddle. Further, in the same manner as the source and line 22, the interlayer, the 'bar film 8', and a part or all of the source wiring 22 are formed as the source wiring 22 (upper layer) and The laminated structure of the transparent conductive film u (lower layer) may be used. In this case, even if the source wiring 22 is broken, a transparent conductive film is formed under the broken portion, so that the effect of redundant wiring is obtained. Further, a high-yield thin film transistor array substrate can be provided. [Schematic Description] [Fig. 1] A plan view showing a configuration of a thin film transistor array substrate according to an embodiment of the present invention. [Fig. 2] Fig. 3 is a cross-sectional view showing the structure of a thin film transistor array substrate according to an embodiment of the present invention. [Fig. 4] (A) to (E) Flowchart of the manufacturing process of the thin film transistor array substrate of the first embodiment. [Fig. 5] Fig. 5 is a cross-sectional view showing the configuration of the gate terminal of the embodiment of the present invention

2185-8937-PF 23 200811565 Fig. 6 is a cross-sectional view showing the configuration of a gate terminal portion according to the first embodiment of the present invention. Fig. 7 is a cross-sectional view showing the configuration of another gate terminal portion according to the first embodiment of the present invention. Fig. 8 is a cross-sectional view showing the configuration of another source terminal portion according to the first embodiment of the present invention. Fig. 9 is a plan view showing the configuration of a thin film transistor array substrate according to a second embodiment of the present invention. Fig. 10 is a cross-sectional view showing the configuration of a thin film transistor array substrate according to a second embodiment of the present invention. Fig. 11 is a plan view showing the configuration of a conventional thin film transistor array substrate for a liquid crystal display device. [=12] A cross-sectional view showing the structure of a conventional thin film transistor array substrate. S 3 ] A cross-sectional view of a gate terminal portion of a thin film transistor array substrate for a liquid crystal display device. * 4 ] A cross-sectional view of the source terminal portion of the thin film transistor array substrate for a liquid crystal display device. [Description of main component symbols] 1 gate electrode, 2, auxiliary grid electrode, g gate insulating film, 4 semiconductor active film, 5 ohm contact film, 2185-8937-Pp 24 200811565 6 > and pole electrode, 7 Source electrode, 8 interlayer insulating film, 9 halogen contact hole, 10 part with auxiliary capacity 11 transparent conductive film, 11a halogen electrode, lib source electrode, 11c electrodeless electrode, 14 gate terminal pad, 18 source Extreme Substrate, 19 Conductive Film, 20 Supplemental Capacity Wiring, 21 Gate Wiring, 22 Source Wiring, 23 Semiconductor Layer, 24 Alizarin Contact Hole, 25 Alizarin Reflective Electrode, 26 TFT Channel Section, 27 Source Electrode Contact Hole, 28 source terminal pad pattern, 29 gate terminal pad pattern, 31 gate terminal contact hole, 32 source terminal contact hole, 25

2185-8937-PF 200811565 110 Substrate, 111 display area, 112 front edge area, 115 Wiggle signal drive circuit, 116 display signal drive circuit, 117 、, 118 external wiring, 119 external wiring,

120 TFT 26

2185-8937-PF

Claims (1)

200811565 X. Patent Application Scope 1 · A thin film transistor array substrate comprising: a gate electrode disposed on the substrate; a gate insulating film formed on the gate electrode; a semiconductor layer formed on the gate The insulating film is disposed opposite to the gate electrode; the source electrode and the drain electrode are composed of a transparent conductive film formed on the semiconductor layer; the halogen electrode extends from the drain electrode, and the transparent a conductive film composition; an interlayer insulating film formed on the halogen electrode, the source electrode, and the drain electrode, having a contact hole reaching the source electrode; and a source wiring formed on the interlayer insulating film And connected to the source electrode via the contact hole. 2. The thin film transistor array substrate as described in claim 5, wherein the source wiring comprises germanium, Ag or Cu. 3. The thin film transistor array substrate according to claim 2 or 2, wherein a 5" transparent conductive film is formed under the source wiring layer along a direction in which the source wiring is provided, and is formed in the The tantalum transparent conductive film under the source wiring is electrically connected to the source wiring. 4. The thin film transistor array substrate according to claim 2 or 2, wherein the gate wiring connected to the gate electrode is connected to the gate wiring via the gate terminal P and is connected to the source wiring. The conductive film is patterned by a conductive film, and the transparent conductive film is connected to the terminal pad pattern 2185-8937-PF 27 200811565 via the contact hole; the gate wiring and the transparent conductive film are connected The closed-electrode wiring connected to the closed-electrode electrode in the thin-film transistor array base according to the third aspect of the invention is connected to the terminal lining pattern: a lining pattern; a conductive film of the same layer of the original wiring The formed terminal is connected; the through-hole ¥f film is connected to the terminal pad pattern via the contact hole, and the inter-pole wiring is connected to the gg. The electric cymbal is connected to the terminal pad pattern and has a display device as described in the patent application scope! Or 2 of the thin film transistor array substrates described. , 斤 7. A display device having a thin film transistor array substrate as claimed in the patent application. , a method for manufacturing a thin film transistor array substrate, comprising: a step of forming a gate electrode on a substrate; a step of forming a gate insulating film on the gate electrode, · insulating the gate a step of forming a semiconductor layer on the opposite side of the gate electrode; forming a source electrode composed of a transparent conductive film, a drain electrode, and a pixel extending from the gate electrode a step of an electrode; a step of insulating the interlayer film, wherein the interlayer insulating film is formed on the ruthenium electrode, the source electrode, and the drain electrode, and I has reached the source of 2185-893 7-PF 28 200811565 a contact hole of the electrode; and a hole forming a source wiring electrically connected to the source via the contact electrode via the contact electrode. 9. The method of manufacturing a thin film transistor array substrate according to claim 8, wherein the source wiring comprises Al, Ag or Cu. The method for manufacturing a thin film transistor array earth plate according to the above aspect of the invention, wherein in the step of forming the source electrode, the drain electrode, and the pixel electrode, the source wiring is disposed along the source wiring The direction is below the source wiring; the shape; 曰I is the transparent conductive film, and the 4 transparent conductive film formed under the source wiring is electrically connected to the source wiring. 2185-893 7-PF 29