CN114326232A - Array substrate, manufacturing method thereof, display panel and display device - Google Patents
Array substrate, manufacturing method thereof, display panel and display device Download PDFInfo
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- CN114326232A CN114326232A CN202111646144.0A CN202111646144A CN114326232A CN 114326232 A CN114326232 A CN 114326232A CN 202111646144 A CN202111646144 A CN 202111646144A CN 114326232 A CN114326232 A CN 114326232A
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- 239000000758 substrate Substances 0.000 title claims abstract description 82
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 12
- 239000010409 thin film Substances 0.000 claims abstract description 35
- 239000000463 material Substances 0.000 claims abstract description 24
- 239000004065 semiconductor Substances 0.000 claims abstract description 13
- 238000000034 method Methods 0.000 claims description 14
- 238000005530 etching Methods 0.000 claims description 12
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052782 aluminium Inorganic materials 0.000 claims description 11
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 11
- 229910052802 copper Inorganic materials 0.000 claims description 11
- 239000010949 copper Substances 0.000 claims description 11
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 3
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910052738 indium Inorganic materials 0.000 claims description 3
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 3
- 229910052718 tin Inorganic materials 0.000 claims description 3
- 229910052725 zinc Inorganic materials 0.000 claims description 3
- 239000011701 zinc Substances 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 31
- 239000011241 protective layer Substances 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 239000010408 film Substances 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 238000005240 physical vapour deposition Methods 0.000 description 3
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 239000000956 alloy Substances 0.000 description 2
- 229910045601 alloy Inorganic materials 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 2
- 239000007769 metal material Substances 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910052814 silicon oxide Inorganic materials 0.000 description 2
- 239000012780 transparent material Substances 0.000 description 2
- YVTHLONGBIQYBO-UHFFFAOYSA-N zinc indium(3+) oxygen(2-) Chemical compound [O--].[Zn++].[In+3] YVTHLONGBIQYBO-UHFFFAOYSA-N 0.000 description 2
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 229910004205 SiNX Inorganic materials 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000005611 electricity Effects 0.000 description 1
- 239000011810 insulating material Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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Abstract
The application provides an array substrate, a manufacturing method thereof, a display panel and a display device; the array substrate includes: a substrate; the array substrate comprises a plurality of data lines and a plurality of scanning lines, wherein the data lines and the scanning lines are arranged on the substrate in a crossed manner, and two adjacent data lines and two adjacent scanning lines define a pixel region on the substrate; a pixel electrode disposed in the pixel region; a thin film transistor disposed in the pixel region; the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor layer and a source drain electrode; the gate electrode is arranged on the substrate, the gate insulating layer covers the gate electrode, the semiconductor layer is arranged on the gate insulating layer corresponding to the gate electrode, and the source electrode and the drain electrode are arranged on the semiconductor layer; the source and drain electrodes comprise a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected with the data line, and the other one of the source electrode and the drain electrode is electrically connected with the pixel electrode; and a channel is formed between the source electrode and the drain electrode, and the material of the source electrode and the drain electrode is the same as that of the pixel electrode.
Description
Technical Field
The application belongs to the technical field of display, and particularly relates to an array substrate, a manufacturing method of the array substrate, a display panel and a display device.
Background
Thin Film Transistors (TFT) are widely used in Liquid Crystal Displays (LCDs) and Active matrix organic electroluminescent displays (AMOLEDs), and therefore, the Thin Film transistors affect the development of the Display industry. In the related art, the channel width between the source and the drain of the thin film transistor affects the on-state current of the thin film transistor during operation, and the smaller the channel width is, the higher the on-state current is, so that the charging rate of the pixel electrode in the display panel can be improved. However, in the process of processing the source electrode and the drain electrode, the conduction requirements of the source electrode and the drain electrode cause that the channel cannot be effectively narrowed, and the charging rate of the pixel electrode in the display panel is reduced.
Disclosure of Invention
The embodiment of the application provides an array substrate, a manufacturing method thereof, a display panel and a display device, and aims to solve the problem that the charging rate of pixel electrodes of the existing display panel is low.
In a first aspect, an embodiment of the present application provides an array substrate, including:
a substrate;
the array substrate comprises a plurality of data lines and a plurality of scanning lines, wherein the data lines and the scanning lines are arranged on the substrate in a crossed manner, and two adjacent data lines and two adjacent scanning lines define a pixel region on the substrate;
the pixel electrode is arranged in the pixel area;
the thin film transistor is arranged in the pixel region; the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor layer and a source drain electrode; the gate electrode is arranged on the substrate, the gate insulating layer covers the gate electrode, the semiconductor layer is arranged on the gate insulating layer corresponding to the gate electrode, and the source electrode and the drain electrode are arranged on the semiconductor layer;
the source and drain electrodes comprise a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected with the data line, and the other one of the source electrode and the drain electrode is electrically connected with the pixel electrode; and a channel is formed between the source electrode and the drain electrode, and the material of the source electrode and the drain electrode is the same as that of the pixel electrode.
Optionally, the manufacturing material of the data line includes one or more of copper and aluminum.
Optionally, the source electrode is electrically connected to the data line, and the drain electrode and the pixel electrode are integrally formed; or, the drain electrode is electrically connected with the data line, and the source electrode and the pixel electrode are integrally formed.
Optionally, the source and drain electrodes and the pixel electrode are made of an oxide containing one or more of indium, tin, or zinc.
Optionally, the thickness of the source and drain electrodes is set to be 15nm to 150 nm.
In a second aspect, an embodiment of the present application further provides a display panel, where the display panel includes the array substrate according to any one of the above embodiments.
In a third aspect, embodiments of the present application further provide a display device, where the display device includes the display panel as described above.
In a fourth aspect, an embodiment of the present application further provides a method for manufacturing an array substrate, including:
providing a substrate;
arranging data lines and scanning lines which are mutually staggered on the substrate so that the data lines and the scanning lines define pixel regions;
a pixel electrode and a thin film transistor are arranged in the pixel region, one of a source electrode or a drain electrode of the thin film transistor is electrically connected with the data line, and the other one of the source electrode or the drain electrode of the thin film transistor is electrically connected with the pixel electrode; wherein the source electrode and the drain electrode are made of the same material as the pixel electrode.
Optionally, the step of disposing the data lines and the scan lines on the substrate, which are staggered with each other, includes:
the data line is made of a material including one or more of copper or aluminum.
Optionally, the step of disposing a pixel electrode and a thin film transistor in the pixel region includes:
etching the pixel electrode and the source electrode on the same transparent electrode; or, the pixel electrode and the drain electrode are etched on the same transparent electrode.
According to the array substrate provided by the embodiment of the application, the source and drain electrodes are made of the same material as the pixel electrode, so that the etching amount of the etching process to the channel part can be reduced when the source and drain electrodes are etched, the width of the channel can be shortened, the on-state current of the thin film transistor during operation can be improved, the charging rate of the pixel electrode can be improved, and the display effect of the display panel can be improved.
Drawings
In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings used in the description of the embodiments will be briefly described below. It is obvious that the drawings in the following description are only some embodiments of the application, and that other drawings can be derived from these drawings by a person skilled in the art without inventive effort.
For a more complete understanding of the present application and its advantages, reference is now made to the following descriptions taken in conjunction with the accompanying drawings. Wherein like reference numerals refer to like parts in the following description.
Fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure.
Fig. 2 is a schematic top view of an array substrate according to an embodiment of the present disclosure.
Fig. 3 is a schematic flow chart illustrating a manufacturing method of an array substrate according to an embodiment of the present disclosure.
Detailed Description
The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the drawings in the embodiments of the present application. It is to be understood that the embodiments described are only a few embodiments of the present application and not all embodiments. All other embodiments, which can be derived by a person skilled in the art from the embodiments given herein without making any creative effort, shall fall within the protection scope of the present application.
The embodiment of the application provides an array substrate, a display panel and a display device, and aims to solve the problem that the pixel charging rate of the existing display panel is low. Which will be described below with reference to the accompanying drawings.
The array substrate provided by the embodiment of the application can be applied to a display panel. The display panel comprises an array substrate, a color film substrate 10 and a liquid crystal layer, wherein the array substrate and the color film substrate 10 are arranged oppositely, and the liquid crystal layer is located between the array substrate and the color film substrate 10. The array substrate comprises a substrate 10, a thin film transistor 50 positioned on the substrate 10, a scanning line 30 and a data line 20; the scanning line 30 and the data line 20 intersect to define a pixel region, a thin film transistor 50 and a pixel electrode 40 electrically connected to the thin film transistor 50 are disposed in the pixel region, and the thin film transistor 50 is electrically connected to the scanning line 30 and the data line 20.
In order to more clearly illustrate the structure of the array substrate and the thin film transistor 50, the thin film transistor 50 and the array substrate will be described below with reference to the accompanying drawings.
For example, please refer to fig. 1 and fig. 2, fig. 1 is a schematic cross-sectional view of an array substrate according to an embodiment of the present disclosure; fig. 2 is a schematic top view of an array substrate according to an embodiment of the present disclosure. The array substrate includes a substrate 10, a data line 20, a scan line 30, a pixel electrode 40, and a thin film transistor 50. The number of the data lines 20 and the scan lines 30 is plural, the data lines 20 and the scan lines 30 are arranged on the substrate 10 in an intersecting manner, and two adjacent data lines 20 and two adjacent scan lines 30 define a pixel region on the substrate 10. The pixel electrode 40 and the thin film transistor 50 are disposed in the pixel region. The thin film transistor 50 includes a gate electrode 51, a gate insulating layer 52 layer, a semiconductor, and source and drain electrodes; the gate electrode 51 is provided on the substrate 10, the gate insulating layer 52 covers the gate electrode 51, the semiconductor layer 53 is provided on the gate insulating layer 52 corresponding to the gate electrode 51, and the source and drain electrodes are provided on the semiconductor layer 53. The source and drain electrodes include a source electrode 54 and a drain electrode 55, and one of the source electrode 54 and the drain electrode 55 is electrically connected to the data line 20 and the other is electrically connected to the pixel electrode 40. A channel 56 is formed between the source 54 and the drain 55, and the scan line 30 is electrically connected to the gate electrode 51.
When the voltage on the scan line 30 reaches the turn-on voltage, the source electrode 54 and the drain electrode 55 of the thin film transistor 50 are turned on, so that the data voltage on the data line 20 is input to the pixel electrode 40, and the pixel electrode 40 is charged to control the display of the corresponding pixel region. The charging rate of the pixel electrode 40 is related to the width of the channel 56, and the width of the channel 56, i.e., the distance between the source electrode 54 and the drain electrode 55, and the width of the channel 56 is about narrow, the higher the on-state current of the thin film transistor 50, the higher the charging rate of the pixel electrode 40.
The source and drain electrodes are typically formed by an etching process and have certain requirements on thickness. In the prior art, the source and drain are made of metal, and if the source and drain are etched to a predetermined thickness, the lateral dimension of the source and drain is also affected by the etching, which increases the width of the channel 56, thereby affecting the charging rate of the pixel electrode 40.
In the array substrate provided in the embodiment of the present application, the source and drain electrodes are made of the same material as the pixel electrode 40, so that when the source and drain electrodes are etched, the etching amount of the channel 56 in the etching process can be reduced, the width of the channel 56 can be shortened, the on-state current of the thin film transistor 50 during operation can be increased, the charging rate of the pixel electrode 40 can be increased, and the display effect of the display panel can be improved.
For example, the material of the source and drain electrodes and the pixel electrode 40 may be an oxide containing one or more of indium, tin, or zinc, such as indium tin oxide or indium zinc oxide. Indium tin oxide material is abbreviated as ITO, and indium zinc oxide is abbreviated as IZO. The ITO and the IZO are transparent materials, can play a role in conducting electricity, and can effectively realize the electric connection between the source electrode, the drain electrode, the pixel electrode 40 and data; and the influence on the lateral dimension can be reduced in the etching process. In addition, the ITO and IZO are used as transparent materials, so that the source and drain electrodes have a light transmission effect, and the aperture opening ratio of the display panel can be improved.
Illustratively, the source electrode 54 is electrically connected to the data line 20, and the drain electrode 55 is integrally formed with the pixel electrode 40; alternatively, the drain electrode 55 is electrically connected to the data line 20, and the source electrode 54 is integrally formed with the pixel electrode 40. The source electrode 54 is electrically connected to the data line 20, and the drain electrode 55 is integrally formed with the pixel electrode 40. A layer of ITO material or IZO material may be deposited on the gate insulating layer 52, the semiconductor layer 53 and the substrate 10 and then patterned by an etching process to simultaneously form the pixel electrode 40 and the drain electrode 55. Of course, in one embodiment, the source electrode 54 can also be obtained by patterning the same ITO layer or IZO layer. Therefore, the processing steps of the source and the drain can be reduced, and the processing efficiency of the source and the drain is improved.
Illustratively, the thickness of the source and drain electrodes is set to be 15nm to 150 nm. If the thickness of the source and drain electrodes is less than 15nm, the structural strength is weak, and the structural stability is poor; if the thickness of the source and drain electrodes is greater than 150nm, crystallization may occur during deposition, resulting in failure to perform patterning. Therefore, the thickness of the source and the drain is set to be 15nm to 150nm, so that the structural strength and the structural stability of the source and the drain can be guaranteed, and the processing stability of the source and the drain can be guaranteed.
Illustratively, the material of the data line 20 includes one or more of copper and aluminum. For example, the material of which the data line 20 is made may be copper, an alloy containing copper, aluminum, an alloy containing aluminum, or a multi-layer metal containing both copper and aluminum. The data line 20 is used to input a data voltage to the pixel electrode 40 through the source and drain electrodes, and the smaller the resistance of the data line 20, the faster the input rate of the data voltage, and the higher the charging rate of the pixel electrode 40. Therefore, when the data line 20 is made of a material including one or more of copper or aluminum, the charging rate of the pixel electrode 40 can be further increased.
For example, the array substrate provided in the embodiment of the present application further includes a protective layer 60 covering the source and drain electrodes, the protective layer 60 is provided with a through hole, and the data line 20 is electrically connected to the source 54 through the through hole. The protective layer 60 may be formed using SiNx or SiOx deposited by PECVD techniques. The protective layer 60 may serve to passivate and protect the channel 56, thereby preventing the channel 56 from being exposed to the external environment, and reducing the influence on the device characteristics. In addition, the protective layer 60 may also serve as an insulating layer to separate the data line 20 from the source/drain and the pixel electrode 40, so as to prevent unnecessary contact and conduction between the data line 20 and the source/drain or the pixel electrode 40, thereby ensuring the working stability of the array substrate.
By way of example, embodiments of the present application further provide a display device, including the display panel as described above. The display device can be any product or component with a display function, such as electronic paper, a mobile phone, a tablet personal computer, a television, a display, a notebook computer, a digital photo frame, a navigator and the like.
For example, referring to fig. 3, an embodiment of the present invention further provides a method for manufacturing an array substrate, including the following steps:
s10, providing a substrate 10.
S20, arranging the data lines 20 and the scan lines 30 on the substrate 10 to be interlaced with each other, such that the data lines 20 and the scan lines 30 define pixel regions.
S30, providing a pixel electrode 40 and a thin film transistor 50 in the pixel region, and electrically connecting one of a source 54 or a drain 55 of the thin film transistor 50 to the data line 20 and the other to the pixel electrode 40; wherein the source electrode 54 and the drain electrode 55 are made of the same material as the pixel electrode 40.
In step S10, the substrate 10 serves as both a substrate for the thin film transistor 50 and a substrate for the pixel electrode 40, and the substrate 10 may be a glass substrate 10 or a flexible substrate 10.
In step S30, a gate electrode 51 and a gate insulating layer 52 are first disposed on the substrate 10, specifically, a layer of metal is deposited on the substrate 10 by PVD (Physical Vapor Deposition) technique and patterned to form the gate electrode 51, in this embodiment, the metal material forming the gate electrode 51 is molybdenum, but other metal materials may be used in other embodiments; next, a layer of insulating material is deposited by using a PECVD (Plasma Enhanced Chemical Vapor Deposition) technique to form the gate insulating layer 52, the gate insulating layer 52 covers the gate electrode 51, that is, the gate electrode 51 is formed between the glass substrate 10 and the gate insulating layer 52, in this embodiment, the gate insulating layer 52 is made of silicon oxide, and in other embodiments, the gate insulating layer 52 may be made of silicon nitride or other materials capable of achieving the purpose of insulation.
Illustratively, the step of disposing the pixel electrode 40 and the thin film transistor 50 in the pixel region includes:
s31, etching the pixel electrode 40 and the source electrode 54 on the same transparent electrode; alternatively, the pixel electrode 40 and the drain electrode 55 are etched on the same transparent electrode.
In step S31, a layer of ITO or IZO material may be deposited on the pixel region and the gate insulating layer 52 by PVD technique, and then patterned to form the source electrode 54 and the pixel electrode 40, or to form the drain electrode 55 and the pixel electrode 40.
Illustratively, the step of disposing the data lines 20 and the scan lines 30 on the substrate 10 to be interlaced with each other includes: s21, forming the data line 20 from a material including one or more of copper or aluminum.
In step S21, the data line 20 may be formed by etching a copper material or an aluminum material.
In the foregoing embodiments, the descriptions of the respective embodiments have respective emphasis, and for parts that are not described in detail in a certain embodiment, reference may be made to related descriptions of other embodiments.
In the description of the present application, the terms "first", "second" are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implying any number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more features. The array substrate provided by the embodiments of the present application is described in detail above, and the principles and embodiments of the present application are explained herein by applying specific examples, and the description of the embodiments is only used to help understanding the method and the core concept of the present application; meanwhile, for those skilled in the art, according to the idea of the present application, there may be variations in the specific embodiments and the application scope, and in summary, the content of the present specification should not be construed as a limitation to the present application.
Claims (10)
1. An array substrate, comprising:
a substrate;
the array substrate comprises a plurality of data lines and a plurality of scanning lines, wherein the data lines and the scanning lines are arranged on the substrate in a crossed manner, and two adjacent data lines and two adjacent scanning lines define a pixel region on the substrate;
the pixel electrode is arranged in the pixel area;
the thin film transistor is arranged in the pixel region; the thin film transistor comprises a gate electrode, a gate insulating layer, a semiconductor layer and a source drain electrode; the gate electrode is arranged on the substrate, the gate insulating layer covers the gate electrode, the semiconductor layer is arranged on the gate insulating layer corresponding to the gate electrode, and the source electrode and the drain electrode are arranged on the semiconductor layer;
the source and drain electrodes comprise a source electrode and a drain electrode, one of the source electrode and the drain electrode is electrically connected with the data line, and the other one of the source electrode and the drain electrode is electrically connected with the pixel electrode; and a channel is formed between the source electrode and the drain electrode, and the material of the source electrode and the drain electrode is the same as that of the pixel electrode.
2. The array substrate of claim 1, wherein the data lines are made of a material comprising one or more of copper and aluminum.
3. The array substrate of claim 1 or 2, wherein the source electrode is electrically connected to the data line, and the drain electrode is integrally formed with the pixel electrode; or, the drain electrode is electrically connected with the data line, and the source electrode and the pixel electrode are integrally formed.
4. The array substrate of claim 1 or 2, wherein the source and drain electrodes and the pixel electrode are made of an oxide containing one or more of indium, tin, or zinc.
5. The array substrate according to claim 1 or 2, wherein the thickness of the source and drain electrodes is set to be 15nm to 150 nm.
6. A display panel comprising the array substrate according to any one of claims 1 to 5.
7. A display device characterized by comprising the display panel according to claim 6.
8. A method for manufacturing an array substrate includes:
providing a substrate;
arranging data lines and scanning lines which are mutually staggered on the substrate so that the data lines and the scanning lines define pixel regions;
a pixel electrode and a thin film transistor are arranged in the pixel region, one of a source electrode or a drain electrode of the thin film transistor is electrically connected with the data line, and the other one of the source electrode or the drain electrode of the thin film transistor is electrically connected with the pixel electrode; wherein the source electrode and the drain electrode are made of the same material as the pixel electrode.
9. The method of manufacturing an array substrate of claim 8, wherein the step of providing the data lines and the scan lines on the substrate to be staggered with each other comprises:
the data line is made of a material including one or more of copper or aluminum.
10. The method of manufacturing an array substrate according to claim 8, wherein the step of providing the pixel electrode and the thin film transistor in the pixel region comprises:
etching the pixel electrode and the source electrode on the same transparent electrode; or, the pixel electrode and the drain electrode are etched on the same transparent electrode.
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| CN102809859A (en) * | 2012-08-01 | 2012-12-05 | 深圳市华星光电技术有限公司 | Liquid crystal display device, array substrate and manufacture method thereof |
| CN103984170A (en) * | 2013-02-19 | 2014-08-13 | 上海天马微电子有限公司 | Array substrate, manufacturing method thereof and liquid crystal display |
| CN104282767A (en) * | 2013-07-05 | 2015-01-14 | 业鑫科技顾问股份有限公司 | Thin film transistor and manufacturing method thereof |
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| CN103474433A (en) * | 2013-09-09 | 2013-12-25 | 深圳莱宝高科技股份有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN203705779U (en) * | 2014-01-24 | 2014-07-09 | 京东方科技集团股份有限公司 | Array substrate and display device |
| CN104733477A (en) * | 2015-04-01 | 2015-06-24 | 上海天马微电子有限公司 | Array substrate, manufacturing method of array substrate, display panel and display device |
| CN105487285A (en) * | 2016-02-01 | 2016-04-13 | 深圳市华星光电技术有限公司 | Array substrate and preparing method of array substrate |
| CN106483726A (en) * | 2016-12-21 | 2017-03-08 | 昆山龙腾光电有限公司 | Thin-film transistor array base-plate and preparation method and display panels |
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