CN203465495U - Thin film transistor array substrate - Google Patents
Thin film transistor array substrate Download PDFInfo
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- CN203465495U CN203465495U CN201320566401.4U CN201320566401U CN203465495U CN 203465495 U CN203465495 U CN 203465495U CN 201320566401 U CN201320566401 U CN 201320566401U CN 203465495 U CN203465495 U CN 203465495U
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- film transistor
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Abstract
The utility model relates to the technical field of panel display, in particular to a thin film transistor array substrate. The thin film transistor array substrate comprises a substrate provided with a first surface as well as a plurality of scanning lines, a plurality of signal lines, a plurality of thin film transistors and a plurality of pixel electrodes which are formed in the first surface of the substrate, wherein each thin film transistor comprises a grid electrode, a source electrode and a drain electrode; the scanning lines and the grid electrodes of the plurality of thin film transistors are jointly manufactured by a first conducting layer through the same manufacture procedure; and the pixel electrodes and the source electrodes and the drain electrodes of the thin film transistors are jointly manufactured by a second conducting layer through the same manufacture procedure.
Description
Technical field
The utility model relates to technical field of flat panel display, relates in particular to a kind of thin-film transistor array base-plate.
Background technology
Thin Film Transistor-LCD (Thin Film Transistor Liquid Crystal Display, TFT-LCD) is a kind ofly to take liquid crystal as medium, the O-E Products that the thin film transistor (TFT) of take is control element.It mainly comprises colored filter, liquid crystal and thin-film transistor array base-plate.
Thin-film transistor array base-plate is as the critical elements of TFT-LCD, its manufacture craft mainly comprises base-plate cleaning, dry, composition, check reparation etc., wherein core process is composition technique, comprise coating, exposure, development, etching, peel off several basic links, composition technique all needs to carry out etching by different mask plates each time.
In recent years, the development of TFT-LCD technology is very fast, has experienced 7 times early stage compositions, has evolved to the great variety of 6 times, 5 times.And reduce composition number of times, and reduce the quantity of mask plate and the number of times of etching and be to improve yields, shorten fabrication cycle, reduce the place of the key of energy consumption, be also the power of TFT development.Therefore, be necessary to develop the thin-film transistor array base-plate that a kind of manufacture craft is simple, yields is high.
Utility model content
In view of this, the utility model provides the thin-film transistor array base-plate that a kind of manufacture craft is simple and yields is high.
The described thin-film transistor array base-plate that the utility model provides comprise have first surface substrate, be formed at multi-strip scanning line, many signal line, a plurality of thin film transistor (TFT) and a plurality of pixel electrode on the first surface of described substrate; Described in each, thin film transistor (TFT) comprises grid, source electrode, drain electrode, the grid of described sweep trace and a plurality of thin film transistor (TFT)s is made through same processing procedure in the lump by one first conductive layer, and the source electrode of described pixel electrode and thin film transistor (TFT), drain electrode are made through same processing procedure in the lump by one second conductive layer.
In the described thin-film transistor array base-plate that the utility model provides, described multi-strip scanning line and many signal line intersect on described surface mutually, and define a plurality of pixel regions, described a plurality of thin film transistor (TFT) is arranged at respectively in described a plurality of pixel region, and in each pixel region, be at least provided with a described thin film transistor (TFT), described in each, thin film transistor (TFT) is electrically connected with signal wire described in sweep trace described in one and respectively, described thin film transistor (TFT) also comprises gate insulation layer, active, restraining barrier, described grid is formed on the surface of described substrate, described gate insulation layer is formed on described grid, and cover described grid and sweep trace, on described active gate insulation layer that is arranged at described grid top, described restraining barrier is covered on described active, described restraining barrier has first in the position that covers described active, the second through hole, pixel electrode in the pixel region at described thin film transistor (TFT) place extends on the described restraining barrier of described active top, described pixel electrode extends to the drain electrode that the part of described active top is described thin film transistor (TFT), described drain electrode and described source electrode interval are formed on described restraining barrier, and respectively by described first, the second through hole and described active electric connection.
In the described thin-film transistor array base-plate that the utility model provides, described in each, the source electrode of pixel electrode and described thin film transistor (TFT), drain electrode are made by same transparent conductive material.
In the described thin-film transistor array base-plate that the utility model provides, also comprise many signal line, many described signal wires and the grid of thin film transistor (TFT), many described sweep traces are made in the lump through same processing procedure, and every described signal wire is divided into a plurality of subsignal lines by described sweep trace, is arranged in two described subsignal lines that same row are adjacent and passes through source series.
In the described thin-film transistor array base-plate that the utility model provides, the source electrode of many described signal wires and a plurality of pixel electrode, a plurality of described thin film transistor (TFT)s, drain electrode are made in the lump through same processing procedure.
In the described thin-film transistor array base-plate that the utility model provides, also comprise a plurality of sub-public electrodes, a plurality of described sub-public electrodes are arranged at respectively in described a plurality of pixel region, the grid of a plurality of described sub-public electrodes, a plurality of described thin film transistor (TFT)s, many described sweep traces and many described signal wires all complete in same composition technique, and a plurality of described sub-public electrodes are mutually connected and formed the public electrode of described thin-film transistor array base-plate.
In the described thin-film transistor array base-plate that the utility model provides, because pixel electrode, source electrode and drain electrode all complete in a composition technique, the manufacture craft of whole thin-film transistor array base-plate only needs composition technique 4 times, reduced the number of times of number and the etching of mask plate, therefore simplified the manufacture craft of thin-film transistor array base-plate, the yields having improved.
Accompanying drawing explanation
Below in conjunction with the drawings and the specific embodiments, the utility model is described in further detail, in accompanying drawing:
The schematic diagram of the thin-film transistor array base-plate that Fig. 1 provides for the utility model;
The making process flow diagram of the thin-film transistor array base-plate of the preferred embodiments that Fig. 2 A-2D provides for the utility model;
Fig. 3 is that thin film transistor (TFT) shown in Fig. 2 D is along the schematic cross-section of A-A direction;
Fig. 4 is that thin-film transistor array base-plate shown in Fig. 2 D is along the schematic cross-section of B-B direction;
The structural drawing of the thin-film transistor array base-plate of another preferred embodiments that Fig. 5 provides for the utility model.
Embodiment
Thin film transistor (TFT) for explanation the utility model provides, is described in detail below in conjunction with Figure of description and explanatory note.
Please refer to Fig. 1, the schematic diagram of the thin-film transistor array base-plate 100 of the preferred embodiments that it provides for the utility model.Described thin-film transistor array base-plate 100 comprise have first surface 101a substrate 101, be formed at multi-strip scanning line 103, many signal line 104, a plurality of thin film transistor (TFT) 130 and a plurality of pixel electrode 110 on the first surface 101a of substrate 101.Described substrate 101 is made as glass, resin for transparent material, and first surface 101a is continuous and smooth plane or a curved surface.
Between described multi-strip scanning line 103, be uniformly-spaced arranged in parallel, between described many signal line 104, be uniformly-spaced arranged in parallel, and mutually intersect on described first surface between described multi-strip scanning line 103 and many signal line 104, and define a plurality of pixel regions 200, described a plurality of thin film transistor (TFT) 130 is arranged at respectively in described a plurality of pixel region 200, and described in each, thin film transistor (TFT) 130 is electrically connected with one scan line 103 and signal wire 104 respectively, a plurality of pixel electrodes 110 are arranged at respectively in described a plurality of pixel region 200, and each pixel electrode 110 is electrically connected the described thin film transistor (TFT) 130 that is positioned at same pixel region 200.Described multi-strip scanning line 103 and many signal line 104 are made by metal or metal alloy, described pixel electrode 110 is made by transparent conductive material, and described transparent conductive material can be compound of indium tin oxide target (ITO), Zinc oxide/indium oxide zinc (IZO) or zinc-gallium oxide (GZO) or its composition etc.
In present embodiment, shown in thin-film transistor array base-plate 100 also comprise a plurality of sub-public electrode 112aa (not shown in figure 1)s, a plurality of described sub-public electrode 112a are arranged at respectively in described a plurality of pixel region 200, and a plurality of described sub-public electrode 112a that is positioned at same row mutually connects and forms the public electrode 112 of described thin-film transistor array base-plate 100.Described public electrode 112 is made by metal or metal alloy.In other embodiments, also can there is no public electrode, or public electrode arranges with other forms.
In present embodiment, every described signal wire of described thin-film transistor array base-plate 100 is cut into a plurality of subsignal line 104a by many described sweep traces 103, and a plurality of described subsignal line 104a series connection that is positioned at same row forms the signal wire 104 of described thin-film transistor array base-plate 100.
Described thin film transistor (TFT) 130 (referring to Fig. 3) comprises grid 102, gate insulation layer 105, active 106, restraining barrier 107 and source electrode 108, drains 109, and the pixel electrode 110 in the pixel region 200 that described drain electrode 109 is described thin film transistor (TFT) 130 places extends to the part on described active 106.
Please also refer to Fig. 2 A-2D, it is the making process flow diagram of a preferred embodiments of thin-film transistor array base-plate described in Fig. 1.In the present embodiment, only take and make a thin film transistor (TFT) and pixel region and describe as example, wherein Fig. 2 A is first composition schematic diagram, and Fig. 2 B is second composition schematic diagram, Fig. 2 C Wei tri-road composition schematic diagram, Fig. 2 D Wei tetra-road composition schematic diagram.
As shown in Figure 2 A, on the first surface 101a of substrate 101, form one first conductive layer, and form grid 102, sweep trace 103, sub-public electrode 112a and signal wire 104 through first composition technique,
Described grid 102 and the integrated pattern of described sweep trace 103, all grids 102 that are positioned at same row are all connected to same sweep trace 103, and described grid 132 and sweep trace adopt conductive material to make, and described conductive material is metal or metal alloy for example.The concrete making step that forms described grid 102 and sweep trace 103 through first composition technique is as follows: on described array base palte 101, through magnetron sputtering or other technique, form one first conductive layer, then on described the first conductive layer, coating forms one first photoresist layer, and through one first mask, described photoresist layer is carried out to photoetching, obtain the first photoetching agent pattern.Utilize described the first photoetching agent pattern to carry out etching to described the first conductive layer, obtain described grid 102, sweep trace 103, sub-public electrode 112a and the signal wire 104 of a plurality of thin film transistor (TFT)s 130.Described grid 102, sweep trace 103, sub-public electrode 112a and signal wire 104 are the pattern that the first conductive layer obtains after etching.
Further, at described grid 102, sweep trace 103, on sub-public electrode 112a and signal wire 104, utilize chemical vapor deposition (CVD) or additive method to form gate insulation layer 105 (not shown)s, described gate insulation layer 105 covers described grid 102 completely, sweep trace 103, sub-public electrode 112a and signal wire 104, and cover not by described grid 102, sweep trace 103, the first surface 101a that sub-public electrode 112a and signal wire 104 cover, in other embodiments, described gate insulation layer 105 is cover gate 102 only also, sweep trace 103, sub-public electrode 112a and signal wire 104.Described gate insulation layer 105 adopts transparent insulation materials to make as silicon nitride or monox.
As shown in Figure 2 B, on described gate insulation layer 105, adopt chemical vapor deposition (CVD) or additive method to form an active layer, through the second composition technique, make active 106, described active layer is made through depositing operation by oxide semiconductor material, in the present embodiment, described oxide semiconductor material is indium oxide gallium zinc (IGZO).The manufacture craft of making active 106 through the second composition technique specifically comprises: on described active layer, be coated with one second photoresist layer, and through the second mask, described the second photoresist layer carried out to photoetching, obtain the second photoetching agent pattern; Utilize described the second photoetching agent pattern to carry out etching to described active layer, obtain described active 106 of described thin film transistor (TFT) 130, described active 106 patterns that obtain after etching for described active layer.
Further, on described active 106, utilize chemical vapor deposition (CVD) or additive method to form restraining barrier 107 (not shown)s, described restraining barrier 107 adopts the transparent insulation material identical or not identical with described gate insulation layer 105 to make.
As shown in Figure 2 C, through San road composition technique, the position that covers described active 106 in it on described restraining barrier 107 forms the first through hole K1 and the second through hole K2, described San road composition technique specifically comprises, on described restraining barrier 107, be coated with one the 3rd photoresist layer, and through the 3rd mask, described the 3rd photoresist is carried out to photoetching, obtain the 3rd photoetching agent pattern; Utilize described the 3rd photoetching agent pattern in the position that covers described active 106, to carry out etching to described restraining barrier 107, obtain having the restraining barrier 107 of the first through hole K1 and the second through hole K2, described in described the first through hole K1 and the second through hole K2 exposed portions serve active 106.
In the present embodiment, through San road composition technique, also form respectively by the third through-hole K3 of each subsignal line 104 and each sub-public electrode 112a series connection, fourth hole K4.Described fourth hole K4 is positioned at each sub-public electrode 112a near one end of described subsignal line 104a, and described fourth hole K4 exposes the described sub-public electrode 112a of described part.Described third through-hole K3 is positioned at head end and the tail end of each subsignal line 104a, on the gate insulation layer 105 above two adjacent described subsignal line 104a and restraining barrier 107, be respectively formed with a third through-hole K3, the head end that the tail end of described subsignal line 104a in present embodiment is adjacent another subsignal line 104a connecing is scanned line 103 and separates, and described third through-hole K3 exposes the described subsignal line of described part 104a.
Further, on described restraining barrier 107, form one second conductive layer, described the second conductive layer at least covers described pixel region 200 and described sweep trace 103 and data line 104, and in other embodiments, described the second conductive layer also can not cover described sweep trace 103 and data line 104.Described the second conductive layer is made by transparent conductive material, and described transparent conductive material can be the compound of indium tin oxide target (ITO), Zinc oxide/indium oxide zinc (IZO) or zinc-gallium oxide (GZO) or its composition.
As shown in Figure 2 D, through Si road composition technique, on the second conductive layer, form a pixel electrode 110 and source electrode 109 simultaneously, its concrete steps comprise, on described the second conductive layer, be coated with one the 4th photoresist layer, and through the 4th mask, described the 4th photoresist is carried out to photoetching, obtain the 4th photoetching agent pattern; Utilize described the 4th photoetching agent pattern to carry out etching to described the second conductive layer, obtain described pixel electrode 110 and source electrode 108.In present embodiment, described pixel electrode 110 extends to the drain electrode 109 that the part of described active 106 tops is described thin film transistor (TFT), described drain electrode 109 is arranged at intervals on described active 106 with described source electrode 108, and described in each, the pixel electrode 110 in the source electrode 108 of thin film transistor (TFT) and the pixel region 200 at described thin film transistor (TFT) 130 places is made by same transparent conductive material.That is, by Si road composition technique, formed simultaneously thin-film transistor array base-plate 100 source electrode 108, drain 109 and pixel electrode 110, simplified composition technique, shortened fabrication cycle, improved yields.
In present embodiment, described source electrode 108 has also covered described third through-hole K3, be that two adjacent described third through-hole K3 are connected by source electrode 108, and many described subsignal line series connection that are positioned at same row formed to the signal wire 104 of described thin-film transistor array base-plate.
The position that in present embodiment, ， tetra-road composition techniques are also included in described fourth hole K4 forms a bridging structure 113, and described bridging structure 113 is made in same composition technique with described drain electrode 109 and pixel electrode 110.Described fourth hole K4 is connected sub-public electrode 112a described in adjacent each by bridging structure 113.
In addition, also can one passivation layer be set in described source electrode, drain electrode and channel region, play the effect of protection source electrode, drain electrode and channel region.
As shown in Figure 3, Figure 4, it is respectively thin-film transistor array base-plate described in Fig. 2 D along the sectional view of A-A' and B-B' direction.Wherein, Fig. 3 is also the structural representation of described thin film transistor (TFT) 130.In Fig. 4, shown in two sub-public electrode 112a by described bridging structure 113, be electrically connected, wherein, shown in the part on dotted line the right not shown in Fig. 2 D.
In the manufacturing process of above-mentioned thin-film transistor array base-plate, because source electrode, drain electrode and pixel electrode are all made in same composition technique, therefore reduced the number of times of number and the etching of mask plate, be that whole thin-film transistor array base-plate only needs composition technique 4 times, thereby shortened the fabrication cycle of thin-film transistor array base-plate, the yields having improved.
As shown in Figure 5, it is the structural drawing of the another kind of preferred embodiments of thin-film transistor array base-plate of the present utility model, one of difference of itself and aforementioned thin film transistor (TFT) is, described sub-public electrode 112b is a continuous integrated electrode, or the bridging structure (not shown) of connexon public electrode 112b is made in composition technique with grid, grid sweep trace; Two of difference is, described signal wire 204 is made in composition technique with source electrode, drain electrode and pixel electrode, in concrete tetra-road composition techniques, make, described signal wire 204 and described source electrode 108, drain 109 and pixel electrode 110 by same transparent conductive material, made.Other steps are identical with aforementioned embodiments.In present embodiment, without signal wire 204 and on form through hole, by described source electrode 108 and the integrated formation of described signal wire 204, simplified composition technique, and because described signal wire also has transparent conductive material, make, therefore, improved the aperture opening ratio of thin-film transistor array base-plate.
The preferred embodiments of the thin-film transistor array base-plate providing for the utility model above; can not be interpreted as the restriction to the utility model rights protection scope; those skilled in the art should know; without departing from the concept of the premise utility; also can do multiple improvement or replacement; these all improvement or replacement all should be within the scope of rights protections of the present utility model, and rights protection scope of the present utility model should be as the criterion with claim.
Claims (6)
1. a thin-film transistor array base-plate, comprise have first surface substrate, be formed at multi-strip scanning line, many signal line, a plurality of thin film transistor (TFT) and a plurality of pixel electrode on the first surface of described substrate; Described in each, thin film transistor (TFT) comprises grid, source electrode, drain electrode, the grid of described sweep trace and a plurality of thin film transistor (TFT)s is made through same processing procedure in the lump by one first conductive layer, and the source electrode of described pixel electrode and thin film transistor (TFT), drain electrode are made through same processing procedure in the lump by one second conductive layer.
2. thin-film transistor array base-plate as claimed in claim 1, it is characterized in that: described multi-strip scanning line and many signal line intersect on described surface mutually, and define a plurality of pixel regions, described a plurality of thin film transistor (TFT) is arranged at respectively in described a plurality of pixel region, and in each pixel region, be at least provided with a described thin film transistor (TFT), described in each, thin film transistor (TFT) is electrically connected with signal wire described in sweep trace described in one and respectively, described thin film transistor (TFT) also comprises gate insulation layer, active, restraining barrier, described grid is formed on the surface of described substrate, described gate insulation layer is formed on described grid, and cover described grid and sweep trace, on described active gate insulation layer that is arranged at described grid top, described restraining barrier is covered on described active, described restraining barrier has first in the position that covers described active, the second through hole, pixel electrode in the pixel region at described thin film transistor (TFT) place extends on the described restraining barrier of described active top, described pixel electrode extends to the drain electrode that the part of described active top is described thin film transistor (TFT), described drain electrode and described source electrode interval are formed on described restraining barrier, and respectively by described first, the second through hole and described active electric connection.
3. thin-film transistor array base-plate as claimed in claim 2, is characterized in that: described in each, the source electrode of pixel electrode and described thin film transistor (TFT), drain electrode are made by same transparent conductive material.
4. thin-film transistor array base-plate as claimed in claim 2, it is characterized in that: also comprise many signal line, many described signal wires and the grid of thin film transistor (TFT), many described sweep traces are made in the lump through same processing procedure, and every described signal wire is divided into a plurality of subsignal lines by described sweep trace, is arranged in two described subsignal lines that same row are adjacent and passes through source series.
5. thin-film transistor array base-plate as claimed in claim 2, is characterized in that: also comprise many signal line, the source electrode of many described signal wires and a plurality of pixel electrode, a plurality of described thin film transistor (TFT)s, drain electrode are made in the lump through same processing procedure.
6. thin-film transistor array base-plate as claimed in claim 2, it is characterized in that: also comprise a plurality of sub-public electrodes, a plurality of described sub-public electrodes are arranged at respectively in described a plurality of pixel region, the grid of a plurality of described sub-public electrodes, a plurality of described thin film transistor (TFT)s, many described sweep traces and many described signal wires all complete in same composition technique, and a plurality of described sub-public electrodes are mutually connected and formed the public electrode of described thin-film transistor array base-plate.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
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| CN201320566401.4U CN203465495U (en) | 2013-09-09 | 2013-09-09 | Thin film transistor array substrate |
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| Application Number | Priority Date | Filing Date | Title |
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| CN201320566401.4U CN203465495U (en) | 2013-09-09 | 2013-09-09 | Thin film transistor array substrate |
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| CN201320566401.4U Expired - Lifetime CN203465495U (en) | 2013-09-09 | 2013-09-09 | Thin film transistor array substrate |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474433A (en) * | 2013-09-09 | 2013-12-25 | 深圳莱宝高科技股份有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN114326232A (en) * | 2021-12-30 | 2022-04-12 | 广州华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
-
2013
- 2013-09-09 CN CN201320566401.4U patent/CN203465495U/en not_active Expired - Lifetime
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103474433A (en) * | 2013-09-09 | 2013-12-25 | 深圳莱宝高科技股份有限公司 | Thin film transistor array substrate and manufacturing method thereof |
| CN103474433B (en) * | 2013-09-09 | 2016-10-26 | 深圳莱宝高科技股份有限公司 | A kind of thin-film transistor array base-plate and preparation method thereof |
| CN114326232A (en) * | 2021-12-30 | 2022-04-12 | 广州华星光电半导体显示技术有限公司 | Array substrate, manufacturing method thereof, display panel and display device |
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