JP5685805B2 - SEMICONDUCTOR DEVICE, SEMICONDUCTOR DEVICE MANUFACTURING METHOD, AND ELECTRONIC DEVICE - Google Patents

Description

  The present invention relates to a semiconductor device, a semiconductor device manufacturing method, and an electronic apparatus.

  As a semiconductor device in which a thin film transistor (hereinafter also referred to as TFT) is formed on a substrate body, an element substrate used for an electro-optical device such as a liquid crystal device or an organic electroluminescence device (hereinafter also referred to as an organic EL device) An element substrate used for a solid-state imaging device using a light receiving element can be given. In such a semiconductor device (element substrate), a pixel transistor is constituted by a TFT. There is also electronic paper as a semiconductor device using TFT.

As a semiconductor layer constituting a TFT used in such a semiconductor device, for example, an amorphous silicon layer can be exemplified. However, the amorphous silicon layer has a carrier mobility of about 0.6 cm ² / V · sec, and other semiconductor layers. Since these TFTs are relatively low, for example, when a high-speed moving image signal such as a high-definition moving image is handled using this TFT, there is a problem that it is difficult to display following the image signal.

Therefore, in recent years, as disclosed in Patent Document 1, a metal oxide semiconductor layer such as an indium (In) -gallium (Ga) -zinc (Zn) oxide layer (IGZO layer) is used as a channel region of a TFT. Has been proposed. Although the IGZO layer depends on the manufacturing method, it has a conductivity of about 10 ⁻⁵ S / cm, and the operation as a TFT can be performed by controlling this conductivity. Since the IGZO layer has a mobility of about 10 cm ² / V · sec, which is 10 times or more that of amorphous silicon, a switching operation can be performed at a high speed. Further, since there is no grain boundary unlike polysilicon, it is possible to form a TFT with high uniformity.

  Here, it has been reported that a metal oxide semiconductor layer typified by an IGZO layer generates oxygen vacancies when exposed to argon plasma or the like (see Non-Patent Document 1). Therefore, when performing a plasma process, the method of performing a process in the state provided with the protective layer which covers an IGZO layer is mainly used.

  In addition, as described in Patent Document 2, a metal oxide conductor layer represented by indium-tin oxide (ITO) is another conductor layer unless conduction is achieved through a refractory metal such as titanium. The contact resistance between the two becomes high. Therefore, when the metal layer and the metal oxide conductor layer are electrically connected, a laminated structure of a metal such as aluminum that has easy processability and low electrical resistivity and titanium as a refractory metal is used. The structure used is used.

JP 2008-235871 A JP 61-13227 A

Applied Physics Letters 93, 203506 (2008)

When electrically connecting an IGZO layer and an ITO layer through a metal layer, as described above, a laminate of a metal such as aluminum having easy processability and low electrical resistivity and titanium as a refractory metal Although it is necessary to use a structure, when forming a laminated structure, it is necessary to form a plurality of metal layers. For this reason, there is a problem that the production process increases, the generation probability of particles and the like increases, and the yield decreases. In addition, since the conductivity of the IGZO layer is as low as about 10 ⁻⁵ S / cm as described above, it is difficult to use this layer as a wiring layer, and a conductor layer is formed in parallel in some form. The case of conducting is mainly known, but in this case as well, the manufacturing process becomes complicated, and there is a problem that an increase in the manufacturing process and a decrease in yield due to an increase in the manufacturing process occur.

  SUMMARY An advantage of some aspects of the invention is to solve at least a part of the problems described above, and the invention can be implemented as the following forms or application examples.

One of the semiconductor device according to the application example of the present invention includes an insulating layer having a first opening disposed on the substrate surface side, is provided between the substrate and the insulator layer, in a plan view, the A first metal oxide wiring layer having a second opening in a region overlapping with the first opening; and provided between the first metal oxide wiring layer and the insulator layer; a metal conductor layer in the area overlapping the aperture comprises a third opening of said sandwiching an insulator layer, Rutotomoni provided on the side opposite to the first metal oxide layer, said first aperture Part, the second opening, and a second metal oxide wiring layer provided on a side surface of the third opening, and a thin film transistor, and the first metal oxide wiring layer includes: A channel layer of the thin film transistor and a first wiring layer extending from the channel layer; The metal conductor layer is a second wiring layer extending from the electrode and the electrode of the thin film transistor, said second metal oxide film wiring layer, the first metal oxide film wires in said second opening The second metal oxide film wiring layer is electrically connected to the metal conductor layer in the third opening .
In the above semiconductor device, it is preferable that the first metal oxide wiring layer has a carrier density of the first wiring layer higher than a carrier density of the channel layer.
In the above semiconductor device, the first metal oxide layer is IGZO (indium-gallium-zinc oxide), indium-zinc oxide, or ZnO (zinc oxide), and the second metal oxide wiring layer is ITO (indium-tin oxide) is preferable.
One method of manufacturing a semiconductor device according to an application example of the present invention includes a step of forming a gate electrode on a substrate surface side, a step of forming a gate insulating layer on the gate electrode, and a step of forming on the gate insulating layer. A step of forming a first metal oxide wiring layer; a step of forming an etching protective layer on a part of the first metal oxide wiring layer and overlapping the gate electrode in a plane direction of the substrate; Forming a metal conductor layer on the first metal oxide wiring layer and the etching protection layer; etching the first metal oxide wiring layer and the metal conductor layer in a predetermined shape; A step of exposing the protective layer, a step of forming a protective layer on the substrate surface side, a step of opening the protective layer, exposing the first metal oxide wiring layer, and forming a first opening. The first metal oxide wiring Forming a second opening in the exposed region, and a second metal oxide wiring electrically connected to the first metal oxide wiring layer on the substrate surface side in the second opening Forming a layer.
In the manufacturing method of one semiconductor device described above, it is preferable to perform plasma treatment on the first metal oxide wiring layer between the step of forming the etching protective layer and the step of forming the metal conductor layer.
In the manufacturing method of one semiconductor device described above, the step of forming the first opening includes a step of forming a third opening in a region of the metal conductor layer that overlaps the first opening. ,
In the step of forming the second metal oxide wiring layer, it is preferable that the second metal oxide wiring layer and the metal conductor layer are electrically connected in the third opening.
[Application Example 1] A semiconductor device according to this application example includes an insulator layer disposed on a substrate surface side and having an opening, a metal oxide semiconductor layer and a first layer located on one surface side of the insulator layer. A first metal oxide layer also serving as a metal oxide wiring layer; and located on the other surface side of the insulator layer, separated from the first metal oxide layer by a separation region including the insulator layer; and And a second metal oxide wiring layer partially in close contact with the first metal oxide wiring layer through the opening.

  According to this, electrical conduction is achieved by bringing the second metal oxide wiring layer and the first metal oxide wiring layer into close contact with each other. When the second metal oxide wiring layer having conductivity is used for wiring and electrical connection with the metal layer is made, if contact is not made through a refractory metal layer such as titanium, the contact resistance is disclosed in Patent Document However, when the metal oxide wiring layers are brought into close contact with each other, the structures are similar to each other. It becomes possible to take conduction. Therefore, the structure can be simplified by using a structure in which the refractory metal layer is omitted. By reducing the number of components in this way, it is possible to provide a semiconductor device that is excellent in terms of reliability and cost.

  Application Example 2 In the semiconductor device according to the application example described above, the first metal oxide wiring layer includes a metal conductor layer electrically connected in parallel.

  According to the application example described above, by providing the metal conductor layers having low electric resistance in parallel, it is possible to reduce the equivalent electric resistance of the first metal oxide wiring layer, and the first metal oxide wiring layer can be further reduced. It can be used as a good wiring layer.

  Application Example 3 In the semiconductor device according to the application example described above, the first metal oxide wiring layer has a higher carrier density than the metal oxide semiconductor layer.

  According to the application example described above, the electrical resistance of the first metal oxide wiring layer is lower than that of the metal oxide semiconductor layer. Since the metal oxide semiconductor layer needs to have a function of modulating the conductivity, the carrier density is limited. However, the first metal oxide wiring layer has no such limitation. The electric resistance can be lowered. As a specific example, the carrier density can be increased and the electrical resistance can be decreased by intentionally forming oxygen vacancies functioning as donors in the first metal oxide wiring layer.

  Application Example 4 In the semiconductor device according to the application example described above, the first metal oxide wiring layer and the second metal oxide wiring layer are formed of the first metal oxide wiring layer connected to the opening. It is characterized by being in close contact with at least one of the first metal oxide wiring layer located on the side wall or the opening surface.

  According to the application example described above, it is possible to easily make electrical contact. In the case of close contact with the side wall of the first metal oxide wiring layer connected to the opening, it is technically difficult to dispose a refractory metal such as titanium on the side wall of the first metal oxide wiring layer. It is easy to bring a similar first metal oxide wiring layer and second metal oxide wiring layer into close contact with each other, and conduction can be achieved without sandwiching a refractory metal such as titanium. In addition, since the first metal oxide wiring layer located on the opening surface is in close contact using the area of the opening as it is, it is possible to conduct in a larger area than the side wall, and conduct with a lower electric resistance. It becomes possible to take.

  Application Example 5 In the semiconductor device according to the application example described above, the first metal oxide layer is IGZO (indium-gallium-zinc oxide), indium-zinc oxide, ZnO (zinc oxide), The second metal oxide wiring layer is made of ITO (indium-tin oxide).

  According to the application example described above, since substances having similar structures are brought into close contact with each other, it is possible to suppress contact resistance and achieve electrical conduction without using a refractory metal such as titanium.

  Application Example 6 A semiconductor device manufacturing method according to this application example includes a step of forming a gate electrode on the substrate surface side, a step of forming a gate insulating layer on the substrate surface side, and a step of forming the gate electrode on the substrate surface side. A step of forming a metal oxide layer serving as both a metal oxide semiconductor layer and a first metal oxide wiring layer, and an etching overlapping with the gate electrode in a planar direction of the substrate on a part of the surface of the metal oxide layer A step of forming a protective layer, a step of forming a protective layer on the substrate surface side, a step of opening the protective layer to form an opening exposing the first metal oxide wiring layer, and the substrate Forming a second metal oxide wiring layer in close contact with the first metal oxide wiring layer at the opening on the surface side.

  According to this, the second metal oxide wiring layer is formed on the exposed first metal oxide wiring layer. When the second metal oxide wiring layer is used to establish electrical continuity with the metal layer, contact resistance is increased as shown in Patent Document 2 unless continuity is established through a refractory metal such as titanium. However, when the metal oxide wiring layers are brought into close contact with each other, it is possible to establish electrical continuity without causing an increase in contact resistance simply by bringing them into close contact with each other because the structures are similar to each other. It becomes. Therefore, it is possible to use a metal having excellent workability such as AlNd (aluminum: neodymium alloy) for the metal layer without making the metal layer a refractory metal or a laminated structure.

  Application Example 7 A method of manufacturing a semiconductor device according to the application example, wherein after forming the etching protective layer and before forming the protective layer, forming a metal layer on the substrate surface side; Etching the metal layer and the metal oxide layer at a time in the surface direction of the substrate, removing the metal layer in a region overlapping the etching protection layer and leaving a source / drain region sandwiching the gate electrode. And further comprising.

  According to the application example described above, the number of photolithographic steps can be reduced. Etching at a time can complete the photolithographic process required twice. In addition, since the source / drain regions and the metal layer are formed in a self-aligned manner, etching without misalignment is possible.

  [Application Example 8] A method of manufacturing a semiconductor device according to the application example, wherein after the etching protective layer is formed and before the protective layer is formed, the substrate surface side is subjected to plasma treatment, And a step of forming the first metal oxide wiring layer having higher conductivity than the metal oxide semiconductor layer.

  According to the application example described above, the metal oxide semiconductor layer is covered with the etching protective layer, and the metal oxide layer is exposed to the plasma atmosphere with the first metal oxide wiring layer exposed. Since the metal oxide semiconductor layer is not exposed to the plasma atmosphere, the carrier density does not change and the property as a semiconductor layer capable of carrier density modulation by the electric field from the gate is maintained. On the other hand, when the first metal oxide wiring layer is exposed to the plasma atmosphere, the carrier density becomes high, and the electric resistance can be lowered as compared with the metal oxide semiconductor layer. Therefore, it is possible to suppress a voltage drop in the first metal oxide wiring layer.

  Application Example 9 An electronic apparatus according to this application example includes the semiconductor device described above or a semiconductor device manufactured by the method for manufacturing a semiconductor device described above.

  According to this, since this electronic device includes a semiconductor device using a simplified structure that omits the refractory metal layer, it is possible to provide an electronic device that is excellent in terms of reliability and cost. It becomes.

(A) is the top view which looked at the element substrate as a semiconductor device to which this invention was applied from the counter substrate side, (b) is H-H 'sectional drawing of (a). FIG. 6 is an equivalent circuit diagram illustrating an electrical configuration of an element substrate included in the liquid crystal device. (A) is a top view of the liquid crystal device containing the electro-optical device concerning 1st Embodiment, (b) is the sectional view on the A1-B1 line of (a). (A) is a top view of the liquid crystal device containing the electro-optical apparatus concerning 2nd Embodiment, (b) is the sectional view on the A1-B1 line of (a). (A), (b), (c) is process sectional drawing which shows the manufacturing method of the element substrate concerning 3rd Embodiment. (A), (b), (c) is process sectional drawing which shows the manufacturing method of the element substrate concerning 3rd Embodiment. (A), (b) is process sectional drawing which shows the manufacturing method of the element substrate concerning 4th Embodiment. (A) is a mobile personal computer equipped with an electro-optical device, (b) is a mobile phone equipped with the electro-optical device, and (c) is a configuration diagram of an information portable terminal to which the electro-optical device is applied.

(First embodiment: overall configuration of a liquid crystal device including an element substrate as a semiconductor device)
Hereinafter, embodiments embodying the present invention will be described with reference to the drawings. FIG. 1A is a plan view of a liquid crystal device provided with an element substrate as a semiconductor device to which the present invention is applied, as viewed from the side of a counter substrate together with each component formed thereon, and FIG. It is HH 'sectional drawing of a). Hereinafter, “upper” is defined as a direction from the element substrate 10 toward the counter substrate 20, and includes a case where components are not in direct contact with each other. “Lower” is defined as pointing in the opposite direction to “upper”, and includes cases where the components are not in direct contact. 1A and 1B, a liquid crystal device 100 of the present embodiment is driven in a TN (Twisted Nematic) mode, an ECB (Electrically Controlled Birefringence) mode, a VAN (Vertical Aligned Nematic) mode, or the like. This is an active matrix liquid crystal device. In the liquid crystal device 100, the element substrate 10 (semiconductor device) and the counter substrate 20 including the counter electrode 28, the alignment film 29, and the like are bonded to the element substrate 10 side of the counter substrate body 21 through the sealing material 22. In the meantime, the liquid crystal 1f is held. In the element substrate 10, the data line driving IC 60 and the scanning line driving IC 30 are mounted on the end region located outside the sealing material 22 and mounted along the side of the substrate. A terminal 12 is formed. The sealing material 22 is an adhesive using a photo-curing resin, a thermosetting resin, or the like for bonding the element substrate 10 and the counter substrate 20 around them, so that the distance between the two substrates is a predetermined value. Gap materials such as glass fiber or glass beads are blended. A liquid crystal injection port 25 is formed in the sealing material 22 by the discontinuous portion. After the liquid crystal 1f is injected, the sealing material 22 is sealed with a sealing material 26.

  On the element substrate 10, TFTs 1c and pixel electrodes 2a are formed in a matrix, and an alignment film 19 is formed on the surface thereof. On the counter substrate 20, a frame 24 (not shown in FIG. 1B) using a light-shielding material is formed in the inner region of the sealing material 22, and the inner side is an image display region 1 a. Although not shown in the figure, a light shielding film called a black matrix or black stripe is formed in a region facing the vertical and horizontal boundary regions of each pixel on the counter substrate 20. An alignment film 29 is formed. Although not shown in FIG. 1B, an RGB color filter is formed together with the protective film in a region of the counter substrate 20 facing each pixel of the element substrate 10, so that the liquid crystal device 100 is described above. Thus, it can be used as a color display device for electronic devices such as mobile computers, mobile phones, and liquid crystal televisions.

(Configuration of element substrate)
FIG. 2 is an equivalent circuit diagram showing an electrical configuration of an element substrate included in the liquid crystal device shown in FIG. As shown in FIG. 2, a plurality of source lines 6a (data lines) and gate lines 3a (scanning lines) are formed in the element substrate 10 in a direction corresponding to the image display area 1a in a direction intersecting with each other. A pixel 1b is formed at a position corresponding to the intersection of the wirings. The gate line 3a extends from the scanning line driving IC 30 and the source line 6a extends from the data line driving IC 60. In addition, a pixel switching TFT 1c for controlling driving of the liquid crystal 1f is formed in each pixel 1b on the element substrate 10, a source line 6a is electrically connected to the source of the TFT 1c, and a gate of the TFT 1c is connected to the gate. The gate line 3a is electrically connected.

  Furthermore, the capacitor substrate 3b is formed in the element substrate 10 in parallel with the gate line 3a. In this embodiment, a liquid crystal capacitor 1g configured between the TFT 1c and the counter substrate 20 is connected in series, and a holding capacitor 1h is connected in parallel to the liquid crystal capacitor 1g. Here, the capacitor line 3 b is held at a constant potential by being connected to the scanning line driving IC 30.

  In the liquid crystal device 100 configured as described above, the TFT 1c is turned on for a certain period, thereby writing an image signal supplied from the source line 6a into the liquid crystal capacitor 1g of each pixel 1b at a predetermined timing. An image signal of a predetermined level written in the liquid crystal capacitor 1g is held in the liquid crystal capacitor 1g for a certain period. Further, the liquid crystal capacitor 1g is provided with a holding capacitor 1h in parallel, and the fluctuation of the image signal held in the liquid crystal capacitor 1g due to leakage is suppressed.

(Configuration of each pixel: Configuration in which drain electrode and wiring layer are arranged in parallel)
Hereinafter, a configuration in which the drain electrode and the wiring layer are arranged in parallel will be described with reference to the drawings. 3A is a plan view of one pixel of the liquid crystal device including the electro-optical device according to the present embodiment, and FIG. 3B is a cross-sectional view when the liquid crystal device is cut at a position corresponding to A1-B1. It is. In FIG. 3A, the pixel electrode is indicated by a thick and long dotted line, the gate line and the thin film formed simultaneously with it are indicated by a thin solid line, the source line and the thin film formed simultaneously with it are indicated by a thin one-dot chain line, Is indicated by a thin and short dotted line. The contact hole is indicated by a thin solid line, like the gate line.

  As shown in FIG. 3A, in the element substrate 10, the following elements constituting the pixel 1b are configured in the pixel region 1e surrounded by the gate line 3a and the source line 6a. First, in the pixel region 1e, a metal oxide semiconductor layer 7c constituting an active layer included in the bottom gate type TFT 1c is formed. Here, description will be continued for the case where IGZO formed simultaneously is used as the material for the metal oxide semiconductor layer 7c and the wiring layer 7a as the first metal oxide wiring layer. When IGZO is used as a material, it is preferable to use a thickness of about 50 nm from the viewpoint of controllability, leakage current, and the like. Here, instead of IGZO, a substance such as IZO (registered trademark, indium-zinc oxide), ZnO (zinc oxide) or the like may be used, and Cd—Ge—O (cadmium-germanium oxide), Cd— A substance such as Pb-O (cadmium-lead oxide) may be used. . Here, a gate electrode is formed by a protruding portion from the gate line 3a. In the gate line 3a, for example, in the metal oxide semiconductor layer 7c, the source line 6a overlaps with the source side end, and the drain side end overlaps with the drain electrode 6b. A capacitor line 3b is formed in parallel with the gate line 3a. A metal oxide semiconductor layer 7c is disposed below the etching stop layer 8a (details will be described later) using silicon oxide or the like.

  Further, in the pixel region 1e, a protruding portion from the capacitor line 3b is a lower electrode 3c, and an extended portion having a laminated structure of a drain electrode 6b and a wiring layer 7a as a first metal oxide wiring layer is an upper electrode 6c. A holding capacitor 1h is formed. The source line 6a also has a structure overlapping the wiring layer 7a. The pixel electrode 2a using an ITO layer (Indium Tin Oxide) having a thickness of about 200 nm as the second metal oxide wiring layer is electrically connected to the upper electrode 6c through the contact hole 9a. Has been.

  An A1-B1 cross section of the element substrate 10 configured as described above is expressed as shown in FIG. First, on a glass substrate, a quartz substrate, or an insulating substrate 11 using a resin such as PET (polyethylene terephthalate) or acrylic, a material having conductivity such as a metal or a semiconductor exhibiting metallic conduction was used. A gate line 3a (gate electrode) and a capacitor line 3b (lower electrode 3c of the storage capacitor 1h) are formed. In the present embodiment, description of an example using a glass substrate is continued. As the gate line 3a and the capacitor line 3b, an aluminum alloy layer added with neodymium or an aluminum alloy layer added with copper having a thickness of about 150 nm can be used.

  In this embodiment, a gate using silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide or the like so as to cover the gate line 3a on the upper side of the gate line 3a An insulating layer 4 is formed. In the present embodiment, the gate insulating layer 4 is made of silicon oxynitride. Although the thickness depends on the operating voltage of the TFT 1c, for example, a thickness of about 200 nm can be exemplified.

  A metal oxide semiconductor layer 7c constituting an active layer of the TFT 1c is formed in a region of the upper layer of the gate insulating layer 4 that partially overlaps the protruding portion (gate electrode) of the gate line 3a. Of the metal oxide semiconductor layer 7c, a source line 6a (source electrode) is stacked on the upper layer of the source region, and a drain electrode 6b is formed on the upper layer of the drain region to constitute the TFT 1c. An upper electrode 6c is formed by the extended portion of the drain electrode 6b. The upper electrode 6c constitutes a storage capacitor 1h by facing the lower electrode 3c through a dielectric layer 4c using a part of the gate insulating layer 4. For the source line 6a and the drain electrode 6b (upper electrode 6c), for example, molybdenum having a thickness of 100 nm is used.

  On the upper layer side of the source line 6a, the drain electrode 6b, and the upper electrode 6c, an interlayer insulating layer 9 having a laminated structure of a protective layer 9c using silicon oxide or the like and a planarizing layer 9b using acrylic resin or the like is formed. The pixel electrode 2 a is formed on the interlayer insulating layer 9. The pixel electrode 2 a is electrically connected to the upper electrode 6 c and the wiring layer 7 a through a contact hole 9 a formed in the interlayer insulating layer 9. When a metal oxide such as ITO is brought into direct contact with the pixel electrode 2a and an aluminum alloy to which neodymium is added, the contact resistance may increase, but an IGZO layer is used for the wiring layer 7a, and the pixel electrode 2a When the second metal oxide wiring layer such as ITO is used, since the structures are similar to each other, it is possible to establish electrical conduction without causing an increase in contact resistance simply by bringing them into close contact.

  Here, the wiring layer 7a as the first metal oxide wiring layer and the pixel electrode 2a as the second metal oxide wiring layer using a metal oxide such as ITO are in contact with each other on the side surface of the contact hole 9a. However, in this state, the pixel electrode 2a and the wiring layer 7a may be brought into contact with the lower surface of the contact hole 9a with the wiring layer 7a remaining. In this case, since the pixel electrode 2a and the wiring layer 7a are in contact with each other over a wide area, a lower contact resistance can be obtained.

  The pixel electrode 2a is electrically connected to the drain region of the TFT 1c through the upper electrode 6c, the wiring layer 7a, and the drain electrode 6b. An alignment film 19 is formed on the surface of the pixel electrode 2a.

  The counter substrate 20 is disposed so as to face the element substrate 10 configured as described above, and the liquid crystal 1 f is held between the element substrate 10 and the counter substrate 20. The counter substrate 20 is provided with a color filter 27 for each color, a counter electrode 28, and an alignment film 29, and a liquid crystal capacitor 1g (see FIG. 2) is formed between the pixel electrode 2a and the counter electrode 28. Note that a black matrix, a protective film, or the like may be formed on the counter substrate 20 side, but these are not shown. Here, when IGZO is used for the metal oxide semiconductor layer 7c and the wiring layer 7a as the first metal oxide wiring layer, a structure in which the resistance of the wiring layer 7a portion is selectively reduced may be used. For example, when plasma irradiation is performed using the etching stop layer 8a using silicon oxide having a thickness of about 100 nm as a mask, carriers are generated by a donor estimated to be oxygen deficient. Therefore, the carrier density is increased, and the resistance of the wiring layer 7a can be selectively reduced. In this case, since the plasma irradiation is not performed on the lower side of the etching stop layer 8a, the carrier density in the region of the metal oxide semiconductor layer 7c is maintained as it is, and the properties as a semiconductor can be maintained.

Second Embodiment: Configuration of Each Pixel: Configuration Using Wiring Layer as Drain Electrode and Capacitance Electrode
Hereinafter, a configuration in which the wiring layer is used for the drain electrode and the capacitor electrode will be described with reference to the drawings. 4A is a plan view of one pixel of the liquid crystal device including the electro-optical device according to the present embodiment, and FIG. 4B is a view when the liquid crystal device is cut at a position corresponding to A1-B1 in FIG. FIG. Since this embodiment has many similarities to the above-described embodiment, the main differences will be described to avoid duplication.

The major difference is that the drain electrode 6b and the upper electrode 6c shown in FIG. 3 do not exist, and the wiring layer 7a as the first metal oxide wiring layer serves as the drain electrode 6b and the upper electrode 6c. In this case, it is preferable to increase the conductivity of the wiring layer 7a while maintaining the carrier density of the metal oxide semiconductor layer 7c. Specifically, plasma is generated in an atmosphere using hydrogen or ammonia while the element substrate 10 on which the etching stop layer 8a and the source line 6a are formed is heated to a temperature of about 150 ° C. or higher and 220 ° C. or lower. in the donor is generated suspected of oxygen deficiency, it improves the conductivity of the wiring layer 7a is, for example, it is possible to obtain a conductivity of about 10 ² S / cm. In this step, since the metal oxide semiconductor layer 7c in the region where the etching stop layer 8a is disposed is protected from plasma, for example, the conductivity of about 10 ⁻⁵ S / cm is maintained and the properties of the semiconductor are maintained. Is possible.

In FIG. 4B, the contact hole 9a is etched to a depth substantially coinciding with the surface of the wiring layer 7a. This is because after the planarization layer 9b is plasma etched, etching is continued, plasma etching is continued, for example, atmosphere analysis in plasma is performed, and components of In (indium) and Ga (gallium) are detected, This can be realized by using a method such as etching. In this case, it is also preferable to use a technique for improving the selection ratio between the protective layer 9c and the wiring layer 7a by adjusting the gas constituting the plasma and the excitation energy. As an example, CF ₄ , CF ₄ + H ₂ , CHF ₃ + Ar, SF ₆ + O ₂ -based gas is used as a gas constituting the plasma, and for example, conditions for etching at room temperature can be given. As described above, the wiring layer 7a and the pixel electrode 2a may be brought into contact with each other on the side surface of the contact hole 9a. In this case, a high process margin can be ensured.

(Third Embodiment: Manufacturing Method-1 of Element Substrate as Semiconductor Device Used for Liquid Crystal Device)
Next, a method for manufacturing an element substrate as a semiconductor device will be described with reference to the drawings.

  5A, 5B, 5C, 6A, 6B, and 6C are process cross-sectional views illustrating a method for manufacturing an element substrate used in the liquid crystal device of this embodiment. The element substrate manufacturing method will be described below with reference to the drawings. In addition, process sectional drawing has shown about the position corresponded to A1-B1 shown to Fig.3 (a).

  First, as step 1, as shown in FIG. 5A, a glass substrate, a quartz substrate, or a surface of an insulating substrate 11 using a resin such as PET (polyethylene terephthalate) or acrylic has a thickness of about 100 nm. An aluminum alloy film to which neodymium is added is formed. Then, a resist mask is formed using a photolithography technique, and a part of the metal film is etched, so that the gate line 3a (gate electrode) and the lower electrode 3c (capacitor line 3b) are formed simultaneously. Here, the description of the case where a glass substrate is used as the insulating substrate 11 will be continued. The insulating substrate 11 includes a substrate in which an insulating layer is formed so as to cover the conductor substrate. For example, a silicon substrate in which a silicon oxide layer is stacked is also applicable.

  Next, as step 2, as shown in FIG. 5B, using a plasma CVD method or a sputtering method, silicon oxide, silicon nitride, silicon oxynitride, silicon nitride oxide, hafnium oxide, zirconium oxide, aluminum oxide, yttrium oxide are used. A gate insulating layer 4 using, for example, is formed. In the present embodiment, the gate insulating layer 4 is made of silicon oxynitride. Although the thickness depends on the operating voltage of the TFT 1c, for example, a thickness of about 200 nm can be exemplified. A portion of the gate insulating layer 4 formed on the lower electrode 3c is used as the dielectric layer 4c.

Next, as step 3, as shown in FIG. 5C, a metal oxide layer 7 is formed on the gate insulating layer 4 by sputtering or the like mainly using argon gas. In this embodiment, an amorphous IGZO layer is formed as the metal oxide layer 7 as the metal oxide layer 7. In the sputtering process, an indium-gallium-zinc sintered body is used as a target, and the oxygen partial pressure at that time is adjusted. For example, as a sintered body used for sputtering film formation, a sintered body having a metal composition ratio of In: Ga: Zn = 1: 1: 1 is used, and the oxygen partial pressure in the sputtering gas is adjusted to adjust the metal oxide layer 7. By controlling the resistivity, an indium-gallium-zinc oxide (IGZO) layer having a conductivity of about 10 ⁻¹⁰ S / cm or more and 10 ⁻⁴ S / cm or less is formed. Here, the film thickness of the IGZO layer is, for example, about 50 nm. Instead of IGZO, a substance such as IZO (registered trademark, indium-zinc oxide), ZnO (zinc oxide), or the like may be used.

  Next, as step 4, an etching stop layer 8a is formed on the metal oxide layer 7 as shown in FIG. The etching stop layer 8a is formed using a plasma CVD method or a sputtering method with a silicon oxide layer having a thickness of about 100 nm. Here, when the plasma CVD method is used, the layer formation can be performed without affecting the carrier density of the metal oxide layer 7 by exposure to an oxygen plasma atmosphere before forming the silicon oxide layer. Then, a resist mask is formed using a photolithography technique, and a part of the silicon oxide layer is etched to form the etching stop layer 8a.

  Next, as step 5, as shown in FIG. 6B, a source line 6a and a drain electrode 6b (upper electrode 6c) are formed simultaneously. First, a molybdenum layer is formed by sputtering using argon. In this step, since the metal oxide layer 7 is exposed to a plasma atmosphere for performing sputtering except for the region covered with the etching stopper layer 8a, carriers are generated by a donor presumed to be oxygen deficient. Therefore, the carrier density is increased and the conductivity of the wiring layer 7a portion is selectively improved. After forming the molybdenum layer, the etching stop layer 8a is used as an etching stop layer, and the molybdenum layer and the metal oxide layer 7 are selectively etched at once by using a photolithographic technique, so that the source line 6a and A drain electrode 6b (upper electrode 6c) is formed. In the region overlapping with the source line 6a and the drain electrode 6b (upper electrode 6c), the metal oxide layer 7 remains as the wiring layer 7a as the first metal oxide wiring layer, and in the region overlapping with the etching stop layer 8a. It remains as the metal oxide semiconductor layer 7c.

  Next, as step 6, as shown in FIG. 6C, an interlayer having a laminated structure of a protective layer 9c using silicon oxide, silicon nitride oxide, or the like and a planarizing layer 9b using acrylic resin, polyimide resin, or the like. An insulating layer 9 is formed. In this embodiment, the protective layer 9c uses silicon oxide, and the planarizing layer 9b uses acrylic resin. Then, a contact hole 9a is opened using a photolithography technique. Subsequently, after forming an ITO layer as a second metal oxide wiring layer to a thickness of about 200 nm, a pixel mask 2a is formed by forming a resist mask using a photolithography technique and selectively etching the resist mask. Then, the element substrate 10 shown in FIG. 3 is formed by forming the alignment film 19. The pixel electrode 2 a is electrically connected to the upper electrode 6 c and the wiring layer 7 a through a contact hole 9 a formed in the interlayer insulating layer 9. When a metal oxide such as ITO is brought into direct contact with the pixel electrode 2a and an aluminum alloy to which neodymium is added, the contact resistance may increase, but an IGZO layer is used for the wiring layer 7a, and the pixel electrode 2a When the second metal oxide wiring layer such as ITO is used, since the structures are similar to each other, it is possible to establish electrical conduction without causing an increase in contact resistance simply by bringing them into close contact. In addition, when the contact hole 9a is formed, for example, an atmosphere analysis in plasma is performed, a component such as In (indium) or Ga (gallium) is detected, and etching is stopped to leave the wiring layer 7a. The pixel electrode 2a may be formed by forming an ITO layer as the second metal oxide wiring layer in a thickness of about 200 nm in a state, and then forming a resist mask using a photolithography technique and selectively etching the resist mask. good. By forming the pixel electrode 2a using the second metal oxide wiring layer such as ITO while leaving the wiring layer 7a, the contact area is increased and the contact resistance can be reduced.

(Fourth Embodiment: Method 2 for Manufacturing Element Substrate as Semiconductor Device Used for Liquid Crystal Device)
Next, another method for manufacturing an element substrate as a semiconductor device will be described with reference to the drawings. 7A and 7B are process cross-sectional views illustrating a method for manufacturing an element substrate used in the liquid crystal device of this embodiment. Since this embodiment has many similarities to the above-described embodiment, the main differences will be described to avoid duplication. Steps 1 to 4 are omitted because the same steps are used, and step 5 and subsequent steps will be described.

Here, as step 5, as shown in FIG. 7A, a source line 6a is formed. First, a molybdenum layer is formed by sputtering using argon. In this step, since the metal oxide layer 7 is exposed to a plasma atmosphere for performing sputtering except for the region covered with the etching stopper layer 8a, carriers are generated by a donor presumed to be oxygen deficient. Therefore, the carrier density is increased and the conductivity of the wiring layer 7a can be selectively improved. After forming the molybdenum layer, the etching stop layer 8a is used as an etching stop layer, and the molybdenum layer and the metal oxide layer 7 are selectively etched using a photolithography technique to form the source line 6a. . This step can be realized by plasma etching of the molybdenum layer, for example, by analyzing the atmosphere in the plasma, detecting components of In (indium) and Ga (gallium), and using a method such as aborting the etching. . In this case, it is also preferable to use a technique for improving the selectivity between the molybdenum layer and the wiring layer 7a by adjusting the gas constituting the plasma and the excitation energy. As an example, CF ₄ , CF ₄ + H ₂ , CHF ₃ + Ar, SF ₆ + O ₂ -based gas is used as a gas constituting the plasma, and for example, conditions for etching at room temperature can be given. Although the above-described plasma etching can also improve the conductivity of the wiring layer 7a, here, after the etching is completed, it is again exposed to plasma in a hydrogen or ammonia atmosphere to generate more donors that are assumed to be oxygen deficient. Therefore, it is also preferable to increase the conductivity of the wiring layer 7a.

  Next, as step 6, as shown in FIG. 7B, an interlayer having a laminated structure of a protective layer 9c using silicon oxide, silicon nitride oxide, or the like and a planarizing layer 9b using acrylic resin, polyimide resin, or the like. An insulating layer 9 is formed. In this embodiment, the protective layer 9c uses silicon oxide, and the planarizing layer 9b uses acrylic resin. Then, a contact hole 9a is opened using a photolithography technique. For example, the contact hole 9a is subjected to an atmosphere analysis in plasma, detects a component of In (indium) or Ga (gallium), and uses a method such as stopping etching to leave the wiring layer 7a. After the ITO layer as the second metal oxide wiring layer is formed to a thickness of about 200 nm, a pixel mask 2a is formed by forming a resist mask and selectively etching using a photolithography technique. Then, by forming the alignment film 19, the element substrate 10 shown in FIG. 4 is formed. By forming the pixel electrode 2a using the second metal oxide wiring layer such as ITO while leaving the wiring layer 7a, the contact area is increased and the contact resistance can be reduced. Here, when the pixel oxide 2a and the aluminum alloy to which neodymium is added are brought into direct contact with a metal oxide such as ITO, the contact resistance may increase, but an IGZO layer is used as the wiring layer 7a. When the second metal oxide wiring layer such as ITO is used for the electrode 2a, the structures are similar to each other, so that it is possible to establish electrical continuity without causing an increase in contact resistance simply by bringing them into close contact with each other. It becomes. The pixel electrode 2a may be formed after etching to penetrate the wiring layer 7a. In this case, since the influence on the contact resistance is reduced even if the etching depth accuracy is lowered, a high process margin is provided. Can be secured.

(Fifth embodiment: example of mounting on an electronic device)
Next, an electronic apparatus equipped with a liquid crystal device including an element substrate as the electro-optical device according to the above-described embodiment will be described. FIG. 8A illustrates a configuration of a mobile personal computer including a liquid crystal device. The personal computer 2000 includes a liquid crystal device 100 as a display unit and a main body 2010. The main body 2010 is provided with a power switch 2001 and a keyboard 2002. FIG. 8B illustrates a configuration of a mobile phone including a liquid crystal device. The cellular phone 3000 includes a plurality of operation buttons 3001, scroll buttons 3002, and the liquid crystal device 100 as a display unit. By operating the scroll button 3002, the screen displayed on the liquid crystal device 100 is scrolled. FIG. 8C shows a configuration of a personal digital assistant (PDA) to which the liquid crystal device is applied. The information portable terminal 4000 includes a plurality of operation buttons 4001, a power switch 4002, and the liquid crystal device 100 as a display unit. When the power switch 4002 is operated, various kinds of information such as an address book and a schedule book are displayed on the liquid crystal device 100.

  Electronic devices to which the liquid crystal device 100 is applied include those shown in FIG. 8, a digital still camera, a liquid crystal television, a viewfinder type, a monitor direct-view type Blu-ray player, a car navigation device, a pager, an electronic notebook, a calculator. , Word processors, workstations, videophones, POS terminals, devices with touch panels, and the like. And the liquid crystal device 100 mentioned above is applicable as a display part of these various electronic devices.

  DESCRIPTION OF SYMBOLS 1a ... Image display area, 1b ... Pixel, 1c ... TFT, 1e ... Pixel area, 1f ... Liquid crystal, 1g ... Liquid crystal capacity, 1h ... Holding capacity, 2a ... Pixel electrode, 3a ... Gate line, 3b ... Capacitance line, 3c ... Lower electrode, 4 ... Gate insulating layer, 4c ... Dielectric layer, 6a ... Source line, 6b ... Drain electrode, 6c ... Upper electrode, 7 ... Metal oxide layer, 7a ... Wiring layer, 7c ... Metal oxide semiconductor layer, 8a ... Etching stop layer, 9 ... Interlayer insulating layer, 9a ... Contact hole, 9b ... Flattening layer, 9c ... Protective layer, 10 ... Element substrate, 11 ... Insulating substrate, 12 ... Mounting terminal, 19 ... Alignment film, 20 ... Counter substrate 21, counter substrate body 22, sealing material, 24 frame, 25 liquid crystal injection port, 26 sealing material, 27 color filter, 28 counter electrode, 29 alignment film, 30 scanning line drive IC, 60... Data line driving IC, 1 DESCRIPTION OF SYMBOLS 0 ... Liquid crystal device, 2000 ... Personal computer, 2001 ... Power switch, 2002 ... Keyboard, 2010 ... Main part, 3000 ... Mobile phone, 3001 ... Operation button, 3002 ... Scroll button, 4000 ... Information portable terminal, 4001 ... Operation button, 4002: Power switch.

Claims (6)

An insulator layer disposed on the substrate surface side and having a first opening;
A first metal oxide wiring layer provided between the substrate and the insulator layer, and having a second opening in a region overlapping the first opening in plan view ;
A metal conductor layer provided between the first metal oxide wiring layer and the insulator layer and having a third opening in a region overlapping the first opening;
Across the insulator layer, said first metal oxide layer provided on the side facing the Rutotomoni, the first opening, the second opening, and a side surface of the third opening A second metal oxide wiring layer provided ;
A thin film transistor;
Including
The first metal oxide wiring layer is a channel layer of the thin film transistor and a first wiring layer extending from the channel layer,
The metal conductor layer is an electrode of the thin film transistor and a second wiring layer extending from the electrode,
The second metal oxide film wiring layer is electrically connected to the first metal oxide film wiring layer in the second opening ;
The second metal oxide film wiring layer is electrically connected to the metal conductor layer in the third opening . 2. The semiconductor device according to claim 1 , wherein the first metal oxide wiring layer has a carrier density of the first wiring layer higher than a carrier density of the channel layer. The semiconductor device according to any one of claims 1 or 2, wherein the first metal oxide layer is IGZO (indium - gallium - zinc oxide), indium - zinc oxide, ZnO (zinc oxide) , and the second metal oxide wiring layer, ITO - wherein a is (indium tin oxide). Forming a gate electrode on the substrate surface side;
Forming a gate insulating layer on the gate electrode;
Forming a first metal oxide wiring layer on the gate insulating layer;
Forming an etching protective layer on the first metal oxide wiring layer overlying the gate electrode in a planar direction of the substrate;
Forming a metal conductor layer on the first metal oxide wiring layer and on the etching protection layer;
Etching the first metal oxide wiring layer and the metal conductor layer into a predetermined shape to expose the etching protective layer ;
Forming a protective layer on the substrate surface side;
Opening the protective layer, exposing the first metal oxide wiring layer, and forming a first opening ;
Forming a second opening in an exposed region of the first metal oxide wiring layer;
Forming a second metal oxide wiring layer electrically connected to the first metal oxide wiring layer and the second opening on the substrate surface side;
A method for manufacturing a semiconductor device, comprising: 5. The method of manufacturing a semiconductor device according to claim 4 , wherein the first metal oxide wiring layer is subjected to plasma treatment between the step of forming the etching protective layer and the step of forming the metal conductor layer. A method for manufacturing a semiconductor device. A method of manufacturing a semiconductor device according to claim 4 or 5 ,
The step of forming the first opening includes a step of forming a third opening in a region overlapping the first opening in the metal conductor layer,
In the step of forming the second metal oxide wiring layer , the second metal oxide wiring layer and the metal conductor layer are electrically connected in the third opening. Device manufacturing method.

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