JP2008026433A - Tft array substrate and method of manufacturing the same, and display device using the same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a display device having excellent display quality and high productivity. <P>SOLUTION: A TFT array substrate has on a substrate 110, a gate electrode 1, a gate insulating film 3, a semiconductor layer 23, source and drain electrodes 11b and 11c composed of a transparent conductive film 11 and a pixel electrode 11a extended from the drain electrode 11c. An interlayer dielectric 8 having a source electrode contact hole 27 reaching the source electrode 11b and a source line 22 connected to the source electrode 11b through the source electrode contact hole 27 are formed on the transparent conductive film 11. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a TFT array substrate, a method for manufacturing the same, and a display device using the same.

  There are a simple matrix type liquid crystal display device and an active matrix type liquid crystal display device using a switching element as electro-optical elements for display using liquid crystals. In particular, an active matrix type liquid crystal display device uses a TFT-LCD, and has good portability and display quality, so that it is widely used in notebook personal computers and the like. In a TFT-LCD, a liquid crystal layer is generally sandwiched between a TFT array substrate (TFT: Thin Film Transistor) and a counter substrate. TFTs are formed in an array on the TFT array substrate. Polarizing plates are provided outside the TFT array substrate and the counter substrate, respectively. Further, a backlight is provided on one side. With such a structure, a good color display can be obtained.

  In order to reduce the manufacturing cost of the display device, reducing the manufacturing cost of the TFT array substrate is also a major issue. A technique for manufacturing a TFT array substrate with a smaller number of patterns has been considered. That is, a technique for simplifying the manufacturing process by reducing the number of photolithography processes has been considered (Patent Document 1).

  As a method for solving such a problem, Patent Document 1 discloses a method of manufacturing an active matrix liquid crystal display device in which a TFT array substrate is formed by five photolithography processes.

  A plan view of a conventional TFT substrate disclosed in Patent Document 1 is shown in FIG. 11, and cross-sectional views of main parts are shown in FIGS. 12 is a cross-sectional view taken along the line XX of FIG. 13 and 14 schematically show the cross-sectional structures of the TCP terminal portions provided outside the display area. TCP supplies a signal potential from a signal potential source of a common electrode of a gate wiring, a source wiring, an auxiliary capacitance wiring, and a counter substrate to a gate wiring, a source wiring, an auxiliary capacitance wiring, and a common electrode, respectively.

  A conventional TFT substrate includes a gate electrode 1 provided on a substrate 110, a gate insulating film 3 on the gate electrode 1, a semiconductor layer on the gate insulating film 3, and a source electrode 7 and a drain electrode 6 on the semiconductor layer. And an interlayer insulating film 8 having a pixel contact hole 9 formed so as to cover the source electrode 7 and the drain electrode 6 and reaching the drain electrode 6, and a transparent conductive film 11 on the interlayer insulating film 8.

  The gate electrode 1 is an electrode that is a part of the gate wiring 21 or is a terminal branched from the gate wiring 21 and connected to each TFT. In addition, a part of the auxiliary capacitance line 20 is arranged so as to overlap the transparent conductive film 11 to form an auxiliary capacitance.

  Patent Document 1 discloses a manufacturing method for manufacturing a TFT array substrate by five photolithography processes, and describes the effects thereof. Since the source wiring 22 and the source electrode 7 do not get over the step of the semiconductor layer 23 composed of the semiconductor active film 4 and the ohmic contact film 5 in the display portion, the source wiring 22 and the source electrode 7 of the semiconductor layer 23 are caused by the step. Disconnection can be eliminated. Further, there is a semiconductor layer 23 near the periphery of the transparent conductive film 11. However, the transparent conductive film 11 and the semiconductor layer 23, and the transparent conductive film 11 and the source wiring 22 are separated by the interlayer insulating film 8. Thereby, the pattern defect of the semiconductor layer 23 and the source wiring 22 can be eliminated. Therefore, it is possible to prevent the occurrence of a simple short circuit between the source wiring 22 and the transparent conductive film 11 or a short circuit when the resistance of the semiconductor active film 4 is reduced under light irradiation.

  However, in the TFT array substrate in Patent Document 1, when an Al film is used for the source wiring 22, there is a problem in that minute projections (hillocks) are generated on the surface of the Al film due to heating, resulting in an interlayer insulation failure. In addition, an oxide layer is formed between the source wiring 22 and the transparent conductive film 11, and there is a problem in that a contact resistance is increased at a connection portion between the source wiring 22 and the transparent conductive film 11 to cause a display defect.

  Further, when an Al film is used as a single layer for the metal thin film material of the source wiring 22, interdiffusion between Al and Si occurs at the connection portion between the source wiring 22 and the semiconductor layer 23 electrically connected, There is a problem that the contact resistance increases and display defects occur.

  Patent Document 2 discloses a method of forming a high melting point metal such as Cr or Mo on the upper layer of the Al film as a method for solving these problems. Thereby, an interlayer insulation failure due to hillocks and a contact failure between the transparent conductive film 11 can be prevented, and a refractory metal can be formed in the lower layer of the Al film to prevent a contact failure with the semiconductor layer 23.

  Patent Document 3 discloses that a source signal line, a source electrode, a drain electrode, and a transmissive pixel electrode are formed in the same layer. Thereby, contact failure can be prevented.

Japanese Patent Laid-Open No. 10-268353 JP 2000-284326 A JP 2000-258802 A

  However, in the case of Patent Document 2, two or more types of source wiring materials (high melting point metals such as Al, Cr, and Mo) are required, and the cost increases due to an increase in the number of manufacturing steps such as film formation and etching of the source wiring. . Furthermore, since the source wiring has a three-layer structure, there is a problem that it is difficult to control the cross-sectional shape after processing, leading to a decrease in yield.

  In the case of Patent Document 3, the source signal line, the source electrode, the drain electrode, and the transmissive pixel electrode are made of a transparent conductive film and a metal film. For this reason, two or more kinds of materials are required, and the cost increases due to an increase in the number of manufacturing steps such as film formation and etching. Further, since there is no interlayer insulating film between the source signal line and the transmissive pixel electrode, there is a problem that the source signal line and the transmissive pixel electrode are easily short-circuited, and the yield is reduced due to poor lighting.

  On the other hand, Patent Document 1 discloses that a conventional TFT array substrate uses an Ag film as a low-resistance wiring material for the metal thin film of the source wiring 22. However, Ag generally has low plasma resistance, and there is a problem that Ag in the contact hole disappears when the contact hole is formed.

  The present invention has been made to solve such an object, and an object of the present invention is to provide a display device with excellent display quality and high productivity.

  A TFT array substrate according to the present invention includes a gate electrode provided on the substrate, a gate insulating film formed on the gate electrode, and formed on the gate insulating film, and disposed on the opposite side of the gate electrode. A semiconductor layer, a source electrode and a drain electrode made of a transparent conductive film formed on the semiconductor layer, a pixel electrode extending from the drain electrode and made of the transparent conductive film, the pixel electrode, and the source An interlayer insulating film formed on the electrode and the drain electrode and having a contact hole reaching the source electrode; and a source wiring formed on the interlayer insulating film, and the source via the contact hole And the source wiring connected to the electrode.

  According to the present invention, a display device with excellent display quality and high productivity can be provided.

  Embodiments to which the present invention can be applied will be described below. The following description is about the embodiment of the present invention, and the present invention is not limited to the following embodiment.

Embodiment 1 FIG.
First, an active matrix display device to which the TFT array substrate according to the present invention is applied will be described with reference to FIG. FIG. 1 is a plan view showing a configuration of a TFT substrate used in a display device. The display device according to the present invention will be described using a liquid crystal display device as an example. However, the display device is illustrative only, and a flat display device (flat panel display) such as an organic EL display device can be used.

  The display device according to the present invention includes a substrate 110. The substrate 110 is, for example, a TFT array substrate. A frame region 112 is provided on the substrate 110 so as to surround the display region 111. In the display area 111, a plurality of gate lines (scanning signal lines) 21 and a plurality of source lines (display signal lines) 22 are formed. The plurality of gate wirings 21 are provided in parallel. Similarly, the plurality of source lines 22 are provided in parallel. The gate wiring 21 and the source wiring 22 are formed so as to cross each other. The gate wiring 21 and the source wiring 22 are orthogonal to each other. A region surrounded by the adjacent gate wiring 21 and source wiring 22 is a pixel 117. Accordingly, on the substrate 110, the pixels 117 are arranged in a matrix.

  Further, a scanning signal driving circuit 115 and a display signal driving circuit 116 are provided in the frame region 112 of the substrate 110. The gate line 21 extends from the display area 111 to the frame area 112. The gate wiring 21 is connected to the scanning signal driving circuit 115 at the end of the substrate 110. Similarly, the source line 22 extends from the display area 111 to the frame area 112. The source line 22 is connected to the display signal driving circuit 116 at the end of the substrate 110. In the vicinity of the scanning signal driving circuit 115, an external wiring 118 is connected. An external wiring 119 is connected in the vicinity of the display signal driving circuit 116. The external wirings 118 and 119 are wiring boards such as FPC (Flexible Printed Circuit).

  Various external signals are supplied to the scanning signal driving circuit 115 and the display signal driving circuit 116 via the external wirings 118 and 119. The scanning signal driving circuit 115 supplies a gate signal (scanning signal) to the gate wiring 21 based on a control signal from the outside. The gate wiring 21 is sequentially selected by this gate signal. The display signal driving circuit 116 supplies a display signal to the source line 22 based on an external control signal and display data. Thereby, a display voltage corresponding to the display data can be supplied to each pixel 117.

  At least one TFT 120 is formed in the pixel 117. The TFT 120 is disposed in the vicinity of the intersection of the source line 22 and the gate line 21. For example, the TFT 120 supplies a display voltage to the pixel electrode. That is, the TFT 120 which is a switching element is turned on by the gate signal from the gate wiring 21. Thereby, a display voltage is applied from the source line 22 to the pixel electrode connected to the drain electrode of the TFT. An electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode. Note that an alignment film (not shown) is formed on the surface of the substrate 110.

  Further, a counter substrate is disposed opposite to the substrate 110. The counter substrate is, for example, a color filter substrate, and is disposed on the viewing side. On the counter substrate, a color filter, a black matrix (BM), a counter electrode, an alignment film, and the like are formed. Note that the counter electrode may be disposed on the substrate 110 side. A liquid crystal layer is sandwiched between the substrate 110 and the counter substrate. That is, liquid crystal is injected between the substrate 110 and the counter substrate. Further, a polarizing plate, a retardation plate, and the like are provided on the outer surfaces of the substrate 110 and the counter substrate. A backlight unit or the like is disposed on the non-viewing side of the liquid crystal display panel.

  The liquid crystal is driven by the electric field between the pixel electrode and the counter electrode. That is, the alignment direction of the liquid crystal between the substrates changes. As a result, the polarization state of the light passing through the liquid crystal layer changes. That is, the polarization state of light that has been linearly polarized after passing through the polarizing plate is changed by the liquid crystal layer. Specifically, the light from the backlight unit becomes linearly polarized light by the polarizing plate on the array substrate side. Then, the polarization state changes as this linearly polarized light passes through the liquid crystal layer.

  Therefore, the amount of light passing through the polarizing plate on the counter substrate side changes depending on the polarization state. That is, the amount of light that passes through the polarizing plate on the viewing side among the transmitted light that passes through the liquid crystal display panel from the backlight unit changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel.

  Next, the structure of the TFT 120 on the substrate 110 will be described with reference to FIGS. FIG. 2 is a plan view showing the configuration of the TFT array substrate according to the first exemplary embodiment of the present invention. 3 is a cross-sectional view of the XX portion of the TFT array substrate in FIG.

  A plurality of gate wirings 21 are provided on the substrate 110 in parallel. Further, the source wiring 22 is also provided in parallel. The gate wiring 21 and the source wiring 22 are formed so as to cross each other. The gate wiring 21 and the source wiring 22 are orthogonal to each other. A pixel electrode 11 a is formed in a region surrounded by the adjacent gate line 21 and source line 22.

  The gate wiring 21 is connected to the gate electrode 1. A storage capacitor line 20 is arranged between the adjacent gate lines 21. The auxiliary capacitance line 20 is formed in parallel with the gate line 21. The auxiliary capacitance line 20 overlaps with the pixel electrode 11a. Thereby, an auxiliary capacitor is formed. A TFT 120 serving as a switching element is formed in the vicinity of the intersection of the gate line 21 and the source line 22. The TFT 120 has a semiconductor layer 23 composed of the semiconductor active film 4 and the ohmic contact film 5. The semiconductor layer 23 is formed on the gate electrode 1. A drain electrode 11c and a source electrode 11b are formed on the semiconductor layer 23. An interlayer insulating film 8 is formed on the source electrode 11b and the drain electrode 11c. A source wiring 22 is formed on the interlayer insulating film 8. A source electrode contact hole 27 reaching the source electrode 11b is formed in the interlayer insulating film 8. The source electrode 11 b and the source wiring 22 are electrically connected through the source electrode contact hole 27. Further, the pixel electrode 11a extends from the drain electrode 11c. That is, the drain electrode 11c and the pixel electrode 11a are integrally formed.

  Next, a manufacturing method of the TFT 120 will be described with reference to FIGS. FIG. 4 is a manufacturing process diagram for this embodiment. In the present embodiment, the TFT array substrate is manufactured by five photolithography processes.

(A) First photolithography process First, a substrate 110 such as a glass substrate is cleaned with pure water (a). In this case, you may wash | clean using a hot sulfuric acid instead of a pure water. Then, a first metal thin film for forming the gate electrode 1, the gate wiring 21, and the auxiliary capacitance wiring 20 is formed on the substrate 110 (b). In order to pattern the first metal thin film, the first photolithography is performed (c). Specifically, a resist pattern is formed by applying, exposing, and developing a resist. As the first metal thin film, it is preferable to use Al, Mo, Cr having low electrical specific resistance, or an alloy containing these as a main component. In this embodiment, an AlNd alloy in which 0.2 mol% of Nd is added to Al can be used. For example, the AlNd film having a thickness of 200 nm can be formed by a DC magnetron sputtering method using a known Ar gas. Thereafter, the AlNd film is wet etched using a known solution containing phosphoric acid + nitric acid (d). Then, the resist pattern is peeled off and washed with pure water (e). As a result, the gate electrode 1, the gate wiring 21, and the auxiliary capacitance wiring 20 are formed.

(B) Second Photolithographic Process Next, a first insulating film made of silicon nitride (SiN), a semiconductor active film 4 made of amorphous silicon, and an ohmic contact film 5 made of n + amorphous silicon doped with impurities are formed. Films are sequentially formed (f). In order to pattern the semiconductor active film 4 and the ohmic contact film 5, a second photolithography is performed (g). At this time, it includes a portion for forming a thin film transistor, and is formed in a larger and continuous shape than the pattern of the source wiring 22 and the drain electrode 11c formed by a process described later. In this embodiment, a chemical vapor deposition (CVD) method is used, the SiN film is 400 nm as the first insulating film, the amorphous silicon film is 150 nm as the semiconductor active film 4, and the phosphorus (P N + amorphous silicon film doped with) as an impurity is sequentially formed with a thickness of 30 nm. Thereafter, the semiconductor active film 4 and the ohmic contact film 5 are etched by a dry etching method using a known fluorine-based gas (h). Thereafter, the resist pattern is peeled off and washed with pure water (i). Thereby, a semiconductor layer 23 composed of the semiconductor active film 4 and the ohmic contact film 5 is formed as a semiconductor pattern. Further, the first insulating film becomes the gate insulating film 3. In this case, the impurity may be added after film formation.

(C) Third photolithography process Next, a transparent conductive film 11 is formed (j). In order to pattern the transparent conductive film 11, a third photoengraving is performed (k). A drain electrode 11c, a pixel electrode 11a, and a source electrode 11b are formed. Further, in this step, a gate terminal pad for supplying a signal to the gate wiring 21 and a source terminal pad for supplying a signal to the source wiring 22 are formed at the same time. In this embodiment, an ITO film in which indium oxide (In ₂ O ₃ ) and tin oxide (SnO ₂ ) are mixed is used as the transparent conductive film 11. The transparent conductive film 11 is formed to a thickness of 100 nm by a sputtering method using a known Ar gas. Then, wet etching is performed using a known solution containing hydrochloric acid + nitric acid (l). Thereby, the drain electrode 11c, the pixel electrode 11a, the source electrode 11b, the gate terminal pad, and the source terminal pad are formed. The configuration of the gate terminal pad and the source terminal pad will be described later. Further, the ohmic contact film 5 between the source electrode 11b and the drain electrode 11c is dry-etched using a known fluorine-based gas (m). Subsequently, the resist pattern is peeled off and washed with pure water (n). Thereby, the source electrode 11b, the drain electrode 11c, the pixel electrode 11a, the TFT channel portion 26, the gate terminal pad, and the source terminal pad are formed.

  In the above description, the transparent conductive film 11 is an ITO film. In this case, an amorphous ITO film can also be used. The transparent conductive film 11 may be an indium oxide film, a tin oxide film, or a zinc oxide film. Further, an IZO film in which indium oxide and zinc oxide are mixed, or an ITZO film in which indium oxide, tin oxide, and zinc oxide are mixed may be used. These transparent conductive films 11 can be etched with oxalic acid, which is a weak acid. Therefore, when the transparent conductive film 11 is etched, other wirings and electrodes are not corroded, so that the yield can be improved.

(D) Fourth Photolithographic Process Next, in order to form the interlayer insulating film 8, a second insulating film made of SiN is formed (o). In this embodiment mode, a silicon nitride SiN film is formed as a second insulating film with a thickness of 300 nm by using a chemical vapor deposition (CVD) method (o). Then, the fourth photoengraving is performed (p). Thereafter, dry etching is performed using a known fluorine-based gas (q). At this time, a source electrode contact hole 27 penetrating to the surface of the source electrode 11b is formed in the second insulating film. Thereafter, the resist pattern is peeled off and washed with pure water (r). Thereby, the interlayer insulating film 8 having the source electrode contact hole 27 is formed.

(E) Fifth photolithography process Next, a second metal thin film is formed (s). As the second metal thin film, Al or an Al alloy is preferable. Cr or Cr alloy, Mo or Mo alloy may be used. In this embodiment, an AlNi alloy in which 2 mol% of Ni is added to Al is formed to a thickness of 200 nm by a sputtering method using a known Ar gas.

  Subsequently, in order to pattern the second metal thin film, the fifth photolithography is performed (t). Then, wet etching is performed using a known solution containing phosphoric acid + nitric acid (u). Thereafter, the resist pattern is peeled off, and the second metal thin film is patterned. (V)

  Thereby, the conductive film 19 in the same layer as the source wiring 22 to which the source electrode 11b is electrically connected through the source electrode contact hole 27 is formed. That is, the conductive film 19 is formed by the second metal thin film. Further, the source terminal pad pattern 28 and the gate terminal pad pattern 29 are formed by the fifth photolithography process (E). Specifically, as shown in FIG. 5, a gate terminal pad pattern 29 connected to the gate wiring 21 through the gate terminal contact hole is formed by the conductive film 19. FIG. 5 is a cross-sectional view showing a configuration of a gate terminal portion for inputting a signal to the gate wiring 21. Further, as shown in FIG. 6, a source terminal pad pattern 28 connected to the source terminal pad 18 through the source terminal portion contact hole is formed by the conductive film 19. The source terminal pad pattern 28 extends from the source wiring 22. FIG. 6 is a cross-sectional view illustrating a configuration of a source terminal portion for inputting a signal to the source wiring 22. The gate terminal portion and the source terminal portion are disposed in the frame region 112.

  The gate terminal pad pattern 29 is connected to the gate terminal pad 14 made of the transparent conductive film 11 through a contact hole provided in the interlayer insulating film 8. Further, the gate terminal pad pattern 29 is connected to the gate wiring 21 through a gate terminal portion contact hole provided in the interlayer insulating film 8 and the gate insulating film 3. Therefore, the gate wiring 21 and the gate terminal pad 14 are electrically connected via the gate terminal pad pattern 29. Further, the source terminal pad pattern 28 is connected to the source terminal pad 18 through the source terminal portion contact hole provided in the interlayer insulating film 8. In this case, a gate signal and a source signal are respectively supplied to the gate wiring 21 and the source wiring 22 through a terminal pad made of the transparent conductive film 11. Note that each contact hole provided in the gate terminal portion and the source terminal portion is formed in the fourth photolithography process (D).

  Conventionally, when using an Al film or an Al alloy film for the source wiring, source electrode, and drain electrode, it has been necessary to use a refractory metal such as Cr or Mo for the lower layer and the upper layer of the Al film or Al alloy film, respectively. . Thereby, mutual diffusion between Al of the Al film and Si of the ohmic contact film was prevented, and good contact characteristics could be obtained. However, as described above, it is necessary to laminate an Al film or an Al alloy film, and there is a problem that the number of manufacturing steps increases.

  According to the present invention, the source electrode 11b and the drain electrode 11c are formed of the transparent conductive film 11 (for example, ITO film) used for the pixel electrode 11a. Therefore, the transparent conductive film 11 is sandwiched between the ohmic contact film 5 and the source wiring 22 made of AlNi. As a result, it is possible to prevent deterioration of electrical contact characteristics due to interdiffusion between Al and Si without laminating the Al film, that is, without increasing the number of manufacturing steps by laminating as described above.

Conventionally, since the Al or Al alloy film (lower layer) and the ITO film (upper layer) are directly laminated in this order, the formation of AlO _X at the contact portion has been a problem. In the present invention, the ITO film is the lower layer and the Al or Al alloy is the upper layer. For this reason, the electrical contact characteristics between Al and ITO can be greatly improved.

  On the other hand, when an ITO film (or IZO film, ITZO film, etc.) and an Al film or an Al alloy film are in electrical contact, there is a concern about ITO reductive corrosion in an alkaline developer. Therefore, an Al alloy containing one or more metals of Group 8 elements (Ni, Co, Fe, etc.) of the periodic table, an Al film or Al alloy film containing nitrogen (N), and Group 8 of the periodic table It is preferable to use an Al alloy film in which nitrogen is added to an Al alloy containing at least one elemental metal. As a result, this problem can be solved and a high yield TFT array substrate can be provided.

  In the present embodiment, the interlayer insulating film 8 is provided between the source wiring 22 and the transparent conductive film 11 such as the pixel electrode 11a. Thereby, for example, when the source electrode, the drain electrode, and the source wiring as disclosed in Patent Document 3 are formed in the same layer as the pixel electrode, the electrical connection between the source wiring 22 and the transparent conductive film 11 becomes a problem. It is possible to improve short circuit and lighting failure.

  The above description describes that the gate terminal pad pattern 29 is formed by the transparent conductive film 11. However, when the transparent conductive film 11 is not necessary, the gate terminal pad 14 can be formed simultaneously with the first metal thin film as shown in FIG. Further, as shown in FIG. 8, the source terminal pad 18 can be formed by the conductive film 19 in the same layer as the source wiring 22.

Embodiment 2. FIG.
Next, the configuration of the TFT array substrate for a display device according to the second embodiment of the present invention will be described with reference to FIGS. FIG. 9 shows a TFT array substrate for a liquid crystal display device according to the second embodiment. 10 is a cross-sectional view taken along a line XX in FIG.

  In the present embodiment, in addition to the configuration shown in the first embodiment, a pixel reflection electrode 25 is provided. Since the configuration other than the pixel reflection electrode 25 is the same as that of the first embodiment, the description thereof is omitted. The differences in configuration are described below.

  First, the interlayer insulating film 8 having the source electrode contact hole 27 and the pixel contact hole 24 is laminated so as to cover the transparent conductive film 11. A source line 22 and a pixel reflection electrode 25 are provided on the interlayer insulating film 8. The pixel electrode 11 a is connected to the pixel reflection electrode 25 through the pixel contact hole 24.

  As described above, in the second embodiment, the second metal thin film formed in (E) of the first embodiment is also used as the pixel reflection electrode 25. In other words, the pixel reflection electrode 25 is formed by the conductive film 19 in the same layer as the source wiring 22 and is provided by a transflective liquid crystal display device having the same.

  That is, a portion of the pixel electrode 11a that does not overlap with the pixel reflection electrode 25 is a transmission portion, and a portion where the pixel reflection electrode 25 is provided is a reflection portion. Thus, by forming the pixel reflective electrode 25, a transflective liquid crystal display device having a transmissive portion and a reflective portion in one pixel can be formed.

  FIG. 4 is a manufacturing process diagram for this embodiment. In the present embodiment, in addition to the manufacturing process shown in the first embodiment, the pixel reflection electrode 25 and the pixel contact hole 24 are formed. Since the steps other than these forming steps are the same as those in the first embodiment, description thereof will be omitted.

(D) Fourth photolithography process In the dry etching process of the second insulating film, except that the pixel contact hole 24 penetrating to the surface of the pixel electrode 11a extending to the drain electrode 11c is formed. It is the same.

(E) Fifth photolithography process It is the same as that of Example 1 except that the pixel reflection electrode 25 is formed when the second metal thin film is patterned. A pixel reflection electrode 25 is formed so as to be electrically connected to the drain electrode 11c and the pixel electrode 11a through the pixel contact hole 24. Thereby, the TFT array substrate for liquid crystal display in the second embodiment is completed.

  As the second metal thin film of the present embodiment, it is preferable to use AlNi that has low electrical specific resistance and good electrical contact characteristics and reflection characteristics with the transparent conductive film 11. AlNi is preferably obtained by adding 2 mol% of Ni to Al.

Embodiment 3 FIG.
The present embodiment is different from the second embodiment in that Ag or an Ag alloy is used for the second metal thin film. Therefore, the description common to the second embodiment is omitted. By using Ag or an Ag alloy for the second metal thin film, it is possible to provide a TFT array substrate for transflective liquid crystal display with low resistance, good reflection characteristics, and excellent optical and electrical characteristics.

  Patent Document 1 describes that an Ag film is used for the source wiring 22 and the like. However, when forming a contact hole, there is a problem that Ag is damaged and disappears by plasma during dry etching. Therefore, it has been difficult to use Ag and an Ag alloy in the conventional TFT structure. However, in the present invention, the source wiring 22 is formed after the contact hole is formed. Therefore, the source wiring in the upper layer is not damaged by plasma due to dry etching, and deterioration of electrical characteristics can be prevented.

  When an Ag alloy is used for the second metal thin film, palladium (Pd), copper (Cu), molybdenum (Mo), neodymium (Nd), ruthenium (Ru), germanium (Ge), gold (Au) and It is preferable to contain one or more of tin oxide (SnOx). Thereby, it is possible to obtain a source wiring having excellent adhesion and low resistance. In addition, it is possible to form a pixel reflection electrode having excellent adhesion and reflection characteristics.

Embodiment 4 FIG.
The present embodiment is different from the first embodiment in that Cu or a Cu alloy is used for the second metal thin film. Therefore, the description common to the first embodiment is omitted. By using Cu or Cu alloy having a resistance lower than that of Al for the second metal thin film, it is possible to provide a TFT array substrate having a high definition and a large screen. Further, when a CuMo alloy film in which Mo is added to Cu is used, it is possible to form a source wiring having excellent adhesion and low resistance.

  Conventionally, it has been difficult to control etching when forming a thick film of Cu or Cu alloy. For this reason, the cross-sectional shape on both sides of the wiring is poor, and it is difficult to form an electrical element such as a pixel electrode on the upper layer of the Cu film. In the present invention, the second metal thin film is formed on the uppermost layer of the TFT array substrate. As a result, the influence of the cross-sectional shape on the yield can be lost.

  The transparent conductive film 11 in the first to fourth embodiments is used as the source electrode 7, the drain electrode 6, the gate terminal pad pattern, and the source terminal pad pattern. Furthermore, in the configurations of Embodiments 1 to 4, even if the source wiring 22 is a single layer, a display device with high display quality and high productivity can be provided.

  Note that the transparent conductive film 11 electrically connected to the source wiring 22 may be formed below the source wiring 22. For example, the transparent conductive film 11 may be formed and laminated in the same shape as the source wiring 22 via the interlayer insulating film 8 or the like under the source wiring 22. In this case, it is necessary to form innumerable contact holes in the interlayer insulating film 8 below the source wiring 22 and connect the source wiring 22 and the transparent conductive film 11. Here, the source wiring 22 and the transparent conductive film 11 below the source wiring 22 are formed in parallel with the same pattern width. That is, the source wiring 22 and the transparent conductive film 11 below the source wiring 22 have the same pattern shape. Therefore, when forming the transparent conductive film 11 in the third photolithography process (C), the transparent conductive film 11 is formed along the direction in which the source wiring 22 is provided.

  Alternatively, the interlayer insulating film 8 may be removed in the same shape as the source wiring 22, and a part or all of the source wiring 22 may have a laminated structure of the source wiring 22 (upper layer) and the transparent conductive film 11 (lower layer). In this case, even if the source wiring 22 is disconnected, the transparent conductive film is formed in the lower layer of the disconnected portion, so that the effect of redundant wiring can be obtained and a TFT array substrate with higher yield can be provided. Become.

It is a top view which shows the structure of the TFT array substrate concerning embodiment of this invention. 1 is a plan view showing a pixel configuration of a TFT array substrate according to a first embodiment of the present invention. It is sectional drawing which shows the pixel structure of the TFT array substrate concerning Embodiment 1 of this invention. It is a flowchart which shows the manufacturing process of the TFT substrate concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of the gate terminal part concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of the source terminal part concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of another gate terminal part concerning Embodiment 1 of this invention. It is sectional drawing which shows the structure of another source terminal part concerning Embodiment 1 of this invention. It is a top view which shows the structure of the TFT array substrate concerning Embodiment 2 of this invention. It is sectional drawing which shows the structure of the TFT array substrate concerning Embodiment 2 of this invention. It is a top view which shows the structure of the conventional TFT array substrate for liquid crystal display devices. It is sectional drawing which shows the structure of the conventional TFT array substrate. It is sectional drawing which shows the gate terminal part of the TFT array substrate for the conventional liquid crystal display devices. It is sectional drawing which shows the source terminal part of the conventional TFT array substrate for liquid crystal display devices.

Explanation of symbols

1 gate electrode, 2 auxiliary capacitance electrode, 3 gate insulating film, 4 semiconductor active film,
5 ohmic contact film, 6 drain electrode, 7 source electrode,
8 interlayer insulation film, 9 pixel contact hole,
10 part having auxiliary capacity, 11 transparent conductive film,
11a pixel electrode, 11b source electrode, 11c drain electrode,
14 gate terminal pad pattern, 18 source terminal pad pattern,
19 conductive film, 20 auxiliary capacity wiring, 21 gate wiring, 22 source wiring,
23 semiconductor layer, 24 pixel contact hole, 25 pixel reflective electrode,
26 TFT channel part, 27 Source electrode contact hole,
28 source terminal pad pattern, 29 gate terminal pad pattern 110 substrate, 111 display area, 112 frame area, 22 source wiring,
115 scanning signal driving circuit, 116 display signal driving circuit,
117 pixels, 118 external wiring, 119 external wiring, 120 TFT

Claims (8)

A gate electrode provided on the substrate;
A gate insulating film formed on the gate electrode;
A semiconductor layer formed on the gate insulating film and disposed opposite to the gate electrode;
A source electrode and a drain electrode made of a transparent conductive film formed on the semiconductor layer;
A pixel electrode extending from the drain electrode and made of the transparent conductive film;
An interlayer insulating film formed on the pixel electrode, the source electrode, and the drain electrode and having a contact hole reaching the source electrode;
A TFT array substrate comprising: a source wiring formed on the interlayer insulating film; and the source wiring connected to the source electrode through the contact hole.   The TFT array substrate according to claim 1, wherein the source wiring contains Al, Ag, or Cu.   The transparent conductive film is formed in a lower layer of the source wiring along a direction in which the source wiring is provided, and the transparent conductive film formed in the lower layer of the source wiring is electrically connected to the source wiring. The TFT array substrate according to claim 1 or 2, wherein: A gate wiring connected to the gate electrode is connected to a terminal pad pattern made of a conductive film in the same layer as the source wiring through a gate terminal contact hole.
The transparent conductive film is connected to the terminal pad pattern through a contact hole;
The TFT array substrate according to claim 1, wherein the gate wiring and the transparent conductive film are connected via the terminal pad pattern.   A display device comprising the TFT array substrate according to claim 1. Forming a gate electrode on the substrate;
Forming a gate insulating film on the gate electrode;
Forming a semiconductor layer on the gate insulating film so as to face the gate electrode;
Forming a source electrode made of a transparent conductive film on the semiconductor layer, a drain electrode, and a pixel electrode extending from the drain electrode;
Forming an interlayer insulating film formed on the pixel electrode, the source electrode, and the drain electrode, and having a contact hole reaching the source electrode;
Forming a source wiring connected to the source electrode through the contact hole on the interlayer insulating film.   The method of manufacturing a TFT array substrate according to claim 6, wherein the source wiring contains Al, Ag, or Cu. In the step of forming the source electrode, the drain electrode, and the pixel electrode, the transparent conductive film is formed in a lower layer of the source wiring along a direction in which the source wiring is provided,
The manufacturing method of the TFT array substrate according to claim 6 or 7, wherein the transparent conductive film formed under the source wiring is electrically connected to the source wiring.

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