CN101071626A - 用于半导体存储装置的数据输出电路 - Google Patents

用于半导体存储装置的数据输出电路 Download PDF

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Publication number
CN101071626A
CN101071626A CNA2007101071432A CN200710107143A CN101071626A CN 101071626 A CN101071626 A CN 101071626A CN A2007101071432 A CNA2007101071432 A CN A2007101071432A CN 200710107143 A CN200710107143 A CN 200710107143A CN 101071626 A CN101071626 A CN 101071626A
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CN
China
Prior art keywords
driver
control signal
output
data
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
CNA2007101071432A
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English (en)
Chinese (zh)
Inventor
李炯东
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SK Hynix Inc
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of CN101071626A publication Critical patent/CN101071626A/zh
Pending legal-status Critical Current

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    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1066—Output synchronization
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1051—Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
    • G11C7/1069—I/O lines read out arrangements
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/10—Aspects relating to interfaces of memory device to external buses
    • G11C2207/108—Wide data ports
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2254—Calibration

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  • Dram (AREA)
  • Logic Circuits (AREA)
CNA2007101071432A 2006-05-08 2007-04-30 用于半导体存储装置的数据输出电路 Pending CN101071626A (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR1020060040932A KR100776740B1 (ko) 2006-05-08 2006-05-08 반도체 메모리의 데이터 출력장치 및 방법
KR1020060040932 2006-05-08

Publications (1)

Publication Number Publication Date
CN101071626A true CN101071626A (zh) 2007-11-14

Family

ID=38661032

Family Applications (1)

Application Number Title Priority Date Filing Date
CNA2007101071432A Pending CN101071626A (zh) 2006-05-08 2007-04-30 用于半导体存储装置的数据输出电路

Country Status (5)

Country Link
US (1) US20070258293A1 (enExample)
JP (1) JP2007305288A (enExample)
KR (1) KR100776740B1 (enExample)
CN (1) CN101071626A (enExample)
TW (1) TW200743117A (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102420006A (zh) * 2007-12-27 2012-04-18 海力士半导体有限公司 半导体存储装置中的数据输出电路
CN102737699A (zh) * 2011-03-31 2012-10-17 海力士半导体有限公司 半导体装置的数据输出电路

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011170516A (ja) 2010-02-17 2011-09-01 Elpida Memory Inc メモリコントローラ、半導体記憶装置およびこれらを備えるメモリシステム
KR102860214B1 (ko) 2020-08-21 2025-09-15 삼성전자주식회사 선택적 레벨 변경을 이용한 멀티 레벨 신호 생성 방법, 이를 이용한 데이터 전송 방법, 이를 수행하는 송신기 및 메모리 시스템

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3979690B2 (ja) * 1996-12-27 2007-09-19 富士通株式会社 半導体記憶装置システム及び半導体記憶装置
JPH11213666A (ja) * 1998-01-30 1999-08-06 Mitsubishi Electric Corp 出力回路および同期型半導体記憶装置
JP2001084773A (ja) * 1999-09-16 2001-03-30 Nec Corp 半導体記憶装置
US6351172B1 (en) * 2000-02-29 2002-02-26 Dmel Inc. High-speed output driver with an impedance adjustment scheme
US6889336B2 (en) * 2001-01-05 2005-05-03 Micron Technology, Inc. Apparatus for improving output skew for synchronous integrate circuits has delay circuit for generating unique clock signal by applying programmable delay to delayed clock signal
JP2003007052A (ja) * 2001-06-20 2003-01-10 Mitsubishi Electric Corp 半導体記憶装置およびそれを用いたメモリシステム
EP1492286B1 (en) * 2002-03-29 2012-02-08 Fujitsu Limited Driver driving method; driver circuit; transmission method using driver,and control circuit
KR100480596B1 (ko) 2002-04-03 2005-04-06 삼성전자주식회사 업-슬루율 및 다운-슬루율, 업-드라이빙 세기 및다운-드라이빙 세기가 상호 독립적으로 조절되는 출력드라이버 회로
KR100486263B1 (ko) * 2002-09-19 2005-05-03 삼성전자주식회사 Ｓｄｒ/ｄｄｒ 겸용 반도체 메모리 장치의 데이터 출력 회로
KR100510516B1 (ko) * 2003-01-23 2005-08-26 삼성전자주식회사 이중 데이터율 동기식 반도체 장치의 데이터 스트로브신호 발생 회로
JP2005032291A (ja) * 2003-07-07 2005-02-03 Renesas Technology Corp 半導体記憶装置
KR100499417B1 (ko) * 2003-07-15 2005-07-05 주식회사 하이닉스반도체 디디알 에스디램에서의 링잉 현상 방지 방법 및 그 장치
KR100550796B1 (ko) * 2003-12-11 2006-02-08 주식회사 하이닉스반도체 반도체 메모리 소자의 데이터 전송 장치 및 그 제어 방법
KR100554845B1 (ko) * 2003-12-15 2006-03-03 주식회사 하이닉스반도체 반도체 메모리 소자의 ｄｑｓ 신호 생성 회로 및 그 생성 방법
DE102004021694B4 (de) * 2004-04-30 2010-03-11 Qimonda Ag Verfahren und Schaltungsanordnung zum Steuern eines Schreibzugriffs auf einen Halbleiterspeicher
KR100559737B1 (ko) * 2005-03-14 2006-03-10 삼성전자주식회사 반도체 장치, 반도체 메모리 장치 및 반도체 장치의 데이터스트로브 제어 방법

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102420006A (zh) * 2007-12-27 2012-04-18 海力士半导体有限公司 半导体存储装置中的数据输出电路
CN102420006B (zh) * 2007-12-27 2014-12-24 海力士半导体有限公司 半导体存储装置中的数据输出电路
CN102737699A (zh) * 2011-03-31 2012-10-17 海力士半导体有限公司 半导体装置的数据输出电路
CN102737699B (zh) * 2011-03-31 2016-09-07 海力士半导体有限公司 半导体装置的数据输出电路

Also Published As

Publication number Publication date
JP2007305288A (ja) 2007-11-22
US20070258293A1 (en) 2007-11-08
TW200743117A (en) 2007-11-16
KR20070108639A (ko) 2007-11-13
KR100776740B1 (ko) 2007-11-19

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