CN101043067A - 用以制造柱状相变化存储元件的方法 - Google Patents
用以制造柱状相变化存储元件的方法 Download PDFInfo
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- CN101043067A CN101043067A CN200710001812.8A CN200710001812A CN101043067A CN 101043067 A CN101043067 A CN 101043067A CN 200710001812 A CN200710001812 A CN 200710001812A CN 101043067 A CN101043067 A CN 101043067A
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/063—Shaping switching materials by etching of pre-deposited switching material layers, e.g. lithography
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Shaping switching materials
- H10N70/068—Shaping switching materials by processes specially adapted for achieving sub-lithographic dimensions, e.g. using spacers
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
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- H10N70/8825—Selenides, e.g. GeSe
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- H10N70/8828—Tellurides, e.g. GeSbTe
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Abstract
一种用以在集成电路上制造次特征尺寸柱状结构的方法。此方法首先提供衬底，此衬底上形成有相变化层、电极层、以及硬掩模层。接着通过平板印刷图案化、蚀刻、并剥除光阻层而形成征尺寸硬掩模，再缩减此硬掩模至选定的次特征尺寸，其中此缩减步骤对于此电极与此相变化层以及此硬掩模具有高度选择性。最后的步骤缩减此电极与相变化层至此硬掩模的尺寸，并移除此硬掩模。
Description
优先权信息
本申请要求美国临时申请No.60/757,341“Method for Fabricating aPillar-Shaped Phase Change Memory Element”的优先权，其申请日为2006年1月9日。
技术领域
本发明涉及使用相变化存储材料的高密度存储元件，相变化存储材料包括硫属化物材料与其他材料。本发明同时涉及用以制造这些元件的方法，并尤其涉及用以制造这些尺寸小于工艺中的最小特征尺寸的元件的方法。
背景技术
以相变化为基础的存储材料被广泛地运用于非易失性随机存取存储单元中。包括硫属化物与类似物的这些材料，可通过施加其幅度适用于集成电路中的电流，而引起晶相在非晶态与结晶态之间转换。一般而言非晶态的特征为其电阻高于结晶态，此电阻值可轻易测量得到而用以标示数据。
从非晶态转变至结晶态一般为低电流步骤。从结晶态转变至非晶态(以下指称为重置(reset))一般为高电流步骤，其包括短暂的高电流密度脉冲以融化或破坏结晶结构，其后此相变化材料会快速冷却，抑制相变化的过程，使得至少部份相变化结构得以维持在非晶态。理想状态下，引起相变化材料从结晶态转变至非晶态的重置电流幅度应越低越好。欲降低重置所需的重置电流幅度，可通过减低在存储体中的相变化材料元件的尺寸、以及减少电极与此相变化材料的接触面积而达成，因此可针对此相变化材料元件施加较小的绝对电流值而得到较高的电流密度。
此领域发展的一种方法致力于在集成电路结构上形成微小孔洞，并使用微量可编程的电阻材料填充这些微小孔洞。致力于这些微小孔洞的专利包括：于1997年11月11日公告的美国专利No.5,687,112”Multibit Single Cell Memory Element Having Tapered Contact”、发明人为Ovshinky；于1998年8月4日公告d美国专利No.5,789,277”Methodof Making Chalogenide[sic]Memory Device”、发明人为Zahorik等；于2000年11月21日公告的美国专利No.6,150,253”ControllableOvonic Phase-Change Semiconductor Memory Device and Methods ofFabricating the Same”、发明人为Doan等。
在以非常小的尺度制造这些装置、以及欲满足大规模存储装置时所需求的严格工艺参数时，则会遇到问题。特别是，需要在制造存储单元时使存储单元的部分尺寸小于100纳米时，会遇到此工艺的最小特征尺寸(可被平板印刷蚀刻所定义的最小尺寸)无法允许上述小尺寸特征的定义与形成。
在此领域中已经了解到这个问题的发生，但是并没有提供可以在100纳米以下的尺寸下生成特征结构的解决方法。举例而言，发明人为Dennison的美国专利No.6,744,088”Phase change Memory on aPlanar Composite Layer”，讨论了最小特征尺寸的问题，并提供了多种可能的解决方案，包括使用较短波长的平板印刷(lithography)光源(例如X光)或相转移光掩模、或侧壁隔离，然而这些方式均只能将最小特征尺寸降低到大约100纳米。没有其他方法可以将最小特征尺寸进一步降低。
优选地可提供一种存储单元结构，其具有小尺寸以及低重置电流，同时其结构可解决导热性问题，同时能提供一种用以制造这些结构的方法而能满足用以大规模制造存储元件时的严格工艺参数规格。更优地提供一种制造程序以及结构，其可和制造同一集成电路的周边电路相兼容。
发明内容
一种在集成电路上制造次特征(sub-feature)尺寸的柱状结构的方法，包括下列步骤：提供衬底，此衬底上形成有相变化层、电极层、以及硬掩模层；通过平板印刷图案化、蚀刻、并剥除光阻层而形成特征尺寸硬掩模；缩减此硬掩模至选定的次特征尺寸，其中此缩减步骤对于此电极与此相变化层以及此硬掩模具有高度选择性；缩减此电极与相变化层至此硬掩模的尺寸；以及移除此硬掩模。
附图说明
图1示出本发明的柱状随机存取存储元件。
图2示出制造本发明的柱状随机存取存储元件的初始步骤。
图3示出制造本发明的柱状随机存取存储元件的下一步骤。
图4示出制造本发明的柱状随机存取存储元件的下一步骤。
图5示出制造本发明的柱状随机存取存储元件的下一步骤。
主要元件符号说明
10 柱状结构
12 衬底
14 接触栓塞
16 相变化材料层
18 电极层
20 硬掩模层
22 光掩模
24 介质材料层
26 位线电极结构
具体实施方式
以下详细说明本发明的结构与方法。本发明内容说明部分的目的并非在于限定本发明。本发明由权利要求所限定。凡本发明的实施例、特征、目的及优点等将可通过下列说明书、权利要求书及附图获得充分了解。
图1示出了本发明的柱状结构10。此柱状结构位于衬底12上并具有接触栓塞14，衬底12典型地由二氧化硅或其他公知结构所形成，而接触栓塞14优选地由如钨与铜的耐热金属所构成，并延伸穿透此衬底以接触到附属电路(未示出)。其他可使用的耐热金属包括钛、钼、铝、钽、铜、铂、铱、镧、镍、以及钌。
此柱状结构本身为相当窄的结构，其具有二层：相变化材料层16以及电极层18。电极层为具有良好导电性、可与相变化材料形成优秀粘附特性的材料薄膜，此材料同时可以用作为相变化材料的良好扩散障碍。优选地在电极层使用氮化钛，其他可使用的材料包括钛、钨、钽、氮化钽、钨化钛与类似材料，例如某些具有低导热性的导电氧化物，例如氧化锂铌、镧锶锰氧化物、铟锡氧化物等。此层的厚度介于10至200纳米之间，且在一实施例中优选地为75纳米。此相变化层的厚度介于10至100纳米之间，且在一实施例中优选地为50纳米。
针对本发明书中所提及的方向，对照到附图中所指的“上”、“下”、“左”、“右”指在图中的相对方向。相似地，“厚度”指垂直方向的尺寸，而“宽度”则是指水平方向的尺寸。如本领域的技术人员所了解的那样，这些方向对于电路在操作中的方向并无实际意义。
相变化层16由相变化存储材料所构成，优选地为硫属化物。硫属化物包括下列四元素的任一种：氧(O)、硫(S)、硒(Se)、以及碲(Te)，形成元素周期表上第VI族的部分。硫属化物包括将硫属元素与更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其他物质如过渡金属等结合。硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素，例如锗(Ge)以及锡(Sn)。通常，硫属化合物合金包括下列元素中一个以上的复合物：锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已经在技术文件中进行了描述，包括下列合金：镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中，可以尝试大范围的合金成分。此成分可以下列特征式表示：TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为，在沉积材料中所包括的平均碲浓度远低于70％，典型地低于60％，并在一般类型的合金中的碲含量范围从最低23％至最高58％，且最佳为介于48％至58％得到碲含量。锗的浓度高于约5％，且其在材料中的平均范围从最低8％至最高30％，一般低于50％。最佳地，锗的浓度范围介于8％至40％。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比，其为所有组成元素总和为100％。(Ovshinky‘112专利，栏10～11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada，”Potential ofGe-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording”，SPIE v.3109，pp.28-37(1997))更一般地，过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金，可与锗/锑/碲结合以形成相变化合金，其包括有可编程的电阻性质。可使用的存储材料的特殊范例，如Ovshinsky‘112专利中栏11-13所述，其范例在此列入参考。
相变化合金能在此单元活性通道区域内依其位置顺序在材料为一般非晶态的第一结构状态与为一般结晶固体状态的第二结构状态之间切换。这些材料至少为双稳定态的。“非晶”一词指相对较无次序的结构，其比单晶更无次序性，而带有可检测的特征，如比结晶态更高的电阻值。“结晶态”指相对较有次序的结构，其比非晶态更有次序，因此包括有可检测的特征，例如比非晶态更低的电阻值。典型地，相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其他受到非晶态与结晶态的改变而影响的材料特中包括，原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物，提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质也可能随之改变。
相变化合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出，较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量够大，因此足以破坏结晶结构的键结，同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下，可决定特别适用于特定相变化合金的适当脉冲量变曲线。在本文的后续部分，此相变化材料以GST代称，同时应该了解，也可使用其他类型的相变化材料。在本文中所描述的一种适用于PCRAM中的材料，为Ge2Sb2Te5。
可用于本发明其它实施例中的其它可编程的存储材料包括，掺杂N2的GST、GexSby、或其它以不同结晶态变化来决定电阻的物质；PrxCayMnO3、PrSrMnO、ZrOx、TiOx、NiOx、WOx、经掺杂的SrTiO3或其它利用电脉冲以改变电阻状态的材料；或其它使用电脉冲以改变电阻状态的物质；四氰代二甲基苯醌(7，7，8，8-tetracyanoquinodimethane，TCNQ)、甲烷富勒烯66苯基C61丁酸甲酯(methanofullerene 6，6-phenyl C61-butyric acid methyl ester，PCBM)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何其它聚合物材料其包括有以电脉冲而控制的双稳态或多稳态电阻态。
制造本发明的元件的方法的起始步骤，如图2所示，其示出在衬底12上沉积有相变化层16与电极层18后的工艺步骤。这些沉积工艺为公知的，且可在衬底的表面上生成对应材料的均匀薄膜层，其厚度如上所述。
公知技术接着会进行平板印刷工艺，然而这些工艺并无法制造特征尺寸小于所使用平板印刷工艺的最小特征尺寸的电路。在此，沉积硬掩模层20于电极层18上。硬掩模的构成材料，对蚀刻工艺比公知的光阻材料具有更大的耐受性。在此领域中已知可用做硬掩模的材料中，有三种材料最适于用在本发明的工艺中。第一实施例使用硅氧化物，第二实施例使用硅氮化物，而第三实施例则使用钨。本领域的技术人员可以理解的是，其他材料也可使用。在此，后续的叙述将会分别提及上述的三种实施例。
沉积技术随着在每一实施例中所选择的材料而做调整。硅氧化物与硅氮化物层可利用高密度等离子体化学气相沉积(HDP CVD)方式而沉积。钨层则优选地利用公知的金属化工艺而沉积，例如物理气相沉积(PVD)或其变化方式。对于三种实施例而言，硬掩模层的厚度可以介于50至300纳米。
硬掩模层的图案化使用公知的平板印刷工艺，如硬掩模层上所出现的光掩模22所示。此光掩模由公知技艺中，沉积一层光阻材料、通过光掩模而将此材料暴露于放射线中(光或紫外光)，并除去不需要部分的材料以留下此掩模而产生。硬掩模的尺寸受限于此工艺的最小特征尺寸，在此工艺中大约为150纳米。需要注意的是，除了最小特征尺寸所产生的问题之外，在此并不会提及此问题的进一步处理。光掩模22的尺寸优选地为此工艺所允许的最小特征尺寸。
图3示出了硬掩模蚀刻步骤的结果。一般而言，所有被光阻所暴露的区域下的硬掩模都被移除了(请参见图2)，一直到电极层18的上表面。此特定的蚀刻方法必须随着硬掩模的制作而做调整，且也需要考虑蚀刻剂对硬掩模材料与电极层的选择性。因此，不同的蚀刻工艺使用于每一硬掩模实施例中。对于使用硅氧化物作为硬掩模的实施例而言，优选地使用反应性离子蚀刻(RIE)，并使用四氟化碳作为蚀刻剂。其他适合的蚀刻剂包括三氟甲烷、氩气、八氟环丁烷、氧气、或其他此领域所熟知的蚀刻剂。对于使用硅氮化物作为硬掩模的实施例而言，优选地也使用反应性离子蚀刻，并以四氟化碳作为蚀刻剂。其他适合的蚀刻剂包括氟甲烷、氩气、三氟甲烷、氧气、或其他此领域所公知的蚀刻剂。对于使用钨作为硬掩模的实施例而言，优选地也使用反应性离子蚀刻，并使用六氟化硫作为蚀刻剂。其他适合的蚀刻剂包括氩气、氮气、氧气、或其他此领域中所公知的蚀刻剂。
在硬掩模的蚀刻之后，光阻被剥除。优选地剥除光阻而非将光阻留下，因为光阻的高分子材料可能在后续步骤中降解，造成难以处理的有机废料。三个实施例中优选的剥除方法均为使用氧气等离子体，接着以适当溶剂进行湿剥除以增加效率，适当溶剂可举例如EKC265。这些工艺及其应用在此领域中为公知的。
此时，剩余的硬掩模材料具有大约150纳米的宽度，而硬掩模的关键尺寸(即宽度)则需要缩减到大约50纳米。本发明的方法利用蚀刻工艺以缩减硬掩模20的宽度。此工艺必须可以精确地控制时机，并在电极层与硬掩模间具有高度的选择性。
图4显示了硬掩模缩减步骤之后的结果。如图所示，硬掩模20的尺寸被缩减了大约原来的2/3，而在本例中则缩减至50纳米。如同先前的蚀刻步骤，每一种硬掩模实施例的工艺均不同。共同的因素则是此工艺需要进行湿蚀刻，因为湿蚀刻提供了优良的控制性与选择性。对于硅氧化物硬掩模而言，此工艺使用了稀释的氢氟酸或缓冲氢氟酸。在硅氮化物实施例中，则使用了热磷酸作为蚀刻剂，而在钨的实施例中则使用过氧化氢与适合的溶剂。湿蚀刻在此领域中所公知，并且此工艺的使用根据此领域中所熟知的原则而进行。
一旦硬掩模被缩减至理想尺寸后，则可发挥其掩模功能而将电极与相变化层缩减至与掩模相同的尺寸。图5示出了该部分缩减操作的结果。如图所示，电极层18与相变化层16被缩减至硬掩模20的宽度，留下相当窄的柱状结构并接触至栓塞14。
此步骤的蚀刻工艺必须符合数个条件。首先，此工艺必须为各向异性的，因为其必须移除电极与相变化层而不会对硬掩模形成底切。此步骤还必须对电极与相变化材料以及硬掩模材料、以及其下的衬底与栓塞材料有良好的选择性。
本发明的一实施例使用了反应性离子蚀刻，并以氯气作为优选的蚀刻剂。其他实施例可单独或合并使用氯化硼、氩气、溴化氢、三氟甲烷或氧气作为蚀刻剂。本领域中公知的是，确定一族适合的蚀刻剂，并结合这些蚀刻剂以获得特定应用的最佳结果。此种结合会随着所面临的目标而改变，然而选择并测试此种组合的过程为公知的。
此蚀刻工艺并不是定时工艺，而是在移除相变化层的预定部分后就完成，因此允许使用光学发射终点感测技术，以检测伴随着相变化层的完全移除以及蚀刻到达衬底时，所发生的蚀刻副产物的变化。这些仪器会进行等离子体的频谱分析，并辨识当硅氧化物出现在等离子体中时则表示蚀刻抵达衬底。
上述的单步骤工艺的替代工艺，一个二步骤蚀刻工艺，以移除相变化层以及电极层。在此，并非以单一步骤移除此二层，而是施行二个独立的子步骤，其使用了相同或不同的蚀刻剂。在此，二个步骤均为反应性离子蚀刻，利用氯气作为优选的蚀刻剂。在替代实施例中可单独或合并使用氯化硼、氩气、溴化氢、三氟甲烷、或氧气作为蚀刻剂。第一步骤使用了终点感测系统，其检测蚀刻抵达相变化层的时候，以启动终止信号。第二步骤当蚀刻抵达氧化硅衬底时终止。
所完成的产物如图1所示。此结果接着图5之后的步骤所完成。首先，将硬掩模剥除，留下由相变化层16与电极层18所形成的相变化元件。介质材料层24沉积于相变化元件上并将其环绕，且位线电极结构26优选地形成于相变化元件上，提供位线与电极层之间的接触。此介质层优选地为氧化硅或其他低介电值材料，以高密度等离子体或化学气相沉积工艺所形成，或利用旋转涂布或其他公知工艺所形成。一实施例通过沉积介质层至200-1000纳米的厚度而进行，优选地为300纳米。化学机械研磨(CMP)工艺用以平坦化此介质层表面，接着进行位线平板印刷工艺以在介质层中形成位线沟槽，其延伸至电极层的水平面。适合的接触金属如铜等，沉积于此沟槽中，并进行另一次化学机械研磨工艺以将所生成的表面平坦化。
需要注意的是，此大致柱状的相变化元件为上述工艺的重要结果。大致而言，相变化元件为平版状，但本发明的工艺能够制造小体积的元件，进而将相变化效应所需要的电流最小化，进而将单元中所产生的热能最小化，此特点在数以百万计的单元排列成阵列的元件中是非常重要的。
虽然本发明已参照优选实施例加以描述，应该所了解的是，本发明并不受限于其详细描述的内容。替换方式及修改方式已在先前描述中建议，并且其他替换方式及修改方式将为本领域的技术人员可想到的。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件结合而实现与本发明实质上相同结果的，皆不脱离本发明的精神范畴。因此，所有这些替换方式及修改方式意欲落在本发明所附的权利要求书及其等价物所界定的范畴中。任何在前文中提及的专利申请以及公开文本，均列为本申请的参考。
Claims (17)
1.一种在集成电路上制造次特征尺寸柱状结构的方法，包括下列步骤：
提供衬底，该衬底上形成有相变化层、电极层、以及硬掩模层；
通过平板印刷图案化、蚀刻、并剥除光阻层而形成特征尺寸硬掩模；
缩减该硬掩模至选定的次特征尺寸，其中该缩减步骤对于该电极与该相变化层以及该硬掩模具有高度选择性；
缩减该电极与相变化层至该硬掩模的该尺寸；以及
移除该硬掩模。
2.如权利要求1所述的方法，其中该硬掩模的厚度介于约50至300纳米之间。
3.如权利要求1所述的方法，其中该硬掩模由硅氧化物所构成。
4.如权利要求1所述的方法，其中该硬掩模由硅氮化物所构成。
5.如权利要求1所述的方法，其中该硬掩模由钨所构成。
6.如权利要求1所述的方法，其中
该形成步骤包括以该工艺的大约最小特征尺寸进行平板印刷图案化；以及
该缩减步骤将该硬掩模缩减至使其尺寸小于该工艺的最小特征尺寸。
7.如权利要求1所述的方法，其中该缩减步骤将该硬掩模缩减至约50纳米的尺寸。
8.如权利要求1所述的方法，其中该硬掩模缩减步骤包括干蚀刻该硬掩模。
9.如权利要求8所述的方法，其中该干蚀刻包括反应性离子蚀刻。
10.如权利要求1所述的方法，其中该电极层与该相变化层缩减步骤包括针对该电极层与该相变化层进行湿蚀刻。
11.一种用以在集成电路上制造次特征尺寸柱状结构的方法，包括下列步骤：
提供衬底，该衬底上形成有薄膜相变化层、薄膜电极层、以及硬掩模层，其中
该硬掩模的厚度介于50至300纳米之间；
该硬掩模由选自下列组的材料所构成：硅氧化物、硅氮化物、以及钨；以及
该相变化层的厚度介于10至100纳米之间；
通过平板印刷图案化、蚀刻、并剥除光阻层而形成特征尺寸硬掩模，其中该图案化步骤形成平板印刷图案，其尺寸大约为该工艺的最小特征尺寸；
缩减该硬掩模至选定的次特征尺寸，其中
该缩减步骤对于该电极与该相变化层以及该硬掩模具有高度选择性；以及
该硬掩模缩减至大约50纳米的尺寸；
使用干蚀刻而缩减该电极与该相变化层至该硬掩模的尺寸，该干蚀刻为反应性离子蚀刻；以及
移除该硬掩模。
12.一种存储单元，包括：
多个电极，其位于衬底中并与电脑装置进行信息传输；
相变化元件，其具有大致方形的剖面，该相变化元件的门限尺寸约为50纳米、厚度大约50纳米，包括
障碍电极构件，其接触至该些电极之一；
相变化构件，其接触至该障碍电极构件与该其他电极，其中该相变化构件由具有至少二固态相的材料所构成。
13.如权利要求12所述的存储单元，其中该存储材料包括锗、锑、与碲的组合物。
14.如权利要求12所述的存储单元，其中该相变化单元包括由下列组的一种以上的材料所形成的组合物：锗、锑、碲、硒、铟、钛、镓、铋、锡、铜、钯、铅、银、硫、与金。
15.如权利要求12所述的存储单元，其中该关键尺寸横切至在该些电极间的电流路径。
16.如权利要求12所述的存储单元，其中该硬掩模缩减包一湿蚀刻工艺。
17.如权利要求12所述的存储单元，其中该硬掩模缩包括反应性离子蚀刻工具中进行蚀刻。
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2006
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2007
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101587905B (zh) * | 2008-05-22 | 2012-05-23 | 上海市纳米科技与产业发展促进中心 | 一种相变纳米晶体管单元器件及其制作方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| CN100524879C (zh) | 2009-08-05 |
| US20070158632A1 (en) | 2007-07-12 |
| TWI323940B (en) | 2010-04-21 |
| TW200727459A (en) | 2007-07-16 |
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