CN100501920C - 一种以自对准方式制造薄膜熔丝相变化随机存取存储器的方法 - Google Patents

一种以自对准方式制造薄膜熔丝相变化随机存取存储器的方法 Download PDF

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CN100501920C
CN100501920C CNB2007100044211A CN200710004421A CN100501920C CN 100501920 C CN100501920 C CN 100501920C CN B2007100044211 A CNB2007100044211 A CN B2007100044211A CN 200710004421 A CN200710004421 A CN 200710004421A CN 100501920 C CN100501920 C CN 100501920C
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龙翔澜
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Abstract

一种根据掩模修剪在较宽结构上制造自对准的较窄结构的方法。制造存储器件的方法，包含在包含有使用前段工艺生成的电路的衬底上形成电极层。此电极层包括第一电极和第二电极，其间有着绝缘构件以作为每个相变化存储单元。存储材料补钉形成于横越绝缘构件的该电极层的上表面。此补钉、第一电极和第二电极利用根据掩模修剪使用自对准工艺所生成。

Description

一种以自对准方式制造薄膜熔丝相变化随机存取存储器的方法
联合研究合约的当事人
国际商业机械公司纽约公司、旺宏国际股份有限公司台湾公司及英飞凌技术公司(Infineon Technologies A.G.)德国公司为联合研究合约的当事人。
技术领域
本发明涉及半导体器件的制造方法，特别涉及在次平板印刷(sub-lithographic)尺寸下制造半导体器件的方法。
背景技术
摩尔定律的操作认为，集成电路上的晶体管数目，每十八个月就会增加一倍，因此明显地需要更小的器件尺寸。在业界已熟知，使用目前已知的工艺技术已经遇到所能生产最小器件尺寸的瓶颈。传统的工艺以沉积和蚀刻作为基础，采用光阻式蚀刻掩模。使用可见光将图案投影在光阻上，从而改变光阻结构以将不必要的部分轻易除去，可以将结果图案经由蚀刻复制到其下的物质上。
能够使用目前工艺达到的做小特征通常称为”最小特征尺寸”。当尺寸要求不断地缩小时，然而，此尺寸缩小的需求会遭遇到如光波长等问题，我们不能产生比所使用的光波长更小的物体。所使用的波长目前已被缩短，现在已延伸到可见光之下，同时取代传统的投影技术也已经被开发。
业界已认定到此作法的一些问题，但是尚未能提供解决方法，可以允许产生在范围100纳米或更小的特征。如Dennison的美国专利No.6,744,088号，发明名称为“Phase Change Memory Device on aPlanar Composite Layer(在平坦复合层上的相变化存储器件)”的专利，讨论了最小特征尺寸，以及一些可能的解决方案，包括在平板印刷工艺中使用较短波长的光源，如X光，或是相位移掩模，或是侧壁隔离(spacer)等，这些方式均足以使用于约100纳米。然而，并没有提供小于这个水准的解决方案。
当制造如此小尺寸的器件会遇到许多问题，且工艺的变异要符合制造大尺寸的集成电路的严格工艺规范也是很困难的。因此，必须发展出有着小尺寸以及低重置电流的存储器单元结构，且其制造方法必须符合高级存储器件所需的严谨工艺的变异规范。更需要提供一种结构及其制造方法，可以同时适用于同一晶片中周边电路的制造。
发明内容
本发明的目的为提供一种根据掩模修剪在较宽结构上制造自对准的较窄结构的方法。此制造存储器件的方法，包括在包含有使用前段工艺生成的电路的衬底上形成电极层。此电极层包括第一电极和第二电极，其间有着绝缘构件以作为每一相变化存储单元。存储材料补钉形成于横越绝缘构件的该电极层的上表面。此补钉、第一电极和第二电极利用根据掩模修剪使用自对准工艺所生成。
根据本发明一方面，提供了一种在集成电路元件上制造结构的方法，包含：形成第一材料层，其有着上表面；在该第一材料层的该上表面上形成第二材料层；施加蚀刻掩模于该第二材料层上，该蚀刻掩模定义出会在该第一材料层上形成的第一结构的图案；根据该蚀刻掩模蚀刻该第二材料层和该第一材料层；修剪该蚀刻掩模以形成修剪蚀刻掩模，该修剪蚀刻掩模定义出会在该第二材料层上形成的较窄第二结构的图案；以及根据该修剪蚀刻掩模蚀刻该第二材料层，以形成该第二结构与该第一结构对准。
根据本发明的另一方面，提供了一种制造存储器件的方法，包含：形成有着上表面电极层，该电极层包括第一电极构件以及第二电极构件，且有着位于该第一电极构件与该第二电极构件之间的绝缘构件，该第一电极构件、该第二电极构件与该绝缘构件向该电极层的上表面延伸，且该绝缘构件在该上表面有着介于该第一电极构件与该第二电极构件之间的宽度；在该电极层横越该绝缘构件的该上表面形成存储材料薄膜，该存储材料薄膜有着第一端以及第二端，且与该第一电极构件与该第二电极构件在该第一端接触；在该存储材料薄膜上施加蚀刻掩模，该蚀刻掩模定义出会在该第一电极构件与该第二电极构件形成的第一电极和第二电极的图案；根据该蚀刻掩模蚀刻该存储材料薄膜和该电极层；修剪该蚀刻掩模以形成修剪蚀刻掩模，该修剪蚀刻掩模定义出形成于该第一电极和第二电极上的该存储材料薄膜的较窄补钉图案；以及根据该修剪蚀刻掩模蚀刻该存储材料薄膜，以与该第一电极和第二电极对准形成该补钉，该补钉定义出横越该绝缘构件介于该第一电极和第二电极之间的电极间通道，其有着由该绝缘构件宽度所定义的通道长度，其中该存储材料薄膜有着至少两个固态相。
附图说明
图1A至图1F示出了根据本发明实施例的通用工艺描述的剖面图；
图2A至图2B示出了根据本发明实施例的工艺的起始步骤；
图3A至图3B示出了根据本发明实施例的工艺的进一步骤；
图4A至图4B示出了根据本发明实施例的工艺的更进一步骤；
图5A及图5B示出了根据本发明实施例的工艺的更进一步骤。
主要元件符号说明
10：存储器结构
12：第一材料层
14：第二材料层
16：光阻层
100：随机存取存储器单元
101：基底结构
102：衬底
104：介质填充材料
106：字线
108：导电栓塞
110：共同源极线
112：电极层
114、116、118：电极构件
120、124：栏杆
122：基底构件
126：相变化材料
128：介质覆盖层
130：蚀刻掩模
具体实施方式
以下详细说明本发明的结构与方法。本发明内容说明章节的目的并非在于限定本发明。本发明由权利要求书所限定。凡本发明的实施例、特征、观点及优点等将可通过下列说明书、权利要求书及附图图1至图5获得充分了解。
一般半导体工艺系列是沉积单层或多层结构的材料，然后蚀刻该材料，或是减少其水平延伸区域或是在此材料中形成接触或沟渠。在任一状况下，传统实现此功效的工艺，一般称为平板印刷(lithography)，包括沉积光阻材料层，图案化该光阻材料层使得欲被除去的区域被曝光，在将曝露的区域蚀刻去掉以形成晶片所需的特征。如前所述，传统的技术会对不同的图案化与蚀刻使用不同的平板印刷工艺。同样地如前所述，然而，传统的技术在制造小于最小特征尺寸的元件会遇到严重的问题。
此外，传统的工艺在每一次蚀刻步骤都必须进行一次平板印刷循环。如此的图案化和蚀刻系列是非常消耗时间和资源的。
请参阅图1A到图1E，其示出形成至少一维小于最小特征尺寸的工艺。如此特征被称为“次特征尺寸”或是“次平板印刷”。图1显示的结构10包括两层，被沉积的第一材料12和第二材料14。为了方便说明起见，第一材料必须是与最小特征尺寸相当，在此约为150纳米。第二材料必须比第一尺寸还小，大约是一临界尺寸约50纳米。
第一缩减步骤的起始可见如图1A所示，通过沉积及定义光阻层16于此结构10的表面。必需了解的是，此处的平板印刷工艺可以是业界所通用的任一种平板印刷工艺。此工艺被通称为“平板印刷”，即根据图案化使用的光线及掩模而定。此工艺通常会受到曝光步骤中所使用的光波长所限制，然而，尝试使用更远离可见光的光波长来对此步骤改进。因此，此处所称的“平板印刷”包含各种范围的图案化技术，使用辐射源延伸至低于可见光的波长，且图案化技术如直接图案化，均为业界所公知。
然而，当实施此平板印刷工艺时，光阻层16会在此结构上产生理想尺寸或是最小特征尺寸F。但是要注意的是，在通常情况下，图1A中的结构反应了此光阻图案化步骤。此光阻覆盖在其下层材料上；在此光阻材料上图案化出理想的图案；将多余的光阻除去；曝露出需进一步蚀刻的其下的层。因此，所生成的光阻图案16会比结构10有着更小的尺寸，如图1A所示。在下一个步骤，此光阻材料会作为此蚀刻步骤的掩模，会在此结构10上除去物质而保留与光阻物质相同的水平尺寸。公知技术中有许多蚀刻技术可使用，且可选择任一适合于欲蚀刻的材料和所需求的控制条件来使用。因此，此蚀刻所生成的图案如图1B所示，两层材料12和14会缩减成和光阻掩模一样的尺寸。
至此，传统技术可以在另一平板印刷步骤后用来除去此光阻物质。然而，此步骤并不会产生所预期的结果，因为理想的层14的尺寸小于最小特征尺寸。因此，上方的光阻层必须裁减掉一部份以符合预期的尺寸。
图1C显示了光阻物质被修剪后的结果。由图中所示，光阻物质被缩小了三分之二，或是在其他情况下，至约50纳米的尺寸F’，其小于最小特征尺寸F。最好是利用干蚀刻来达到此效果，最好是离子反应式蚀刻(RIE)技术。干蚀刻技术已为业界所熟知，如何使用此工艺根据业界所知来进行。此蚀刻各向同性地修剪此光阻，使用氧气等离子体，在长度及宽度同时修剪。十分重要的是此工艺必须在第二材料层14与光阻材料16之间有着很高的选择性，以减少第二材料层的损失。
当光阻材料被修减至理想的尺寸后，其可以作为修剪第二材料层的掩模。图1D显示了第二材料层被修剪后的结果。由图中所示，第二材料层14被修剪至与光阻物质16相同的宽度，在层12上保留了相对窄的结构。如图1E所示，为光阻除去后的完成图。
可以被了解的是，图1A到图1E的特征并不是在此工艺所达成的特定形状，而是在使用修剪步骤以行成先前无法做到的小尺寸。例如，另一替代实施例可以产生如图1F的结构，其通过在图1C后对则整个结构进行蚀刻得到。此替代实施例会产生双层的次平板印刷结构，且其他的变化也应为业界所轻易想到的。此外，根据本发明实施例的工艺也可以消除平板印刷循环，导致时间及金钱方面的节省。
在任一情况下，最终蚀刻工艺应该满足以下的条件：第一，此工艺必须是非等向的，即其可以除去物质层却不会伤害到其上的光阻材料。它也应该对物质层与光阻材料之间有着良好的选择性。且此工艺必须有着高度的可控制性，以达到所需的公差程度。这些要求可以由本领域的技术人员实现。
图2至图5为应用此工艺来生产集成电路。每个图均包含一组示意图(如图2A和图2B)，分别显示集成电路的俯视图及侧视图，其为使用此工艺的随机存取存储器单元100的一部分。如图2A和图2B所示，此结构的较低基础部分101已为业界所熟知，有着衬底102，其上覆盖着介质填充材质104。共同源极线110在此单元中央，两个电极栓塞元件108在源极的两端自衬底向上延伸。两个字线106也通过此单元，通常在与附图垂直的方向上。在此显示的图式仅是一个实施例，其他的变化也可以使用于本发明。本领域的技术人员应能轻易明了本发明及其变化。
本发明还显示如何形成相变化存储单元的电极层。此相变化存储单元本身的详细介绍，可参阅美国专利申请No.11/155,067，发明名称为“Thin Film Fuse Phase Change RAM and Manufacturing Method(薄膜熔丝相变化随机存取存储器及其制造方法)”。
如图2B中所示，电极层112包括电极构件114、116和118，其彼此互相通过包括栏杆120、124和基底构件122的绝缘构件所分隔。基底构件122在实施例中比栏杆120、124厚，且将电极构件118与共同源极线110分离。例如，基底构件122在实施例中为80到140纳米，而栏杆却更窄，以减少在电极构件118与共同源极线110间的电容耦合。如实施例中所示，栏杆120、124包含薄的介质薄膜材料于电极构件114、116的侧壁，此电极层112的厚度由此侧壁的厚度来决定。
电极构件114、116和118可以包含任何具有高电导性及高实用性的物质。这些物质最好也可以作为相变化材质的障碍层。在一实施例中，最好是使用氮化钛(TiN)作为这些构件。类似地，在一实施例中，最好是使用氮化硅(SiN)作为这些绝缘构件120、122和124。这些构件的特定材料及其变化，且其制造技术均在之前提到的申请’067中有所讨论。
在此电极构件/绝缘构件上形成相变化材料层126、介质覆盖层128以及蚀刻掩模层130。此介质覆盖层128最好是氧化硅。此蚀刻掩模层130最好是业界所常用的光阻材料。如图2A中俯视图所示，此光阻材料完全覆盖住底层。此光阻的宽度(与此单元长轴横切的方向)，为此工艺所容许的最小特征尺寸F。在一实施例中，此最小特征尺寸为150纳米。而此相变化材料的厚度，在一实施例中介于10纳米到50纳米之间，最好是30纳米。也应注意的是，图2A也显示由光阻所曝露的材料非等向蚀刻后的结果。
此存储单元100中某些实施例所使用的相变化材料包含硫属化物(Chalcogenide)材料作为相变化元件126。硫属化物包括下列四元素中的任一种：氧(O)、硫(S)、硒(Se)、以及碲(Te)，形成元素周期表上第VI族的部分。硫属化物包括将一硫属元素与一更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其他物质如过渡金属等结合。硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素，例如锗(Ge)以及锡(Sn)。通常，硫属化合物合金包括下列元素中一个以上的复合物：锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已在技术文件中进行了描述，包括Ga/Sb，In/Sb，In/Se，Sb/Te，Ge/Te，Ge/Sb/Te，In/Sb/Te，Ga/Se/Te，Sn/Sb/Te，In/Sb/Ge，Ag/In/Sb/Te，Ge/Sn/Sb/Te，Ge/Sb/Se/Te及Te/Ge/Sb/S的合金。在Ge/Sb/Te合金族群里，有许多的合金组成可以使用。组成的特征在于TeaGebSb100-(a+b)，其中a及b代表占构成元素总原子数的原子百分比。一位研究员描述了最有用的合金为，在沉积材料中所包括的平均碲浓度远低于70％，典型地低于60％，并在一般类型的合金中的碲含量范围从最低23％至最高58％，且最佳为介于48％至58％得到碲含量。锗的浓度高于约5％，且其在材料中的平均范围从最低8％至最高30％，一般低于50％。最佳地，锗的浓度范围介于8％至40％。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比，其为所有组成元素总和为100％(Ovshinky‘112专利，栏10～11)。由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada，”Potential ofGe-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording”，SPIE v.3109，pp.28-37(1997))更一般地，过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金，可与锗/锑/碲结合以形成相变化合金，其包括有可编程的电阻性质。可使用的存储材料的特殊范例，如Ovshinsky‘112专利中栏11-13所述，其范例在此列入参考。
相变化合金能在此单元活性通道区域内依其位置顺序在材料为一般非晶态的第一结构状态与为一般结晶固体状态的第二结构状态之间切换。这些材料至少为双稳定态的。“非晶”一词指相对较无次序的结构，其比单晶更无次序性，而带有可检测的特征，如比结晶态更高的电阻值。“结晶态”指相对较有次序的结构，其比非晶态更有次序，因此包括有可检测的特征，例如比非晶态更低的电阻值。典型地，相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其他受到非晶态与结晶态的改变而影响的材料特中包括，原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物，提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质也可能随之改变。
相变化合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出，较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量够大，因此足以破坏结晶结构的键结，同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下，可决定特别适用于特定相变化合金的适当脉冲量变曲线。在本文的后续部分，此相变化材料以GST代称，同时应该了解，也可使用其他类型的相变化材料。用以实施在此所述的电脑存储器的材料为Ge2Sb2Te5。
其他可编程的电阻存储材料也可以使用于本发明的其他实施例中，包括N型搀杂相变化材料(GST)，GexSby，或是其他可用不同结晶相变化来决定电阻值；PrxCayMnO3、PrSrMnO、ZrOx或其他可用电子脉冲来改变电阻状态；TCQN，PCBM，TCNQ-PCBM，Cu-TCNQ，Ag-TCNQ，C60-TCNQ，TCNQ中搀杂其他金属，或是其他任何有着可用电子脉冲来控制的双相稳定或多重向稳定的电阻状态的高分子材料。
图3A和图3B显示此修剪的效果。由图中所示，光阻在水平的两个方向上被修剪，将其宽度(与此单元长轴横切的方向)减为50纳米，为一个小于最小特征尺寸的尺寸F’，同样地，将其长度减少为一个小于底层最小特征尺寸的尺寸。此步骤必须有着良好的选择性及可控制性，通常可通过干蚀刻方式实现。
下一步骤为使用此修剪过的光阻作为掩模进行蚀刻，其结果如图4A和图4B所示。由图中所示，此蚀刻步骤除去了裸露于修剪过光阻外的物质，蚀刻去掉此介质覆盖层和相变化材料层，直到此氮化钛(TiN)层114/116/118。此蚀刻步骤应该是非等向的，以避免相变化材料层被侧削，此蚀刻步骤必须对光阻层与介质/相变化材料层之间有着良好的选择性。在一实施例中，最好是使用离子反应蚀刻(RIE)技术。合适的反应气体包括氧(O2)、氟(F)或是其他业界所公知的化学物质。
最后，如图5A和图5B所示，将光阻除去。最好是将光阻除去，而不是将其留在衬底上，因为光阻的高分子物质会在后续工艺中劣化而影响了半导体元件的可靠性，且会产生十分难以处理的有机污染物。此光阻去除步骤最好是使用氧气(O2)等离子体，其后可在通过湿方式来帮助去除光阻，可使用如EKC265等有机溶剂。
最后完成的结构包括相变化材料层126以及介质覆盖层128，有着次平板印刷宽度尺寸，大约为50纳米。此单元结构可以进行后续的工艺步骤，如先前提过的’067申请所描述的一般。
虽然本发明已参照较佳实施例加以描述，应该所了解的是，本发明并不受限于其详细描述的内容。替换方式及修改方式已在先前描述中建议，并且其他替换方式及修改方式将为本领域的技术人员可想到的。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件结合而实现与本发明实质上相同结果的，皆不脱离本发明的精神范畴。因此，所有这些替换方式及修改方式意欲落在本发明所附的权利要求书及其等价物所界定的范畴中。

Claims (15)

1.一种在集成电路元件上制造结构的方法，包含：
形成第一材料层，其有着上表面；
在该第一材料层的该上表面上形成第二材料层；
施加蚀刻掩模于该第二材料层上，该蚀刻掩模确定出会在该第一材料层上形成的第一结构的图案；
根据该蚀刻掩模蚀刻该第二材料层和该第一材料层；
修剪该蚀刻掩模以形成修剪蚀刻掩模，该修剪蚀刻掩模定义出会在该第二材料层上形成的较窄第二结构的图案；以及
根据该修剪蚀刻掩模蚀刻该第二材料层，以形成该第二结构与该第一结构对准。
2.如权利要求1所述的方法，其中该蚀刻掩模包含光阻材料。
3.如权利要求1所述的方法，其中该蚀刻掩模包含光阻材料，且该修剪包括各向同性地蚀刻该光阻材料。
4.如权利要求1所述的方法，其中该施加蚀刻掩模的步骤包含有着最小特征尺寸F的平板印刷工艺，以定义有着相当于F的宽度的蚀刻掩模，且该修剪蚀刻掩模有着小于F的宽度。
5.如权利要求1所述的方法，其中该第一材料层包含有着上表面的电极层，该电极层包括第一电极构件以及第二电极构件，以及位于该第一电极构件与该第二电极构件之间的绝缘构件，该第一电极构件、该第二电极构件与该绝缘构件向该电极层的上表面延伸，且该绝缘构件在该上表面有着介于该第一电极构件与该第二电极构件之间的宽度。
6.如权利要求1所述的方法，其中该第二材料层包括位于该第一材料层的上表面的薄膜存储材料，以及位于该薄膜存储材料上的覆盖保护层。
7.一种制造存储器件的方法，包含步骤：
形成有着上表面电极层，该电极层包括第一电极构件以及第二电极构件，且有着位于该第一电极构件与该第二电极构件之间的绝缘构件，该第一电极构件、该第二电极构件与该绝缘构件向该电极层的上表面延伸，且该绝缘构件在该上表面有着介于该第一电极构件与该第二电极构件之间的宽度；
在该电极层横越该绝缘构件的该上表面形成存储材料薄膜，该存储材料薄膜有着第一端以及第二端，且与该第一电极构件与该第二电极构件在该第一端接触；
在该存储材料薄膜上施加蚀刻掩模，该蚀刻掩模定义出会在该第一电极构件与该第二电极构件形成的第一电极和第二电极的图案；
根据该蚀刻掩模蚀刻该存储材料薄膜和该电极层；
修剪该蚀刻掩模以形成修剪蚀刻掩模，该修剪蚀刻掩模定义出形成于该第一电极和第二电极上的该存储材料薄膜的较窄补钉图案；以及
根据该修剪蚀刻掩模蚀刻该存储材料薄膜，以与该第一电极和第二电极对准形成该补钉，该补钉定义出横越该绝缘构件介于该第一电极和第二电极之间的电极间通道，其有着由该绝缘构件宽度所定义的通道长度，其中该存储材料薄膜有着至少两个固态相。
8.如权利要求7所述的方法，其中该绝缘构件宽度小于50纳米，该形成补钉包括在正交于该电极层的该上表面的方向上形成厚度小于50纳米的薄膜。
9.如权利要求7所述的方法，其中该形成补钉步骤包括在正交于该电极层的该上表面的方向上形成厚度小于20纳米的薄膜。
10.如权利要求7所述的方法，其中该形成电极层步骤包括：
在衬底上形成介质层；
在该介质层上形成第一导体层；
在该第一导体层上蚀刻图案，该图案包括裸露于该衬底间的堆迭区域，且该衬底上的堆迭区域包括该介质层的剩余部分与该第一导体层的剩余部分，且该堆迭区域有着侧壁；
在该堆迭区域上形成侧壁介质层，且蚀刻该侧壁介质层以在该堆迭区域的侧壁上形成侧壁隔离；
在该堆迭区域之间和该侧壁隔离与该堆迭区域之间的区域上形成第二导体层；
蚀刻且平坦化该第二导体层以定义该电极层，其中该侧壁隔离被曝露于该上表面且作为该绝缘构件，在该堆迭区域中部份的该第一导体层曝露于该上表面且作为该第一电极，介于该堆迭区域之间区域部份的该第二导体层曝露于该上表面且作为该第二电极。
11.如权利要求10所述的方法，其中该蚀刻且平坦化步骤包含化学机械研磨。
12.如权利要求7所述的方法，包括将该电极层形成在衬底的表面，该衬底包含用于存取该存储单元的电路，该衬底的该表面包括一接触，而该电极层的该第二电极耦接至该接触。
13.如权利要求7所述的方法，还包括在该补钉上形成图案化导体层，且形成介于该第一电极与该图案化导体层间的接触。
14.如权利要求7所述的方法，其中该存储材料是含锗、锑和碲的组合物。
15.如权利要求7所述的方法，其中该存储材料是二种或二种以上选自由锗、锑、碲、硒、铟、钛、镓、铋、锡、铜、钯、铅、银、硫及金所组成的族群的材料组合。
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