CN101013736A - 管型相变存储器 - Google Patents
管型相变存储器 Download PDFInfo
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- CN101013736A CN101013736A CN200610146334.5A CN200610146334A CN101013736A CN 101013736 A CN101013736 A CN 101013736A CN 200610146334 A CN200610146334 A CN 200610146334A CN 101013736 A CN101013736 A CN 101013736A
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- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of switching materials, e.g. deposition of layers
- H10N70/026—Formation of switching materials, e.g. deposition of layers by physical vapor deposition, e.g. sputtering
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- H—ELECTRICITY
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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- H—ELECTRICITY
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
- H10N70/8265—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices on sidewalls of dielectric structures, e.g. mesa-shaped or cup-shaped devices
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
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- H10N70/841—Electrodes
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- H10N70/00—Solid-state devices having no potential barriers, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
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Abstract
一种存储器单元部分包括下电极,包括相变材料的管型部分及与管型部分接触的上电极。管型部分内侧有电绝缘及热绝缘材料。本发明还公开了包括管型相变存储器的集成电路。
Description
相关申请信息
本发明要求2005年11月14日申请题目为“管型相变存储器及其制造方法”的美国临时专利申请60/737,424的优先权。
联合研究合约的当事人
国际商业机械公司、台湾旺宏国际股份有限公司以及德国英飞凌技术公司(Infineon TechnologiesA.G.)为联合研究合约的当事人。
技术领域
本发明涉及基于可编程电阻材料,例如相变存储器材料的高密度存储器器件及制造这种器件的方法。
背景技术
硫属化物(Chalcogenide)材料广泛用于读写光盘。这些材料具有至少二种固相,通常为非晶态及通常结晶态。激光脉冲用于读写光盘以在这些状态之间切换及在相变后读取材料的光学性质。
硫属化物材料也可以通过施加电流而改变状态。这种特性则引发了使用可编程电阻材料来形成非易失性存储器电路等的兴趣。
目前发展的方向之一已经朝向利用少量可编程电阻材料,尤其是在微小孔洞中的绝缘材料。揭露朝向微小孔洞发展的专利有:Ovshinsky于1997年11月11日获准的美国专利No.5,687,112、发明名称为“Multibit Single Cell Memory Element Having Tapered Contact”的专利,Zahorik等人于1998年8月4日获准美国专利No.5,789,277、发明名称为“Method of Making Chalogenide[sic]Memory Device”的专利,Doan等人于2000年11月21日获准美国专利No.6,150,253,发明名称为“Controlable Ovionic Phase-Change Semiconductor MemoryDevice and Method of Fabricating the Same”的专利。
发明人的美国专利申请案公开No.US-2004-0026686-A1描述一种相变存储器器件,其中相变元件包括位于电极/电介质层/电极堆栈(stack)结构上的侧壁。通过使用电流使得相变材料在非晶态与结晶状之间进行变换来储存数据。电流使材料提高温度,并且使其发生状态改变。非晶态变成结晶状的变化通常是一种较低电流的操作。结晶态到非晶状的变化,在此称为重置(reset),通常是一种较高的电流操作。用于使相变材料从结晶态变化成非晶状的重置电流大小最好是越小越好。可以通过缩小单元中主动相变材料元件的尺寸的方式,来减小重置所需的重置电流值大小。相变存储器器件的相关问题之一是重置操作所必需的电流大小取决于必须改变相态的相变材料体积。因此,利用标准集成电路工艺制造的单元一直被制造设备的最小特征尺寸所限。因此,必须要开发出为存储器单元提供次光刻(sublithography)尺寸的技术,而该技术可能缺乏大规模高密度存储器器件所需的均匀性与可靠性。
因此,需要设计出一种利用可靠且可重复制造技术、以少量可编程电阻材料制造的存储器单元。
发明内容
本发明包括存储器器件及形成这种存储器单元器件的方法,其中存储器器件包括下电极,位于下电极上的填充层,从填充层上表面延伸至下电极上表面的过孔(via),以及在过孔中由例如相变材料之类的可编程电阻材料做成的共形层(conformal layer)。共形层与下电极接触,并沿着过孔侧边延伸至上表面,在过孔内形成管型部分(pipe-shaped member)。与共形层接触的上电极重叠于填充层上。电绝缘及热绝缘材料填满过孔的其余部分。代表性的绝缘材料包括有基本真空的空洞或者低导热性固态材料,例如二氧化硅,或导热性远小于二氧化硅的材料。
本发明还包括一种制造管型相变存储器单元的方法,包括形成具有上表面的下电极,并且在下电极上形成填充层,其中过孔从填充层上表面延伸至下电极上表面。在过孔中沉积可编程电阻材料的共形层,其从下电极上表面沿着过孔侧边延伸至填充层上表面。最后,在填充层上形成与共形层接触的上电极。在实施例中,形成下电极的步骤及形成填充层的步骤包括:首先在存取器件端子上形成填充层。然后,在所述填充层中形成过孔,其穿透填充层至端子。然后在过孔内填满导体,以形成导电栓塞(plug)。然后将导体部份地从过孔移除,使得过孔中的导电栓塞的其余部分作为下电极,并且通过移除导电材料而曝露出的过孔部份作为其中沉积共形层的过孔。
本发明还公开了一种包括存储器阵列的集成电路,其包括多个以具有多个行和列的高密度阵列方式排列的、具有存取晶体管的存储器器件。存取晶体管包括位于半导体衬底中的源极和漏极区域,以及沿着存储器单元的行耦接到字线上的栅极。存储器单元形成于集成电路的存取晶体管上的一个层内,其中下电极与对应存取晶体管的漏极接触。利用金属化层在存储器器件上形成位线,其沿着阵列中的存储器储器单元的列与存储器器件上的上电极接触。在实施例里,二行存储器单元共享源极接触,公共源极线耦接到源极接触并且通常经过阵列平行地延伸至字线。
本发明还提供了低重置电流的可靠的存储器单元结构,其利用标准光刻与沉积工艺制造,不需要形成次光刻图案的特别技术。该单元结构尤其适合于在大规模集成电路器件上与CMOS电路集成。
以下详细说明本发明的结构与方法。本发明内容说明章节目的并非在于定义本发明。本发明由附带的权利要求所定义。本发明的实施例、特征、观点及优点等都可以通过下列说明及附图获得充分了解。
附图说明
图1示出了基于可编程电阻材料管型部分的存储器元件的实施例的剖面图;
图2示出了基于可编程电阻材料管型部分的存储器元件的实施例的立体视图;
图3示出了包括如图1所示的存储器元件的存储器阵列的电路示意图;
图4示出了包括管型相变存储器阵列和其他电路的集成电路的方框图;
图5示出了根据本发明的实施例的最终阵列结构的剖面图;
图6到13示出了管型相变存储器元件的制造方法的各个阶段;
图14示出了用于描述存储器元件中电流及主动区域的管型相变存储器元件;以及
图15示出了管型相变存储器元件的阵列的布局。
【主要元件符号说明】
10 管型相变存储器单元
11 下电极
12 管型部分
13 绝缘材料
14 管型部分的顶部
15 封闭端子
36 导桥
12a 内表面
28 公共源极线
23,24 字线
41,42 位线
50,51,52,53 存取晶体管
35,36 管型存储器单元
32,33 下电极部分
34,37 上电极部分
75 集成电路
74 其它电路
60 存储器阵列
61 行解码器
62 字线
63 列解码器
64 位线
65 总线
66 感测放大器及数据输入结构
67 数据总线
68 供应电压
69 偏压排列状态机制
71 数据输入线
72 数据输出线
100,101,102,103 管型相变随机存储器单元
110 半导体衬底
111,112 电介质沟道
116 公共源极区域(掺杂区域)
115,117 漏极区域(掺杂区域)
113,114 多晶硅字线
118 电介质填充层
121,120 栓塞结构(下电极)
119 公共源极线
122,123 金属层(接触层)
124 绝缘层
101 单元
99 结构
131,132,134,135 栓塞
130 填充层上表面
133 金属线(多晶硅字线)
140 绝缘填充层
141,142,144,145 过孔
148 可编程电阻材料共形层
149 绝缘填充层
150 管型部分的顶部
151 绝缘填充层
200 下电极
210 上表面
201 管型部分
202 接触层
203 位线层
204 接口材料
205,206,207 重置期间的电流
208,209 主动区域
300 接地线300
301,302 位线
303,304 位线
311,312,313,314 管型相变单元
具体实施方式
图1示出了管型相变存储器单元10的剖面示意图。该单元包括下电极11以及管型部分12,其中管型部分12包括可编程电阻材料。管型部分12充满绝缘材料13,该绝缘材料13优选地具有低导热性。上电极(未示出)与管型部分的顶部14电性耦接。在实施例里,管型部分具有封闭端子15,该端子与下电极11的上表面电性耦接。管型部分内的填充材料13可包括氧化硅、氧氮化硅、氮化硅、Al2O3,其它低k值(低介电常数)的电介质材料,或ONO或SONO多层结构。可替换地,填充材料可以包括电绝缘体,该电绝缘体包括选自由硅(Si)、钛(Ti)、铝(Al)、钽(Ta)、氮N及碳(C)所组成的组中的一个或者多个元素。在优选器件中,填充部份具低导热性,小于约0.014J/cm*degK*sec。代表性的热绝缘材料包括具有硅(Si)、碳(C)、氧(O)、氟(F)及氢(H)等的组合。做为热绝缘覆盖层的热绝缘材料例如包括氧化硅(SiO2)、SiCOH、聚酰胺(polyamide)以及氟碳聚合物。作为热绝缘覆盖层的材料的其它实例包括氟氧化硅、硅氧烷(silsesquioxane)、聚环烯醚(polyarylene ether)、对二甲苯聚体(parylene)、氟聚合物、氟化无定型碳、金刚石类碳、多孔性氧化硅、中孔性氧化硅(mesoporous silica)、多孔性硅氧烷、多孔性聚亚酰胺及多孔性环烯醚。在其它实施例里,热绝缘结构包括位于在横跨导桥36上的电介质填充材料中以提供热绝缘作用的填充空气的空洞。管中的单层或多层可以提供热绝缘及电绝缘作用。
在实施例中,管型部分没有填充固态材料,而是采用上电极封闭,而留有基本抽真空的空洞,因而管型部分具有低导热性的空洞。
管型部分包括内表面12a以及外表面12b,内表面12a及外表面12b为圆筒状。因此,内侧及外表面12a及12b可以是基本上为柱状表面,其典型定义为由平行于固定的线移动及与固定曲线相交的线的轨迹所描绘出的表面,其中对于圆柱体而言,固定线位于管型部分中心处而固定曲线为固定线位于其中心处的圆形。该圆柱体的内侧及外表面12a及12b由各自的、具有根据管型部分的壁厚度而不同的半径的圆圈所定义,因此内侧及外表面12a及12b定义出管型部分的内侧及外侧直径。在管型部分的实施例中,柱体形状具有圆形、椭圆形、矩形或不规则形的外周缘,取决于用以形成管型部分的制造技术而定。
在此所述的实施例中,管型部分通过形成于开设在填充层内的过孔的侧边上、类似过孔衬垫(liner)材料(例如氮化钛(TiN))薄膜的沉积的薄膜,来形成钨栓塞以达到改善钨的黏附性的目的。因此,管型部分的壁可以非常薄,其由用于在过孔内沉积薄膜的工艺决定。同样地,下电极11可以包括导体,如过孔内所沉积的钨。
图2示出了图1的单元的立体图,其中割除部份示出了固体填充部份。图2中管型部分为具圆形外缘形状的圆柱体。另一个实施例中,外缘形状基本上是方形或矩形的。通常,管型部分12的外缘形状由管型部分12形成在其中的过孔的形状以及形成过孔的方法决定。
在此所述的管型单元10可利用标准光刻及薄膜沉积工艺制造,不需要特殊步骤形成次光刻图案,并且同时可以实现非常小尺寸的单元区域,其中该单元区域实际上在编程期间改变其电阻系数。可编程电阻材料包括相变材料,例如Ge2Sb2Te5或其它以下所描述的材料。单元10中相变区域很小,因此,相变所需的重置电流很小。
存储器单元的实施例包括用于管型部分12的基于相变材料的存储器材料,其包括基于硫属化物的材料及其它材料。硫属化物包括下列形成元素周期表上第VI族的部分的四种元素之中任意一种:氧(O)、硫(S)、硒(Se)、以及碲(Te)。硫属化物是将硫属元素与更为正电性的元素或自由基结合而得到。硫属化合物合金是将硫属化合物与例如过渡金属等的其它物质结合。硫属化合物合金通常包括一个以上的选自元素周期表第六栏的元素,例如锗(Ge)以及锡(Sn)。通常,硫属化合物合金包括下列元素中一个以上的复合物:锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变为基础的存储器材料已经在技术文件中进行了描述,包括下列合金:Ga/Sb,In/Sb,In/Se,Sb/Te,Ge/Te,Ge/Sb/Te,In/Sb/Te,Ga/Se/Te,Sn/Sb/Te,In/Sb/Ge,Ag/In/Sb/Te,Ge/Sn/Sb/Te,Ge/Sb/Se/Te及Te/Ge/Sb/S。在Ge/Sb/Te合金族群里,有许多的合金组成可以使用。组成的特征在于TeaGebSb100-(a+b),其中a及b代表占构成元素总原子数的原子百分比。一位研究员描述了最有用的合金为:在沉积材料中所包含的平均碲浓度远低于70%,典型地低于60%,并且碲含量通常在从最低23%至最高58%的范围内,且最佳地是介于48%至58%的碲含量。锗的浓度高于约5%,且其在材料中的平均范围从最低8%至最高30%,一般为低于50%。最佳地,锗的浓度范围介于8%至40%。在此成分中所剩下的主要成分则为Sb(Ovshinky‘112专利,栏10~11)。由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7(Noboru Yamada,“Potential of Ge-Sb-Te Phase-change Optical Disks forHigh-Data-Rate Recording”,SPIE v.3109,pp.28-37(1997))。更一般地,过渡金属例如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金,可与锗/锑/碲结合以形成相变合金,其具有可编程的电阻特性。可使用的存储器材料的特殊示例如Ovshinsky‘112专利中栏11-13所述,在此引入该示例作为参考。
在此存储器单元的活性沟道区域中,相变合金可在第一结构态与第二结构态之间按照其局部次序进行切换,其中第一结构态一般为非晶固态(amorphous solid phase),而第二结构态一般为结晶固态(crystalline solid phase)。这些相变材料至少是双稳态的(bistable)。术语“非晶”用于指示相对较无次序的结构,其与单晶相比更加无次序性,而具有可检测的特征,例如与结晶态相比具有更高的电阻值。术语“结晶态”用于指示相对较有次序的结构,其与非晶态相比更有次序,因此包括可检测的特征,例如比非晶态更低的电阻值。典型地,相变材料可以在完全结晶态与完全非晶态之间的所有可检测的不同状态之间进行电切换。其它受到非晶态与结晶态之间的改变的影响的材料特征包括:原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态,或者可切换成为由两种以上固态所形成的混合物,提供从完全非晶态与完全结晶态之间的灰度级部分。此材料中的电特性也可能随之改变。相变材料可通过施加电脉冲而从一种相态切换至另一种相态。先前观察指出,较短、较大幅度的脉冲倾向于将相变材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量足够大,因此足以破坏结晶结构的结合键,同时其足够短,因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下,可以确定特别适用于特定相变合金的适当的脉冲量变曲线。
在本文的后续部分,此相变材料称为GST,同时应该理解的是,也可以使用其它类型的相变材料。在本文中所描述的一种适用于相变元件中的材料为Ge2Sb2Te5。
可编程电阻材料的有用特征,例如相变材料,包括可编程电阻材料,并且为了实现可编程,优选地采用可逆方式,例如可以具有能够用电流进行可逆地诱发的至少两个固相。所述至少二个固相包括非晶相及结晶相。然而,在操作中,可编程电阻材料可以不完全转化成非晶相或结晶相。中间相或这些相混合在材料特征上具有具有可被侦测到的差异。这二个固态相一般应为双稳态且具有不同电性质。可编程电阻材料可以是硫属化物。硫属化物可以包括GST。或者,可编程电阻材料可以是上述其它相变材料其中一种。
图3是在此实现的存储器阵列的示意图。在图3中,公共源极线28、字线23以及字线24通常设置于Y方向。位线41及42通常设置于X方向。因此,方块45中的Y解码器与字线驱动器耦接至字线23及24,而方块46中的X解码器与一组感测放大器耦接至位线41及42。公共源极线28耦接到存取晶体管50,51,52及53的源极端点。存取晶体管50的栅极耦接至字线23。存取晶体管51的栅极耦接至字线24。存取晶体管52的栅极耦接至字线23。存取晶体管53的栅极耦接至字线24。存取晶体管50的漏极耦接管型存储器单元35(也具有上电极部分34)的下电极部分32。上电极部分34耦接至位线41。同样地,存取晶体管51的漏极耦接至管型存储器单元36(也具有上电极部分37)的下电极部分33。上电极部分37耦接至位线41。存取晶体管52及53耦接至对应的管型存储器单元并且还耦接至位线42上。可以看出公共源极线28是由二行存储器单元共享的,其中一行位于示意图中的Y方向。在其它实施例里,存取晶体管可以由二极管替代,或者由用于对用于读取及写入数据的阵列中的选定器件进行电流控制的结构替代。
图4是根据本发明的实施例的集成电路的简化电路方框图。集成电路74包括利用半导体衬底上管型相变存储器单元实现的存储器阵列60。行解码器61耦接至多个字线62,并且沿着存储器阵列60的行向排列。列解码器63耦接至多个位线64,并且沿着存储器阵列60的列向排列,用于从阵列60中的侧壁管脚存储器单元中读出并编程数据。将地址通过总线65提供给列解码器63及列解码器61。在方框66中的感测放大器以及数据读入(data-in)线路经过数据总线67耦接至列解码器63。数据从集成电路75上的输入/输出端口,或者从集成电路75的其它内部或外部数据源,经由数据输入线路71而提供到方框66的数据输入结构。在所示的实施例中,在集成电路上包括其它电路,如通用目的处理器或特定目的应用电路,或者由薄膜相变存储器单元阵列所支持的、可提供片上系统(system on a chip)功能的整合模块。数据经数据输出线72从方块66内的感测放大器输出至集成电路75上的输入/输出端口,或输出至集成电路75内部或外部的数据端子。
在本实施例中使用偏压排列状态机制69的控制器控制偏压排列供给电压68的应用,例如读取、程序化、擦除、擦除确认与程序化确认电压等。该控制器可使用已知的特定目的逻辑电路来实现。在可替代实施例中,该控制器包括通用目的处理器,其可应用于同一集成电路中,该集成电路执行计算机程序而控制该器件的运行。在另一个实施例中,该控制器使用了特定目的逻辑电路以及通用目的处理器的组合。
图5是多个管型相变随机存取存储器单元100-103的剖面图。单元100-103形成在半导体衬底110上。诸如浅沟渠隔离STI电介质沟渠111及112之类的隔离结构将成对的存储器单元存取晶体管行隔离。由衬底110中的公共源极区域116与衬底110中的漏极区域115及117形成存取晶体管。多晶硅字线113及114形成该存取晶体管的栅极。电介质填充层118形成在多晶硅字线113,114上。接触栓塞结构121及120与各自的读取晶体管的漏极接触,公共源极线119沿着阵列中的行与源极区域接触。公共源极线119接触公共源极区域116,并且公共源极线119包括将其与金属层122,123隔离的绝缘层124。栓塞结构120作为单元101的下电极。栓塞结构121作为单元102的下电极。单元101,同单元100,102及103一样,包括含有GST或图1所示另一相变材料的管型部分。经过图案化的金属层提供单元100-103的上电极,包括含有用于接触GST的材料(例如TiN)的第一接触层122,以及利用标准金属化工艺(包括例如Cu或Al为主的金属)所形成的第二层123。
在代表性实施例中,栓塞结构包括钨栓塞。其它类型的导电性金属也可以使用,包括例如铝及铝合金,氮化钛(TiN),氮化钽(TaN),氮化钛铝(TiAlN)或氮化钽铝(TaAlN)。可以使用的其它导体包括一种或多种选自钛(Ti),钨(W),钼(Mo),铝(Al),钽(Ta),铜(Cu),铂(Pt),铱(Ir),镧(La),镍(Ni),钌(Ru)及氧(O)组成之组群中的元素。
图6-13为图5所示的管型存储器单元的制造过程图。图6是在前段(front-end-of-line)制造过程后的结构99,在所述具体实施例中对应于字线形成标准CMOS器件,以及图5所述阵列中的存取晶体管。此外,还包括栓塞131,132,134及135,其形成于对应的过孔中,所述过孔经由填充层118,并从填充层上表面130延伸至对应的存取晶体管的漏极端子(115,117)。金属线133形成于填充层118内的沟渠里,并沿着字线113及114之间的存取晶体管的行进行延伸。在制造过程的实施例里,金属线133及栓塞131、132、134及135都是利用标准钨栓塞工艺形成的,并且具有由用于对栓塞的过孔进行图案化的光刻工艺所定义的尺寸。在图6里,金属线133位于半导体衬底内的掺杂区域116上,其中掺杂区域116对应图标左侧的第一存取晶体管的源极端子,及图标右侧的第二存取晶体管的源极端子。在该阶段时,金属线133延伸至填充层118的上表面130。掺杂区域115对应于第一存取晶体管的漏极端子。包括多晶硅的字线113,及硅化物帽盖(cap)(未示出),作为第一存取晶体管的栅极。填充层118包括电介质材料,例如二氧化硅,并且位于多晶硅字线113上。栓塞132接触掺杂区域115,并且延伸至结构99的表面130。第二存取晶体管的漏极端子由掺杂区域117提供。包括多晶硅线114的字线,及硅化物帽盖(未示出)作为第二存取晶体管的栅极。栓塞134接触掺杂区域117并且延伸至结构99的上表面130。隔离沟渠111及112使包括漏极端点115及117的双晶体管结构从相邻的双晶体管结构分离。
图7为制造过程的下一阶段。在图7所示的阶段里,利用标准光刻工艺形成包括掩膜136及137的光阻图案。掩膜136及137保护栓塞132,133,134,135并且使金属线133的顶部曝露出来。对金属线133的顶部进行回蚀刻(etch back),使得剩余结构的表面138低于填充层118的上表面130。剩余结构变成第5图所示的源极线119。回蚀刻工艺可以钨金属的基于氟的反应性离子蚀刻工艺进行。在回蚀刻后,移除光阻掩膜136及137,且如图8所示,将绝缘填充层140沉积于剩余结构上,填充沟渠至超过源极线119。绝缘薄膜可以包括二氧化硅或利用其他本领域技术人员已知的化学气相沉积、等离子增强化学气相沉积、高密度等离子化学气相沉积等所沉积的电介质材料。
下一个制造过程阶段在图9中示出,在利用化学机械抛光等移除绝缘层140至填充层118的表面130下之后,在源极线119上留下绝缘材料140的栓塞。
如图10所示,接着,进行回蚀刻,以从栓塞131,132,134,135移除图9的抛光阶段后露出的金属。可以利用上述移除钨金属栓塞所使用的基于氟的离子蚀刻的方式进行回蚀刻。回蚀刻在由回蚀刻工艺后所剩钨栓塞形成的下电极120,121上,留下过孔141,142,144,145。在各实施例中,栓塞120,121的高度约为100nm,栓塞宽度约为80nm。该实施例中,回蚀刻后留下的过孔141-145的深度小于200nm。
图11为例如通过溅镀将GST或其它可编程电阻材料的顺形层148在填充层内的过孔141-145上进行沉积后形成的结构。GST可以利用在约250℃以准直溅镀(sputter with collimation)方式沉积。或者,GST可以利用金属有机化学气相沉积(MO-CVD)工艺沉积。在代表性实施例里,顺形层148包括薄膜,该薄膜的厚度从上表面算起约60-80nm,过孔的侧边上的厚度小于30nm,典型约为10-30nm,顺形层148包括在过孔的底部的层。材料共形于过孔的壁上,且如图11的截面所示,过孔中的阴影区域表示材料没有填满过孔,而是在上述过孔壁上留下管型部分。在另一技术里,可以使用原子层沉积或化学气相沉积形成层148,视所选可编程电阻材料及所期望的单元尺寸而定。
图12为下一个阶段,将绝缘填充层149沉积在图11所示的结构上。在实施例里,填充层149包括利用低于约200℃的工艺温度在可编程电阻材料上形成的低温衬垫绝缘体,例如氮化硅层或氧化硅层(未示出)。一种适当的低温制造工艺利用等离子增强化学气相沉积PECVD涂覆氧化硅。在形成衬垫后,利用较高温度制造工艺,例如氧化硅或其它类似材料的高密度等离子HDP CVD完成电介质填充层149。
如图13所示,使用氧化物化学机械抛光CMP工艺平坦化结构的表面130或该表面附近,并暴露管型部分的顶部(例如150),在管型部分里面留下绝缘填充层151,并且暴露出源极线119上的绝缘体140。在CMP后,利用位线进行金属化制造过程以定义上电极,如图5所示。
图14为管型相变存储器单元的剖面图,其中管型相变存储器单元包括下电极200,包括接触下电极200的上表面210的管型部分201,包括接触层202及位线层203的上电极。该实施例里,管型部分201被填满电介质材料204,例如二氧化硅,或更加优选地为导热性比二氧化硅低的电介质材料。箭头205,206及207说明所示实施例里重置期间的电流。电流从与下电极200接触的存取部分的端子,向上流向管型部分201的侧边,最后经由包括层202及203的金属线流出。主动区域通常在以方块208,209表示的区域中,并且在由于电流通过而发热进而发生相变的相变材料中,主动区域位于管型部分远离下电极200侧边的上方。该单元的特征是通过避免下电极200与管型部分201之间的界面处发生相变的方式来提高可靠性。同样地,该特征建立一个小区域,其中相变材料是主动的,由此降低重置所需的电流大小。
在所述的实施例里,在单元周边的管型部分的侧边是连续的。或者,可以使用沉积技术使得管型部分的侧边不连续,进一步减小主动区域208,209内相变材料的体积。
图15为包括如图5所示的管型相变存储器单元的存储器阵列的布局。阵列包括接地线300,及位线301,302,这些线平行配置。位线303及304正交于字线301,302。管型相变单元311,312,313,314位于位线303,304底下,相邻于字线。如图所示,该实施例里的管型部分为方柱体或长柱体。如上所述,管型部分可以是圆柱体或其它形状,视形成过孔期间所用的制造技术而定。在优选实施例里,利用标准光刻工艺制造的单元具有的尺寸与用于形成过孔的制造过程的最小特征尺寸,而不需要形成次光刻掩膜。
虽然已经参考优选实施例对本发明进行了描述,但是应该理解的是,本发明并非限制于所述内容。先前描述中已经建议了可替换方案及修改方式,并且其它可替换方案及修改方式是本领域技术人员能够想到的。特别是,根据本发明的结构与方法,所有具有实质上相同于本发明的构件组合从而实现与本发明实质上相同的结果的技术都不脱离本发明的精神范畴。因此,所有这些可替换方案及修改方式都会落在本发明的附带的权利要求以及等价物所界定的范围中。
Claims (16)
1.一种存储器器件,包括:
下电极,其具有上表面;
管型部分,其包括相变材料;以及
上电极,与所述管型部分接触。
2.如权利要求1所述的存储器器件,还包括:
填充层,其位于所述下电极之上,包括具有侧边的过孔,所述过孔自所述填充层的上表面延伸至所述下电极的上表面;以及
其中所述管型部分在所述过孔内包括可编程电阻材料共形层,所述共形层与所述下电极接触并且沿着所述过孔侧边延伸至所述下电极的上表面并与所述上电极接触。
3.如权利要求1所述的存储器器件,其中,所述管型部分具有圆筒形的内表面及外表面,并且在所述管型部分的内表面里的上电极之下包括有热绝缘空洞。
4.如权利要求1所述的存储器器件,其中,所述管型部分具有圆筒形的内表面及外表面,并且在所述管型部分的内表面里包括导热性小于所述相变材料以及所述下电极的材料。
5.如权利要求1所述的存储器器件,其中,所述管型部分具有圆筒形的内表面及外表面,并且在所述管型部分内表面里包括电绝缘材料,所述电绝缘材料的导热性小于0.014J/cm*degK*sec。
6.如权利要求1所述的存储器器件,还包括:
填充层,其位于所述下电极之上,包括具有侧边的过孔,所述过孔从所述填充层的上表面延伸至所述下电极的上表面;
其中所述管型部分在所述过孔里面包括可编程电阻材料层,且所述下电极包括部份地填充所述过孔的导电栓塞。
7.如权利要求1所述的存储器器件,其中,所述管型部分具有圆筒形的内表面及外表面,所述内表面与所述外表面之间的厚度小于30nm。
8.如权利要求1所述的存储器器件,还包括:
填充层,其位于所述下电极之上,包括具有侧边的过孔,所述过孔从所述填充层的上表面延伸至电极的上表面;
其中所述管型部分在所述过孔中具有可编程电阻材料层,所述过孔从所述填充层上表面至所述下电极上表面的深度小于200nm。
9.如权利要求1所述的存储器器件,其中,所述相变材料包括硫属化物。
10.如权利要求1所述的存储器器件,其中,所述相变材料具有至少二个可由电流引发可逆的固态相。
11.如权利要求1所述的存储器器件,其中,所述相变材料具有至少二个固态相,包括通常为非晶相及通常为结晶相。
12.如权利要求1所述的存储器器件,其中,所述相变材料包括Ge2Sb2Te5。
13.如权利要求1所述的存储器器件,其中,所述相变材料包括选自由锗(Ge)、锑(Sb)、鍗(Te)、硒(Se)、铟(In)、及钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)银(Ag)、硫(S)及金(Au)所组成的组的二种或二种以上材料的组合。
14.一种存储器器件,包括:
下电极,其具有上表面;
填充层,其位于所述下电极之上,包括具有侧边的过孔,所述过孔从所述填充层上表面延伸至电极上表面;
可编程电阻材料共形层,其位于所述过孔中,与所述下电极接触并且沿着所述过孔侧边延伸至所述下电极的上表面;以及
上电极,其与所述填充层上的共形层接触。
15.一种集成电路,包括:
半导体衬底;
存取晶体管阵列,所述存取晶体管具有在所述半导体衬底中的、包括掺杂区域的端子,所述端子用于将各自的漏极端子耦接至参考电压;
多个字线,所述字线沿着所述存取晶体管阵列内各自的行耦接至所述存取晶体管的栅极端子;
可编程存储器单元阵列,所述阵列中的可编程存储器单元分别包括具有上表面的下电极、包括与下电极接触的可编程电阻材料的管型部分,以及与所述管型部分接触的上电极;以及
多个位线,位于所述存储器单元阵列上,沿着所述可编程存储器单元阵列的各列存储器单元配置并且接触或作为上电极。
16.如权利要求15所述的集成电路,其中,所述阵列中的可编程存储器单元中至少一个包括位于所述下电极上的填充层,所述填充层包括具有侧边的过孔,所述过孔从填充层上表面延伸至所述电极的上表面;位于过孔中的可编程电阻材料的共形层,所述共形层与所述下电极接触并且沿着所述过孔侧边延伸至所述下电极的上表面且与所述上电极接触。
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CN1967897B (zh) | 2010-08-04 |
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US20070108429A1 (en) | 2007-05-17 |
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