CN101017824A - 半导体结构及其形成方法 - Google Patents

半导体结构及其形成方法 Download PDF

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CN101017824A
CN101017824A CNA2006101433212A CN200610143321A CN101017824A CN 101017824 A CN101017824 A CN 101017824A CN A2006101433212 A CNA2006101433212 A CN A2006101433212A CN 200610143321 A CN200610143321 A CN 200610143321A CN 101017824 A CN101017824 A CN 101017824A
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stress
gate
gate stack
lamination
semiconductor structure
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朱慧珑
布鲁斯·B·多丽丝
王敬
任志斌
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明公开了一种半导体结构及其制造方法，包含相邻的pMOSFET和nMOSFET器件，其中栅叠层分别被应力层重叠，该应力层在pMOSFET器件的沟道内提供压应力，在nMOSFET器件的沟道内提供张应力。该pMOSFET或nMOSFET器件之一的高度小于另一个相邻的器件，两个器件中较低的一个由覆盖该较低器件的应力层内的不连续或开口界定。在用于形成该器件的优选方法中，单个应力层形成于具有不同高度的栅叠层上，从而在该栅叠层下方的衬底内形成第一类型应力，并在与较低栅叠层距离一定间距的该应力层内形成开口，使得第二类型应力形成于该较低栅叠层下方。

Description

半导体结构及其形成方法
技术领域
本发明总地涉及半导体器件工艺技术，更具体而言涉及通过使用单应力内衬而非双应力内衬以改善CMOS器件性能和可靠性的方法和结构。
背景技术
最近，已经提出双应力内衬(DSL)技术以在P型MOSFET器件中形成不同于N型MOSFET器件中的应力。例如，第一类型的氮化物内衬形成于CMOS器件的pMOSFET上，而第二类型的氮化物内衬形成于该CMOS器件的nMOSFET上。更具体而言，已经发现，在pMOSFET沟道内沿电流的方向施加压应力可改善载流子即空穴在其中的迁移率，而在nMOSFET沟道内施加张应力可改善载流子即电子在其中的迁移率。因此，pMOSFET器件上的第一类型氮化物内衬被形成以获得压应力，而nMOSFET器件上的第二类型氮化物内衬被形成以获得张应力。
对于采用双内衬的这种CMOS器件，传统的方法是使用分离的光刻图案化步骤以形成这两种不同的氮化物。换而言之，例如，第一类型的氮化物内衬形成于pMOSFET和nMOSFET器件上，该nMOSFET器件上的第一类型的氮化物内衬部分之后被图案化并除去。在可选地形成氧化物层之后，第二类型的氮化物内衬形成这两个区域上，使用第二图案化步骤随后除去该pMOSFET器件上的第二类型的氮化物内衬部分。不幸的是，由于与将光刻水平与先前水平对准相关联的固有误差，该两个内衬的形成可能导致在其间形成间隙或欠重叠(underlap)。具体地，这种间隙会导致随后蚀刻用于金属接触通路的孔时出现问题，因为在该蚀刻期间，欠重叠/间隙区域内的硅化物将被过蚀刻。这将反过来增大硅化物的薄层电阻。
另一方面，这两个内衬还可以形成为一个内衬重叠另一个内衬。实际上，用于该两个分离的图案化步骤的分划板通常设计来确保重叠，使得该两个内衬材料之间没有间隙。然而，使特定区域具有重叠的氮化物内衬会使后续工艺由于例如可靠性与布局低效率的问题而产生其他问题。例如，用于后续接触形成的反应离子蚀刻(RIE)工艺在电路的一些区域中必须考虑单厚度的内衬，而在界面区域必须考虑双厚度(重叠的)内衬。此外，如果将这些重叠区域排出在形成接触之外，则从可利用的布局面积以及临界尺寸(CD)容差方面而言形成了限制。该重叠还将在随后蚀刻用于金属接触通路的孔期间产生问题，因为在该蚀刻期间，除了重叠区域下方的硅化物之外，所有硅化物都将被过蚀刻。这会增大器件的薄层电阻和结漏电流。
因此，期望能够实施应力CMOS器件的形成，而避免上面讨论的与双应力内衬的错位有关的问题。
发明内容
现有技术的前述缺点和缺陷通过用于形成用于互补金属氧化物半导体(CMOS)器件的单应力内衬的方法而被克服或减缓。在示范性实施方案中，该方法包括：1)形成具有nMOSFET和pMOSFET的CMOS结构，该nMOSFET和pMOSFET具有不同的栅极高度(例如，nMOSFET的栅极可低于pMOSFET的栅极或者相反)；2)在该nMOSFET和pMOSFET上形成压应力或张应力的单应力内衬；以及3)蚀刻靠近较短栅极的应力内衬部分以在较短栅极的沟道内形成相反类型的应力。例如，如果首先形成压应力且较短的栅极为nMOSFET，则蚀刻靠近该nMOSFET的压应力内衬部分将在nMOSFET的沟道内形成张应力。如果较短的栅极为pMOSFET，则根据本发明，张应力内衬沉积于两个栅极上，较短pMOSFET周围的应力内衬部分被除去，导致在pMOSFET的沟道内形成压应力。
附图说明
参考示范性图示进行描述，其中在多个图示中使用相同的符号表示相同的元件。
图1至10阐述了用于形成根据本发明实施方案的nMOSFET和pMOSFET的示范性工艺的步骤，其中一个栅极叠层的高度小于另一个栅叠层；
图11阐述了根据本发明形成的应力层内，应力与从高度较小的栅导体到开口边缘的水平距离Lcut之间函数的曲线图；以及
图12至13阐述了根据本发明实施方案，用于形成nMOSFET和pMOSFET的图10之后的另外步骤，其中一个栅叠层的高度小于另一个栅叠层。
具体实施方式
本说明书中公开了通过使用用于nMOSFET和pMOSFET的单应力氮化硅内衬而改善CMOS器件性能和可靠性的方法与结构。简而言之，这里所公开的实施方案通过使用相同的应力膜覆盖pMOSFET和nMOSFET，以在位于相同芯片或集成电路(IC)上的pMOSFET沟道内形成压应力并在nMOSFET沟道内形成张应力。由于nMOSFET和pMOSFET的局部应力这样导致性能增强，而不引起错位问题。
最初参考图1，图中示出了半导体衬底100的剖面视图，该半导体衬底100具有被其间形成的例如浅沟槽隔离(STI)的隔离区105相分隔的nMOSFET器件区域102和pMOSFET器件区域104。
参考图2，栅电介质层106形成于包含隔离区105的衬底100上。栅电介质106可以是任何合适的电介质材料，例如二氧化硅。栅电介质106例如可通过热氧化或沉积高K材料而形成。栅电介质106通常具有约1至2nm的厚度范围。根据本发明，第一栅导体层108形成于栅电介质层106的顶部上。该第一栅导体层108可以是任何合适的栅导体材料，例如多晶硅、W、Ta或SiGe，通常更多地为多晶硅。对于35至45nm的栅长度，多晶硅层108优选地厚为10至30nm。蚀刻速率不同于第一栅导体层108的第二栅导体层110沉积在第一栅导体(例如多晶硅)层108顶部上，如果第一导体层为多晶硅，第二导体层比如为多晶硅-锗(多晶SiGe)。对于35至45nm的栅长度，该多晶SiGe层110优选地厚70至90nm。优选地，第二栅导体层110厚于第一栅导体108。
参考图3，通过现在已知或者将来发展的工艺形成器件102、104。如本领域技术人员将理解的，例如通过下述步骤可以形成栅叠层：图案化蚀刻，形成包含可选的薄氧化物内衬112和氮化物间隙壁114的间隙壁，以及注入而形成源/漏晕区和扩展116，随后进行源/漏退火。
参考图4，pMOSFET 104被诸如光致抗蚀剂层126的掩模覆盖。接着，例如通过对硅、多晶硅、氧化物和氮化物具有选择性的蚀刻工艺，从nMOSFET 102内的第一栅导体层108除去例如多晶SiGe层的第二栅导体层110。接着，例如使用诸如稀释HF(BHF)的工艺，从nMOSFET 102的侧壁114除去第一栅导体108上被暴露的氧化物内衬112。蚀刻时间将取决于氧化物内衬112的厚度。由于氧化物内衬112非常薄，例如约为5至10nm，所以将对隔离区105没有明显的损伤。
参考图5，光致抗蚀剂层126被除去。接着，金属层沉积在该结构上。例如，在优选实施方案中，镍被沉积至约3至20nm的厚度，足以完全硅化该nMOSFET栅叠层102内的多晶硅层108。在例如300至500℃下退火1至60秒之后，由该金属与nMOSFET栅叠层102的硅、衬底100的硅以及pMOSFET栅叠层104的SiGe形成半导体金属合金。所得到的结构包含在源/漏区116上的硅化物区120、在nMOSFET 102内的完全硅化栅导体、以及pMOSFET 104的硅化的顶部124。
接着，氮化物间隙壁114通过例如湿法蚀刻或干法蚀刻工艺被回蚀刻，使得氮化物间隙壁114具有与nMOSFET 102的硅化栅导体122和氧化物内衬112基本上相同的高度，结果使得nMOSFET栅叠层102在高度方面小于pMOSFET栅叠层104。由于湿法蚀刻工艺是各向同性的，所以在pMOSFET104上的氮化物间隙壁114将被减薄。优选地，氮化物间隙壁114被减薄为不大于其原始厚度的大约一半。
参考图7，受压应力的氮化物膜130沉积在该结构上。该受压应力的氮化物膜的厚度优选的范围为40至100nm。该受压应力的氮化物材料130可例如在约200℃至约500℃温度下通过高密度等离子体(HDP)沉积或等离子体增强CVD(PECVD)SiH4/NH3/N2而形成。这导致在nMOSFET和pMOSFET区域102、104的沟道182、184内分别产生压应力。
接着，例如氧化物的薄的蚀刻终止层132形成于受压应力的氮化物层130顶部上，厚度例如为约50至100埃。接着，光致抗蚀剂材料146形成于该结构上且随后被图案化从而在抗蚀剂146内形成开口148，这些开口148暴露源/漏区116上nMOSFET 102的至少对立侧上的薄氧化物132的表面，这些开口148将被用于图案化受压应力的氮化物层130内的开口158(见图10)。对于足够窄宽度的器件，在受压应力的层130内完全环绕栅极122的周边形成开口158可增强器件性能。然而，对于大宽度的器件，开口158围绕该器件所致的附加益处较小，则在较短器件102的对立侧上形成开口158就足够了。该nMOSFET器件102上薄氧化物层132的暴露部分被除去以在薄氧化物132内形成开口151，例如使用终止于受压应力的氮化物层130上诸如RIE的工艺。随后抗蚀剂层146被除去。所得的结构如图9所示。
接着，例如通过各向同性或湿法的蚀刻，将受压应力的氮化物层130除去，从而在薄氧化物132内的开口已经形成于nMOSFET器件102的源/漏区域116上的位置，形成开口158，使得开口158内边缘159与栅导体122外边缘的水平距离为Lcut，使得该nMOSFET器件102的沟道区182的应力被改变为张应力。所得的结构如图10所示。请注意，开口158的宽度可以为约30nm至约100nm，但是该宽度并不是关键的，远离栅叠层的开口158的边缘可延伸直到隔离区105。
开口158与栅导体122优选的水平距离Lcut优选地选择来优化沟道区182内所得的应力。例如可以按照下述方法确定最优距离LMax：模拟与nMOSFET器件102类似的一系列预期栅结构的沟道区182的中心183处的应力，但是改变Lcut距离，随后确定沟道应力最大的Lcut(即LMax)的位置，如图11所示。对于比nMOSFET短的pMOSFET的情形，初始应力层130受张应力，Lcut的值优选地选择为LMax以最大化该pMOSFET沟道内的压应力。
接着，具有基本上中性的应力或者基本上没有大的应力分量的氮化物膜162例如通过化学气相沉积(CVD)或高密度等离子体(HDP)沉积于该结构上，使得受压应力的氮化物层130内的开口158被填充，如图12所示。优选地，中性应力层162的厚度大于开口158宽度的1/2。接着，中性应力层162被回蚀刻至基本上与薄氧化物层132表面平齐的表面，如图13所示。随后，如本领域的技术人员所知，可完成该nMOSFET器件102和pMOSFET器件104的制作。
尽管已经参照本发明的一个或多个优选实施方案描述了对本发明，但是本领域的技术人员将会理解，在不脱离本发明的范围的情况下可以对本发明的元件进行各种改变或等效替换。此外，可以进行许多修改使具体情况或材料适于本发明的教导而不脱离本发明的基本范围。因此，本发明不应受到所公开的被认为是实施本发明的最佳模式的具体实施方案的限制，本发明应包含落在权利要求范围内的所有实施方案。

Claims (21)

1.一种半导体结构，包含：
第一类型的第一MOSFET器件，包含在第一沟道区域上的第一高度的第一栅叠层，所述第一沟道区域受第一类型应力，其中所述第一栅叠层被引起所述第一类型应力的第一应力材料重叠；以及
第二类型的第二MOSFET器件，包含在第二沟道区域上的第二栅叠层，所述第二栅叠层的高度小于所述第一高度，且在所述第二栅叠层下的第二沟道区域受第二类型应力，其中所述第二栅叠层被引起所述第二类型应力的第二应力材料重叠，所述第二类型应力不同于第一类型应力，
其中所述第二应力材料由毗邻所述第二栅导体的所述第二应力材料内至少一个不连续界定，所述不连续将所述第二应力材料与所述第一应力材料相分隔。
2.权利要求1所述的半导体结构，其中所述第二应力材料和所述第一应力材料包含基本上相同的成分。
3.权利要求1所述的半导体结构，其中所述第二应力材料内的所述至少一个不连续与所述第二栅叠层存在一定距离，以使得所述第二类型应力在所述第二沟道区最大。
4.权利要求1所述的半导体结构，其中所述第二应力材料内的所述至少一个不连续至少在所述第二栅叠层的对立侧上。
5.权利要求1所述的半导体结构，其中所述至少一个不连续包含所述第二应力材料内的开口，所述开口完全形成为环绕所述第二栅叠层周边。
6.权利要求1所述的半导体结构，其中所述至少一个不连续至少包含在所述第二应力材料和所述第一应力材料之间的间隙。
7.权利要求1所述的半导体结构，其中所述至少一个不连续包含在所述第二应力材料和所述第一应力材料之间的至少一个间隙，且其中所述至少一个间隙填充有中性应力材料。
8.权利要求1所述的半导体结构，其中所述第一类型的MOSFET器件为pMOSFET且所述第一类型应力为压应力，其中所述第二类型的MOSFET器件为nMOSFET且所述第二类型应力为张应力。
9.权利要求1所述的半导体结构，其中所述第一类型的MOSFET器件为nMOSFET且所述第一类型应力为张应力，其中所述第二类型的MOSFET器件为pMOSFET且所述第二类型应力为压应力。
10.一种用于形成半导体结构的方法，包含：
在衬底上提供设置成彼此相邻的第一和第二栅叠层，其中所述第一栅叠层具有第一高度，所述第二栅叠层具有小于所述第一高度的第二高度；
在所述第一和第二栅叠层上形成应力层，使得第一类型应力形成于所述第一栅叠层和所述第二栅叠层下的衬底内；以及
在与所述第二栅叠层距离一定距离的所述应力层内形成开口，使得第二类型应力形成于所述第二栅叠层下的衬底内，而所述第一类型应力仍保留于所述第一栅叠层下方。
11.权利要求10所述的方法，其中所述第一类型应力为压应力，所述第二类型应力为张应力。
12.权利要求10所述的方法，其中所述第一类型应力为张应力，所述第二类型应力为压应力。
13.权利要求10所述的方法，其中所述开口完全形成为围绕所述第二栅叠层周边。
14.权利要求10所述的方法，其中所述距离设置成使所述第二类型应力最大。
15.权利要求10所述的方法，其中提供所述第二栅叠层包含步骤：
形成第一和第二图案化栅叠层，所述第一和第二图案化栅叠层每个包含形成于所述衬底上的第一导体层以及形成于所述第一导体层上的第二导体层，所述第二导体层的蚀刻速率不同于所述第一导体层的蚀刻速率；以及
在所述第二图案化栅叠层内从所述第一导体层除去所述第二导体层。
16.权利要求15所述的方法，其中所述第一和第二图案化栅叠层进一步包含置于所述第一和第二图案化栅叠层的侧壁上的间隙壁，且其中所述方法进一步包含将所述第一图案化栅叠层上的所述间隙壁蚀刻至基本上与所述第二图案化栅叠层内所述第一导体层相同的高度。
17.权利要求15所述的方法，进一步包含由所述第二图案化栅叠层内的所述第一导体层形成第一半导体金属合金层，以及在所述第一图案化栅叠层内的所述第二导体层内形成第二半导体金属合金。
18.权利要求17所述的方法，其中所述第一和第二图案化栅叠层进一步包含置于所述第一和第二图案化栅叠层的侧壁上的间隙壁，且其中所述方法进一步包含将所述第一图案化栅叠层上的所述间隙壁蚀刻至基本上与所述第二图案化栅叠层内所述第一半导体金属合金层相同的高度。
19.权利要求10所述的方法，进一步包含使用具有基本上中性应力的材料填充所述开口。
20.权利要求11所述的方法，进一步包含形成包含所述第一栅叠层的pMOSFET和形成包含所述第二栅叠层的nMOSFET。
21.权利要求12所述的方法，进一步包含形成包含所述第一栅叠层的nMOSFET和形成包含所述第二栅叠层的pMOSFET。
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