CN101005292B - 具有dc平衡控制的时钟沿调制串行链路 - Google Patents

具有dc平衡控制的时钟沿调制串行链路 Download PDF

Info

Publication number
CN101005292B
CN101005292B CN200610159848.4A CN200610159848A CN101005292B CN 101005292 B CN101005292 B CN 101005292B CN 200610159848 A CN200610159848 A CN 200610159848A CN 101005292 B CN101005292 B CN 101005292B
Authority
CN
China
Prior art keywords
signal
duty ratio
bit
balance
passage
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
CN200610159848.4A
Other languages
English (en)
Chinese (zh)
Other versions
CN101005292A (zh
Inventor
G·金
W·J·崔
D-K·郑
J·金
B－J·李
M-K·金
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Silicon Image Inc
Original Assignee
Silicon Image Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=37714262&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=CN101005292(B) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Silicon Image Inc filed Critical Silicon Image Inc
Publication of CN101005292A publication Critical patent/CN101005292A/zh
Application granted granted Critical
Publication of CN101005292B publication Critical patent/CN101005292B/zh
Ceased legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/02—Transmitters
    • H04B1/04—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0008—Synchronisation information channels, e.g. clock distribution lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
    • H04B1/06—Receivers
    • H04B1/16—Circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/028—Arrangements specific to the transmitter end
    • H04L25/0284—Arrangements to ensure DC-balance
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4902—Pulse width modulation; Pulse position modulation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/02—Details ; arrangements for supplying electrical power along data transmission lines
    • H04L25/0264—Arrangements for coupling to transmission lines
    • H04L25/0272—Arrangements for coupling to multiple lines, e.g. for differential transmission

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Dc Digital Transmission (AREA)
  • Control Of Indicators Other Than Cathode Ray Tubes (AREA)
  • Noise Elimination (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Liquid Crystal Display Device Control (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
CN200610159848.4A 2005-10-31 2006-10-30 具有dc平衡控制的时钟沿调制串行链路 Ceased CN101005292B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US11/264,303 2005-10-31
US11/264,303 US7627044B2 (en) 2005-10-31 2005-10-31 Clock-edge modulated serial link with DC-balance control

Related Child Applications (1)

Application Number Title Priority Date Filing Date
CN2013103476617A Division CN103414546A (zh) 2005-10-31 2006-10-30 具有dc平衡控制的时钟沿调制串行链路

Publications (2)

Publication Number Publication Date
CN101005292A CN101005292A (zh) 2007-07-25
CN101005292B true CN101005292B (zh) 2014-04-23

Family

ID=37714262

Family Applications (2)

Application Number Title Priority Date Filing Date
CN200610159848.4A Ceased CN101005292B (zh) 2005-10-31 2006-10-30 具有dc平衡控制的时钟沿调制串行链路
CN2013103476617A Pending CN103414546A (zh) 2005-10-31 2006-10-30 具有dc平衡控制的时钟沿调制串行链路

Family Applications After (1)

Application Number Title Priority Date Filing Date
CN2013103476617A Pending CN103414546A (zh) 2005-10-31 2006-10-30 具有dc平衡控制的时钟沿调制串行链路

Country Status (6)

Country Link
US (1) US7627044B2 (enExample)
EP (3) EP2501090B8 (enExample)
JP (1) JP5068983B2 (enExample)
KR (2) KR101475065B1 (enExample)
CN (2) CN101005292B (enExample)
TW (1) TWI335744B (enExample)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7627044B2 (en) * 2005-10-31 2009-12-01 Silicon Image, Inc. Clock-edge modulated serial link with DC-balance control
US7768507B2 (en) * 2005-11-17 2010-08-03 Ati Technologies Ulc Methods and apparatus for driving a display device
US8275412B2 (en) * 2008-12-31 2012-09-25 Motorola Mobility Llc Portable electronic device having directional proximity sensors based on device orientation
JP2012044394A (ja) * 2010-08-18 2012-03-01 Sony Corp 信号伝送装置、及び伝送制御方法
WO2013023655A2 (de) * 2011-08-16 2013-02-21 Silicon Line Gmbh Schaltungsanordnung und verfahren zum uebertragen von signalen
US8687752B2 (en) * 2011-11-01 2014-04-01 Qualcomm Incorporated Method and apparatus for receiver adaptive phase clocked low power serial link
US9537644B2 (en) * 2012-02-23 2017-01-03 Lattice Semiconductor Corporation Transmitting multiple differential signals over a reduced number of physical channels
JP5987371B2 (ja) * 2012-03-09 2016-09-07 セイコーエプソン株式会社 データ受信回路、電子機器、及びデータ受信方法
US8958497B2 (en) 2012-06-12 2015-02-17 Silicon Image, Inc. Simultaneous transmission of clock and bidirectional data over a communication channel
US8797075B2 (en) * 2012-06-25 2014-08-05 Intel Corporation Low power oversampling with reduced-architecture delay locked loop
US9230505B2 (en) 2013-02-25 2016-01-05 Lattice Semiconductor Corporation Apparatus, system and method for providing clock and data signaling
KR102041530B1 (ko) 2013-06-26 2019-11-07 삼성디스플레이 주식회사 표시 장치 및 이의 구동 방법
US9312766B2 (en) * 2013-06-27 2016-04-12 Alcatel Lucent Digital serializer based pulsewidth modulator controller
US9871516B2 (en) 2014-06-04 2018-01-16 Lattice Semiconductor Corporation Transmitting apparatus with source termination
TWI533608B (zh) 2014-06-30 2016-05-11 友達光電股份有限公司 資料接收器及資料接收方法
US9525573B2 (en) 2015-01-23 2016-12-20 Microsoft Technology Licensing, Llc Serializing transmitter
US9432061B2 (en) 2015-01-23 2016-08-30 Microsoft Technology Licensing, Llc Serializing transmitter
US10146911B2 (en) 2015-10-23 2018-12-04 Medtronic Minimed, Inc. Medical devices and related methods and systems for data transfer
US9692590B1 (en) * 2015-12-07 2017-06-27 Raytheon Company Serial data multiplexing
CN112584474B (zh) * 2018-02-13 2023-12-15 Oppo广东移动通信有限公司 数据传输的方法、终端设备和网络设备
US11088880B2 (en) 2019-05-15 2021-08-10 Rambus Inc. Phase modulated data link for low-swing wireline applications
CN110868209B (zh) * 2019-10-30 2023-04-28 西安邮电大学 一种用于多相位延时锁相环的高相位精度压控延迟线结构及其实现方法
KR102672609B1 (ko) * 2019-11-13 2024-06-07 삼성전자주식회사 엔코더, 디코더, 및 이를 구비하는 반도체 메모리 장치
DE202021105937U1 (de) * 2021-10-29 2022-02-04 TRUMPF Hüttinger GmbH + Co. KG Steuerschaltung für Treiber
KR102569025B1 (ko) * 2021-11-25 2023-08-21 고려대학교 산학협력단 비대칭적인 전압 파형을 자가 보정할 수 있는 접지 신호 전송 기법 기반의 송신기

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1042262A (zh) * 1988-09-15 1990-05-16 国际商业机器公司 相位鉴别与数据分离的方法和装置
US6671316B1 (en) * 2000-04-13 2003-12-30 Storage Technology Corporation Three state pulse width modulation code

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS595763A (ja) * 1982-07-01 1984-01-12 Hino Denshi Kk 電力・信号伝送方式
JPH0530069A (ja) * 1991-07-22 1993-02-05 Nec Eng Ltd 制御信号伝送方式
US5999571A (en) * 1995-10-05 1999-12-07 Silicon Image, Inc. Transition-controlled digital encoding and signal transmission system
US6463092B1 (en) * 1998-09-10 2002-10-08 Silicon Image, Inc. System and method for sending and receiving data signals over a clock signal line
US7356051B2 (en) * 2001-01-24 2008-04-08 Broadcom Corporation Digital visual interface with audio and auxiliary data cross reference to related applications
US7158593B2 (en) * 2001-03-16 2007-01-02 Silicon Image, Inc. Combining a clock signal and a data signal
WO2002100058A1 (en) * 2001-05-30 2002-12-12 Thine Electronics, Inc. Semiconductor integrated circuit and data transmission system
EP1351462A1 (en) * 2002-03-29 2003-10-08 MystiCom, Ltd. Error Correcting 8B/10B Transmission System
US7394406B2 (en) * 2002-12-17 2008-07-01 Broadcom Corporation Method and system for generating high definition multimedia interface (HDMI) codewords using a TMDS encoder/decoder
JP2005150929A (ja) * 2003-11-12 2005-06-09 Sharp Corp 信号伝送装置および信号伝送方法
JP4101780B2 (ja) * 2004-03-22 2008-06-18 株式会社日立国際電気 信号伝送方法および信号伝送装置
EP1737174B1 (en) * 2004-04-16 2015-05-27 Thine Electronics, Inc. Transmitter circuit, receiver circuit, data transmitting method and system
US7363575B2 (en) * 2004-11-12 2008-04-22 Broadcom Corporation Method and system for TERC4 decoding using minimum distance rule in high definition multimedia interface (HDMI) specifications
US7627044B2 (en) * 2005-10-31 2009-12-01 Silicon Image, Inc. Clock-edge modulated serial link with DC-balance control

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1042262A (zh) * 1988-09-15 1990-05-16 国际商业机器公司 相位鉴别与数据分离的方法和装置
US6671316B1 (en) * 2000-04-13 2003-12-30 Storage Technology Corporation Three state pulse width modulation code

Also Published As

Publication number Publication date
EP2501090A2 (en) 2012-09-19
JP2007129735A (ja) 2007-05-24
EP2787705A1 (en) 2014-10-08
KR20130105571A (ko) 2013-09-25
EP2501090B1 (en) 2014-09-03
CN103414546A (zh) 2013-11-27
KR101475065B1 (ko) 2014-12-22
EP1780930A2 (en) 2007-05-02
TWI335744B (en) 2011-01-01
EP2501090A3 (en) 2012-12-19
EP1780930A3 (en) 2009-12-23
KR101408457B1 (ko) 2014-06-19
CN101005292A (zh) 2007-07-25
US20070098112A1 (en) 2007-05-03
EP2501090B8 (en) 2014-11-05
TW200740156A (en) 2007-10-16
EP1780930B1 (en) 2013-09-04
KR20070046718A (ko) 2007-05-03
JP5068983B2 (ja) 2012-11-07
US7627044B2 (en) 2009-12-01

Similar Documents

Publication Publication Date Title
CN101005292B (zh) 具有dc平衡控制的时钟沿调制串行链路
US9928208B2 (en) Methods to send extra information in-band on inter-integrated circuit (I2C) bus
US9143362B2 (en) N-phase polarity output pin mode multiplexer
JP5066121B2 (ja) クロック情報とデータを伝送する装置及び方法
US10033518B2 (en) Data on clock lane of source synchronous links
CA2343040A1 (en) A system and method for sending and receiving data signals over a clock signal line
US7706309B2 (en) Data transfer control device, electronic instrument, and data transfer control method
US20050201411A1 (en) Data transfer control device and electronic instrument
CN107223312B (zh) 用于数据链路功率降低和吞吐量提高的多调制
CA2396948A1 (en) A system and method for sending and receiving data signals over a clock signal line
CN109831192B (zh) 用于传送器、接收器的物理层电路及其方法、及通讯系统
Choe et al. A 3-mW, 270-Mbps, clock-edge modulated serial link for mobile displays
Jo et al. An Intra-panel Interface for Large Size FPDs with High Resolution And Definition

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
IW01 Full invalidation of patent right

Decision date of declaring invalidation: 20190610

Decision number of declaring invalidation: 40513

Granted publication date: 20140423

IW01 Full invalidation of patent right