CN100590798C - High voltage NMOS transistor manufacturing method and high voltage PMOS transistor manufacturing method - Google Patents
High voltage NMOS transistor manufacturing method and high voltage PMOS transistor manufacturing method Download PDFInfo
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- CN100590798C CN100590798C CN200710094360A CN200710094360A CN100590798C CN 100590798 C CN100590798 C CN 100590798C CN 200710094360 A CN200710094360 A CN 200710094360A CN 200710094360 A CN200710094360 A CN 200710094360A CN 100590798 C CN100590798 C CN 100590798C
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Abstract
The invention discloses a method for manufacturing a high voltage transistor, which comprises: after high voltage well injection, firstly carrying out ion injection for a drift region by low dosage and large energy, then carrying out repeated ion injection for the drift region by gradually decreased energy, and adopting the ion injection of low energy and middle dosage on the surface of the driftregion. The high voltage transistor manufactured by the method can improve driving force and reduce leakage current.
Description
Technical field
The invention belongs to semiconductor technology, particularly a kind of high pressure NMOS transistor fabrication process and high voltage PMOS transistor manufacture method.
Background technology
Semiconductor high-voltage device all adopts the diffusion drift region structure usually, improves the drain terminal junction breakdown voltage on the one hand, on the other hand by the drift region dividing potential drop, improves the puncture voltage of raceway groove.In common process, adopt single high-energy drift region ion to inject usually, to carry out drift region high temperature after the drift region ion injects and advance, the drift region all is to adopt light dope, and the drift region surface impurity concentration is lower, and Impurity Distribution is not gradual.Figure 1 shows that the transistorized drift region of the high pressure NMOS knot schematic diagram that a common process is made, the edge of drift region knot is mild.Vertical CONCENTRATION DISTRIBUTION of drift region phosphorus as shown in Figure 3, the drift region surface impurity concentration is lower, Impurity Distribution is not gradual.Though the drift region all is to adopt light dope to obtain high-breakdown-voltage, has limited the raising of high tension apparatus drive current, lower in addition drift region surface impurity concentration has brought serious grid to introduce drain terminal leakage current effects (GIDL), causes higher leakage current.The GIDL effect is the key factor of high tension apparatus leakage current.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of high pressure NMOS transistor fabrication process and high voltage PMOS transistor manufacture method, adopts the high voltage transistor of this method manufacturing can improve driving force, and reduces the high-pressure crystal tube leakage current.
For solving the problems of the technologies described above, the technical scheme of high pressure NMOS transistor fabrication process of the present invention and high voltage PMOS transistor manufacture method is, after the high pressure trap injects, the drift region ion that carries out low dosage, macro-energy earlier injects, carry out the repeatedly drift region ion injection that energy successively decreases gradually then in succession, and adopt low-yield, middle dosage ion to inject on the surface, drift region.
High pressure NMOS transistor fabrication process of the present invention, after the high pressure trap injected, the transistorized drift region of high pressure NMOS adopted phosphonium ion to inject, and carries out 3e12cm earlier
-2～4e12cm
-2The drift region phosphonium ion of low dosage, 150KeV～200KeV macro-energy injects; Carry out the repeatedly phosphonium ion injection that energy 200KeV～30KeV successively decreases gradually then in succession, form the gradual drift region of Impurity Distribution; Adopt low-yield, the 4e12cm of 30KeV～70KeV on the surface, drift region
-2～7e12cm
-2The phosphonium ion of middle dosage injects, and has increased the drift region surface impurity concentration.
High voltage PMOS transistor manufacture method of the present invention, after the high pressure trap injected, the drift region of high voltage PMOS transistor adopted the boron ion to inject, and carries out 2e12cm earlier
-2～3e12cm
-2The drift region boron ion of low dosage, 100KeV～150KeV macro-energy injects; Carry out the repeatedly boron ion injection that energy 150KeV～20KeV successively decreases gradually then in succession, form the gradual drift region of Impurity Distribution; Adopt low-yield, the 3e12cm of 20KeV～50KeV on the surface, drift region
-2～5e12cm
-2The boron ion of middle dosage injects, and has increased the drift region surface impurity concentration
High pressure NMOS transistor fabrication process of the present invention and high voltage PMOS transistor manufacture method adopt energy repeatedly ion from high to low to inject in the formation of high voltage transistor drift region, take low-yield, middle dosage ion to inject for the last time.Inject energy gradient ion from high to low and inject the drift region that obtains more gradual Impurity Distribution, improve the junction breakdown voltage of drift region, particularly the puncture voltage of side direction knot; The surface, drift region adopts low-yield, middle dosage ion to inject, obtain higher relatively surface impurity concentration, higher drift region surface impurity distributes and has reduced the GIDL effect, thereby has reduced transistorized leakage current, also reduce the series resistance of drift region, improved transistorized drive current; Because the Impurity Distribution difference has increased length of effective channel, has improved the raceway groove puncture voltage.
Description of drawings
Below in conjunction with the drawings and the specific embodiments the present invention is described in further detail.
Fig. 1 is the transistorized drift region of the high pressure NMOS knot schematic diagram that common process is made;
Fig. 2 is the high pressure NMOS transistor drift district knot schematic diagram that high pressure NMOS transistor fabrication process of the present invention is made;
Fig. 3 is the high pressure NMOS transistor of common process manufacturing and vertical distribution schematic diagram of the transistorized drift region of the high pressure NMOS phosphorus concentration that high pressure NMOS transistor fabrication process of the present invention is made;
Fig. 4 is the high pressure NMOS transistor of common process manufacturing and the comparison schematic diagram of the transistorized drift region of the high pressure NMOS drain terminal depletion region that high pressure NMOS transistor fabrication process of the present invention is made;
Fig. 5 is high pressure NMOS transistor fabrication process of the present invention and high voltage PMOS transistor manufacture method one execution mode flow chart.
Embodiment
One execution mode of high pressure NMOS transistor fabrication process of the present invention and high voltage PMOS transistor manufacture method, as shown in Figure 5, after the high pressure trap injects, carry out low dosage earlier, the drift region ion of macro-energy injects, carry out the repeatedly ion injection that energy successively decreases gradually then in succession, form the comparatively gradual drift region of Impurity Distribution, and adopt low-yield on the surface, drift region, middle dosage ion is injected, increase the drift region surface impurity concentration, carried out high voltage grid oxidation layer and polysilicon gate deposit again, the deposit of silica or silicon nitride side wall and etching, technologies such as source leakage ion injection are finally finished the manufacturing of high voltage transistor.The drift region ion of the low dosage that carries out, macro-energy injects and has realized high junction breakdown voltage earlier; The drift region that Impurity Distribution is comparatively gradual has effectively increased the not depleted region area in drift region under the drain terminal HVB high voltage bias, thereby has increased the drive current of device; The repeatedly ion that energy gradient distributes injects and makes the high temperature of common process drift region advance technology to omit, and has reduced the technology cost; The repeatedly drift region ion that energy successively decreases gradually injects, and adopts low-yield, middle dosage ion to inject on the surface, drift region, has increased the drift region surface impurity concentration, has reduced the GIDL effect effectively, has reduced leakage current.
As an embodiment, the drift region of high pressure NMOS part adopts phosphonium ion to inject, and carries out 3e12cm earlier
-2～4e12cm
-2The drift region phosphonium ion of low dosage, 150KeV～200KeV macro-energy injects, carry out the repeatedly phosphonium ion injection that energy 200KeV～30KeV successively decreases gradually then in succession, form the comparatively gradual drift region of Impurity Distribution, and adopt low-yield, the 4e12cm of 30KeV～70KeV on the surface, drift region
-2～7e12cm
-2The phosphonium ion of middle dosage injects, and has increased the drift region surface impurity concentration; The drift region of high voltage PMOS transistor adopts the boron ion to inject, and carries out 2e12cm earlier
-2～3e12cm
-2The drift region boron ion of low dosage, 100KeV～150KeV macro-energy injects, carry out the repeatedly boron ion injection that energy 150KeV～20KeV successively decreases gradually then in succession, form the comparatively gradual drift region of Impurity Distribution, and adopt low-yield, the 3e12cm of 20KeV～50KeV on the surface, drift region
-2～5e12cm
-2The boron ion of middle dosage injects, and has increased the drift region surface impurity concentration.
High pressure NMOS transistor fabrication process of the present invention and high voltage PMOS transistor manufacture method adopt energy repeatedly ion from high to low to inject in the formation of high voltage transistor drift region, take low-yield, middle dosage ion to inject for the last time.Inject energy gradient ion from high to low and inject the drift region that obtains more gradual Impurity Distribution, improve the junction breakdown voltage of drift region, particularly the puncture voltage of side direction knot; The surface, drift region adopts low-yield, middle dosage ion to inject, obtain higher relatively surface impurity concentration, higher drift region surface impurity distributes and has reduced the GIDL effect, thereby has reduced transistorized leakage current, also reduce the series resistance of drift region, improved transistorized drive current; Because the Impurity Distribution difference has increased length of effective channel, has improved the raceway groove puncture voltage.
The transistorized drift region of the high pressure NMOS that method of the present invention is made knot schematic diagram as shown in Figure 2, the edge of drift region knot is more steep, the puncture voltage that helps tying improves, vertical CONCENTRATION DISTRIBUTION of the phosphorus that mixes in the drift region as shown in Figure 3, the drift region Impurity Distribution is more gradual, the concentration of surface, drift region phosphorus is higher, has improved drive current.
Fig. 4 is the high pressure NMOS transistor of common process manufacturing and the comparison schematic diagram of the transistorized drift region of the high pressure NMOS drain terminal depletion region that production method for high voltage transistor of the present invention is made, the high pressure NMOS transistor that method of the present invention is made is under the drain terminal HVB high voltage bias, the pinch off of drift region depletion region occurs, help the raising of device electric breakdown strength.
Table one be the high pressure NMOS characteristics of transistor made of the high pressure NMOS transistor made of the common process of TCAD (Computer-aided Design Technology) simulation and method of the present invention relatively.
Table one:
| Threshold voltage (V) | Saturation current (uA/um) | Puncture voltage (V) | Cut-off current (pA/um) | |
| Conventional high pressure NMOS transistor | 0.796 | 539 | 16.5 | 3 |
| High pressure NMOS transistor of the present invention | 0.799 | 599 | 18.8 | 2.6 |
As can be seen from Table I, the threshold voltage of the high voltage transistor of method manufacturing of the present invention and cut-off current can both be consistent with conventional device, but saturation current and puncture voltage all be greatly improved, and have improved device performance.
The drift region Impurity Distribution of the high voltage transistor that method of the present invention is made is more gradual, has effectively improved the puncture voltage of this knot, particularly the puncture voltage of side direction knot; The drift region surface impurity distributes higher, has reduced the GIDL effect, thereby has reduced transistorized leakage current, has also reduced the series resistance of drift region, has improved transistorized drive current.The present invention is the drive current that improves high voltage transistor by the Impurity Distribution in the optimization high voltage transistor drift region, reduces transistor drain current, solves the contradiction between high-breakdown-voltage and high drive current, the low-leakage current.
Claims (2)
1, a kind of high pressure NMOS transistor fabrication process is characterized in that, after the high pressure trap injected, the transistorized drift region of high pressure NMOS adopted phosphonium ion to inject, and carries out 3e12cm earlier
-2～4e12cm
-2The drift region phosphonium ion of low dosage, 150KeV～200KeV macro-energy injects; Carry out the repeatedly phosphonium ion injection that energy 200KeV～30KeV successively decreases gradually then in succession, form the gradual drift region of Impurity Distribution; Adopt low-yield, the 4e12cm of 30KeV～70KeV on the surface, drift region
-2～7e12cm
-2The phosphonium ion of middle dosage injects, and has increased the drift region surface impurity concentration.
2, a kind of high voltage PMOS transistor manufacture method is characterized in that, after the high pressure trap injected, the drift region of high voltage PMOS transistor adopted the boron ion to inject, and carries out 2e12cm earlier
-2～3e12cm
-2The drift region boron ion of low dosage, 100KeV～150KeV macro-energy injects; Carry out the repeatedly boron ion injection that energy 150KeV～20KeV successively decreases gradually then in succession, form the gradual drift region of Impurity Distribution; Adopt low-yield, the 3e12cm of 20KeV～50KeV on the surface, drift region
-2～5e12cm
-2The boron ion of middle dosage injects, and has increased the drift region surface impurity concentration.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200710094360A CN100590798C (en) | 2007-11-30 | 2007-11-30 | High voltage NMOS transistor manufacturing method and high voltage PMOS transistor manufacturing method |
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|---|---|---|---|
| CN200710094360A CN100590798C (en) | 2007-11-30 | 2007-11-30 | High voltage NMOS transistor manufacturing method and high voltage PMOS transistor manufacturing method |
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| CN100590798C true CN100590798C (en) | 2010-02-17 |
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| CN104517853A (en) * | 2014-05-15 | 2015-04-15 | 上海华虹宏力半导体制造有限公司 | Super-junction semiconductor device manufacturing method |
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Owner name: SHANGHAI HUAHONG GRACE SEMICONDUCTOR MANUFACTURING Free format text: FORMER OWNER: HUAHONG NEC ELECTRONICS CO LTD, SHANGHAI Effective date: 20140115 |
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