CN100589325C - A differential signal interface circuit - Google Patents

Abstract

The disclosed differential signal interface circuit comprises mainly: a configurable operational amplifier (OA) with input from INP, INN, EN1, EN2, VDDH and VNREF, to output differential signal to next circuit; a level switch circuit with VDDH as input to output differential signal to next circuit, and a double-to-one circuit to output single-port signal. This invention is compatible to LVDS and LVPECL signal to converse into CMOS logic signal, and can be used in high-speed data transmission.

Description

A kind of differential signal interface circuit

Technical field

The present invention relates to a kind of differential signal interface circuit that is applied to the high speed data transfer of communicating circuit chips and chip, can compatible LVDS and dissimilar input signal such as LVPECL and convert thereof into the CMOS logical signal by disposing different mode of operations.

Background technology

Along with the development of mechanics of communication, the data transmission bauds of chip chamber is more and more faster, and the use of differential signal now also more and more widely.One of the advantage of differential signal is that its amplitude is less, can make the data transmission bauds maximization.Anti-interference, the noise robustness that is exactly that differential signal has in addition.At communication field, using maximum differential signals is exactly LVDS and LVPECL signal.Wherein, LVDS is meant Low Voltage Differential Signal, low-voltage differential signal; LVPECL is meant low pressure positive emitter coupling logic signal, low-voltage positive emitter-coupled logic.The level setting of these two kinds of signals is all defined by relevant international standard, is that 2.5V or 3.3V formulate at supply voltage generally.

On the other hand, development along with present integrated circuit technology, for the integrated level that increases chip with reduce cost, the main flow live width of CMOS technology is 0.13um at present, and the supply voltage of internal components work also continues to be reduced to 1.2V, so just can also reduce the power consumption of chip when increasing device reliability at the maximum field strength above reducing raceway groove.Because most of chip internal is the cmos digital circuit, unipolar CMOS logical circuit, can not directly handle differential signal, can only handle the CMOS logical signal, therefore the 3.3V/2.5V differential signal of chip exterior input need be transformed out the CMOS logical signal of 1.2V at the port of chip.

In present domestic patent, do not find not have similar LVDS or LVPECL interface circuit patent about interface circuit.And abroad in the patent, similarly interface circuit does not all have the function of level conversion, and different modules is adopted in the processing of input varying level type signal, selects the module of using as required or can only handle the signal of single type.Can handle the input signal of LVDS and CML type simultaneously such as the technology in the U.S. Pat 6462852, and be equipped with AC coupling and two kinds of optional connected modes of DC coupling, its structural representation as shown in Figure 1.This patent has adopted CMLREC receiver module and STIREC to handle the CML signal and the LVDS signal of input respectively, adopts a MUX to select output signal at output.From this United States Patent (USP), describe the structure of CMLREC/STIREC inside modules circuit and know that these modules have been used MOS device and bipolar transistor, realize that therefore this patent must adopt complicated BiCMOS technology.Comprehensive, U.S. Pat 6462852 has following deficiency:

1. adopt two modules to handle the signal with different type of input respectively, make circuit complicated;

2. do not have built-inly to be transformed into the level shifting circuit of low supply voltage signal from the high power supply voltage signal, the scope of application of patent is diminished, inapplicable present technology is to the needs of submicrometer processing development;

3. adopt BiCMOS technology to realize, cost is increased, and can not use in modern CMOS technology.

In addition, U.S. Pat 2004/0174191A1 describes a LVDS acceptor circuit simple in structure, as shown in Figure 2.From patent is described, know that this patent can only receive the LVDS signal, and do not have the function of level conversion.

Summary of the invention

The objective of the invention is at the deficiencies in the prior art, a kind of interface circuit that can carry out level conversion of high speed is provided, dispose the input signal that can be applicable to LVDS or LVPECL level respectively by chip internal, the connected mode in the time of can disposing its use simultaneously.

In order to realize the foregoing invention purpose, the present invention proposes a kind of differential signal interface circuit, mainly comprise configurable amplifier 101, level shifting circuit 102, double rotary single circuit 103.

The concrete connection of interface circuit is as follows: outside input differential signal INP and INN are input in the configurable amplifier 101, and external control signal EN1, EN2 and reference voltage VNREF are input in the configurable amplifier 101 simultaneously; Configurable amplifier one group of differential signal 111 of 101 outputs and 112 is input in the level shifting circuit 102; The high-tension power vd DH of outside input imports in configurable amplifier 101 and the level shifting circuit 102 simultaneously; Level shifting circuit one group of differential signal 113 of 102 outputs and 114 enters into double rotary single circuit 103; Double rotary single circuit 103 output single-ended signals 115; The power vd DL of outside input low-voltage is input in the double rotary single circuit 103; The high-tension power vd DH of outside input connects configurable amplifier 101 and level shifting circuit 102 simultaneously; External reference ground voltage VSS is input in configurable amplifier 101, level shifting circuit 102 double rotary single circuits 103 as reference ground.

Further, the output single-ended signal 115 of double rotary single circuit 103 outputs in the buffer circuit 104, output buffer 104 output signal OUT.This output buffer 104 is to provide enough driving forces for different loads.

The power vd DL of outside input low-voltage is input in double rotary single circuit 103 and the output buffer 104 simultaneously; Conduct is with reference to ground in the external voltage VSS input and output buffer circuit 104.

The differential signal INP and the INN of outside input can be the LVDS level, also can be the LVPECL level.

In the technique scheme, configurable amplifier 101 inside have comprised a lot of impedance matchings and dc point is provided with circuit, according to the level form of input differential signal INP and INN, the configuration mode of input control signal EN1 and EN2 and the method for attachment of external build-out resistor realize different level signal inputs.When EN1 is a high level, when EN2 is high level, need not external build-out resistor just be applicable to differential signal INP and the INN that uses LVDS; When EN1 is a high level, when EN2 is low level, be applicable to differential signal INP and the INN of DC coupling LVPECL, need external build-out resistor set the dc point of input differential signal INP and INN and reach impedance matching this moment; When EN1 is a low level, when EN2 is high level, need not external build-out resistor just be applicable to differential signal INP and the INN of AC coupling LVPECL; When EN1 is a low level, when EN2 is low level, be applicable to differential signal INP and the INN of AC coupling LVPECL, need be between INP and INN external parallel resistance reach the purpose of impedance matching.The output signal 111 of configurable amplifier 101 and 112 is a pair of differential signal, and its dc point is set with respect to chip exterior high power supply voltage VDDH.

In order to make signal 111 and 112 be suitable for the instructions for use of chip internal low supply voltage VDDL, need carry out level conversion to output signal 111 and 112.Level shifting circuit 102 is applicable to low supply voltage VDDL with the common-mode voltage of input signal 111 and 112 from being applicable to that high power supply voltage VDDH is reduced to, and the output differential signal 113 of level shifting circuit 102 and 114 level range will be fit to the needs of inner low voltage CMOS device like this.

What signal is handled general employing at chip internal is single-ended cmos signal, therefore also needs the differential signal 113 and 114 of level shifting circuit 102 outputs is carried out conversion of signals. Differential signal 113 and 114 at first carries out double rotary single circuit 103, convert the differential signal 113 and 114 that is fit to VDDL to single-ended signal 115, by output buffer 104 signal 115 is amplified again, make it to reach the CMOS level that is fit to internal core circuit power voltage VDDL needs, as signal OUT output internal circuit.

By technique scheme, a kind of differential signal interface circuit of the present invention has following advantage and beneficial effect at least:

1, by configuration control signal EN1 and EN2, can be suitable for LVDS or LVPECL input signal respectively, like this can be according to input signal situation flexible configuration;

2, inside has comprised build-out resistor, can reduce outward element number when using, and simplifies the circuit structure when using;

3, have the level conversion function, the conversion of signals of the outer high power supply voltage of sheet can be become the signal of chip internal low supply voltage, can reduce the operating voltage of chip internal core circuit like this, reduce the power consumption of chip;

4, operating rate height can reach 622MHz, and this is very high frequency to the LVDS/LVPECL clock signal.

Description of drawings

Fig. 1 is the circuit diagram of U.S. Pat 6462852;

Fig. 2 is the circuit diagram of U.S. Pat 2004/0174191A1;

Fig. 3 is the structure chart of differential signal interface circuit of the present invention;

Fig. 4 is the circuit structure diagram of the embodiment of the invention;

Fig. 5 is the physical circuit figure of control signal converting circuit X201 and X202 among Fig. 4;

Fig. 6 is the circuit diagram of transmission gate TG1 among Fig. 4;

Fig. 7 is that configurable amplifier 101 is configured to EN1=1 among Fig. 4, and EN2=1 connects build-out resistor in having, the circuit reduction figure when being applicable to input LVDS signal;

Fig. 8 is that configurable amplifier 101 is configured to EN1=1 among Fig. 4, and EN2=0 connects build-out resistor in the nothing, the circuit reduction figure when being applicable to DC coupled modes input LVDS/LVPECL signal;

Fig. 9 is that configurable amplifier 101 is configured to EN1=0 among Fig. 4, and EN2=1 connects build-out resistor in having, the circuit reduction figure when being applicable to AC coupled modes input LVPECL signal;

Figure 10 is that configurable amplifier 101 is configured to EN1=0 among Fig. 4, and EN2=0 connects build-out resistor in the nothing, the circuit reduction figure when being applicable to AC coupled modes input LVPECL signal.

Embodiment

Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to the detailed description of the invention as after.

In order to realize the foregoing invention purpose, the present invention proposes a kind of novel interface circuit, mainly comprise configurable amplifier 101, level shifting circuit 102, double rotary single circuit 103 and output buffer 104, physical circuit is referring to Fig. 3.

The concrete connection of interface circuit is as follows: the differential signal INP of outside high level and INN are input in the configurable amplifier 101, and external control signal EN1, EN2 and reference voltage VNREF are input in the configurable amplifier 101 simultaneously; Configurable amplifier one group of differential signal 111 of 101 outputs and 112 is input in the level shifting circuit 102; The high-tension power vd DH of outside input imports in configurable amplifier 101 and the level shifting circuit 102 simultaneously; Level shifting circuit one group of differential signal 113 of 102 outputs and 114 enters into double rotary single circuit 103; Double rotary single circuit 103 output signals 115 in output buffer 104, output buffer 104 output signal OUT; The power vd DL of outside input low-voltage is input in double rotary single circuit 103 and the output buffer 104 simultaneously; External voltage VSS is input to this four circuit, and conduct is with reference to ground in configurable amplifier 101, level shifting circuit 102, double rotary single circuit 103 and the output buffer 104; Whole system just obtains the CMOS level signal OUT that the chip internal circuit can be handled like this.

Embodiment below in conjunction with device of the present invention is described further.

Fig. 4 is a kind of particular circuit configurations figure of the embodiment of the invention, and it has comprised four sub-circuit modules such as configurable amplifier 101 as shown in Figure 3, level shifting circuit 102, double rotary single circuit 103 and output buffer 104.Configurable amplifier 101 is by PMOS pipe P0, P1, P2 and P3, and NMOS manages N0, N1, N2, N3, N4, N5, N6, N7 and N8, resistance R 0, R1, R2 and R3, and transmission gate TG1 and control signal converting circuit X201, X202 form; Level shifting circuit 102 is by PMOS pipe P4, P5, and NMOS pipe N9 and resistance R 4, R5 form; Double rotary single circuit 103 is made up of PMOS pipe P6, P7 and NMOS pipe N10, N11, N12; Output buffer 104 is made up of PMOS pipe P8, P9 and N13, N14.

In Fig. 4, EN1 and EN2 are input to respectively among control signal converting circuit X201 and the X202, export a pair of difference control signal EN1HV/EN1BHV and EN2HV/EN2BHV respectively.Signal EN1HV is input to the grid of PMOS pipe P0 and P1, and the source electrode of PMOS pipe P0 and P1 is all received supply voltage VDDH.An end of resistance R 0 is received in the drain electrode of PMOS pipe P0, and the other end of resistance R 0 and external input signal INP are connected together.External input signal INP is connected to the drain electrode of NMOS pipe N5 simultaneously, and the grid of NMOS pipe N5 is received EN1BHV, and the drain electrode of the source electrode of NMOS pipe N5 and NMOS pipe N0 is connected together.The grid of NMOS pipe N0 is received reference voltage VNREF, and source electrode is connected to ground VSS.External input signal INP is connected to an end of resistance R 2 simultaneously, and the other end of resistance R 2 is connected to the port A of transmission gate TG1.External input signal INP is input to the grid of NMOS pipe N7 simultaneously, and the source electrode of NMOS pipe N7 is connected to the drain electrode of NMOS pipe N2, and the drain electrode of NMOS pipe N7 connects holding wire 111.Holding wire 111 is connected to grid and the drain electrode of PMOS pipe P2 simultaneously, forms diode and connects.Holding wire 111 is connected to the drain electrode of NMOS pipe N1 simultaneously, and the grid of NMOS pipe N1 is connected to reference voltage VNREF, and source electrode is connected to ground VSS.

In Fig. 4, the drain electrode of PMOS pipe P1 is connected to an end of resistance R 1, and the other end of resistance R 1 and external input signal INN link together.External input signal INN is connected to the drain electrode of NMOS pipe N6 simultaneously, and the grid of NMOS pipe N6 is received EN1BHV, and the drain electrode of the source electrode of NMOS pipe N6 and NMOS pipe N4 is connected together.The grid of NMOS pipe N4 is received reference voltage VNREF, and source electrode is connected to ground VSS.External input signal INN is connected to an end of resistance R 3 simultaneously, and the other end of resistance R 3 is connected to another port B of transmission gate TG1.External input signal INP is input to the grid of NMOS pipe N8 simultaneously, and the source electrode of NMOS pipe N8 is connected to the drain electrode of NMOS pipe N2, and the drain electrode of NMOS pipe N8 connects holding wire 112.Holding wire 112 is connected to grid and the drain electrode of PMOS pipe P3 simultaneously, forms diode and connects.Holding wire 112 is connected to the drain electrode of NMOS pipe N3 simultaneously, and the grid of NMOS pipe N3 is connected to reference voltage VNREF, and source electrode is connected to ground VSS.Transmission gate TG1 positive input terminal P meets EN2HV, and negative input end N meets EN2BHV.

In Fig. 4, holding wire 111 is connected to the grid of PMOS pipe P4, and the source electrode of PMOS pipe P4 meets supply voltage VDDH, and the drain electrode of PMOS pipe P4 is connected to holding wire 113.Holding wire 113 is connected to an end of resistance R 4 simultaneously, and the other end of resistance R 4 is connected to holding wire 116.Holding wire 112 is connected to the grid of PMOS pipe P5, and the source electrode of PMOS pipe P5 meets supply voltage VDDH, and the drain electrode of PMOS pipe P5 is connected to holding wire 114.Holding wire 114 is connected to an end of resistance R 5 simultaneously, and the other end of resistance R 5 is connected to holding wire 116.Synchronous signal line 116 is connected to grid and the drain electrode of NMOS pipe N9, and the source electrode of NMOS pipe N9 is connected to ground VSS.

In Fig. 4, holding wire 113 is connected to the grid of NMOS pipe N11, and the drain electrode of NMOS pipe N11 is connected to holding wire 115, and the source electrode of NMOS pipe N11 is connected to holding wire 117.Synchronous signal line 115 is connected to the drain electrode of PMOS pipe P7, and the grid of PMOS pipe P7 is connected to grid and the drain electrode of PMOS pipe P6, and the source electrode of PMOS pipe P7 is connected to supply voltage VDDL.Holding wire 114 is connected to the grid of NMOS pipe N10, and the drain electrode of NMOS pipe N10 is connected to grid and the drain electrode of PMOS pipe P6, and the source electrode of NMOS pipe N10 is connected to holding wire 117.Synchronous signal line 117 is connected to the drain electrode of NMOS pipe N12, and the source electrode of NMOS pipe N12 is connected to ground VSS.The grid of PMOS pipe P6 and drain electrode simultaneously is connected to the grid of NMOS pipe N12 together, and the source electrode of PMOS pipe P6 is connected to supply voltage VDDL.

In Fig. 4, holding wire 115 is input to the grid of PMOS pipe P8 and NMOS pipe N13, and the source electrode of PMOS pipe P8 is connected to supply voltage VDDL, and the source electrode of NMOS pipe N13 connects ground VSS.The drain electrode of PMOS pipe P8 and NMOS pipe N13 links together and outputs to the grid of PMOS pipe P9 and NMOS pipe N14.The source electrode of PMOS pipe P9 is connected to supply voltage VDDL, and the source electrode of NMOS pipe N14 connects ground VSS.The drain electrode of PMOS pipe P8 and NMOS pipe N13 is connected to output signal OUT together.

Fig. 5 is exactly the physical circuit figure of control signal converting circuit X201 and X202 among Fig. 4.In Fig. 5, input signal EN is connected to the grid of PMOS pipe P10 and NMOS pipe N15, and the source electrode of PMOS pipe P10 is connected to supply voltage VDDL, and the source electrode of NMOS pipe N15 connects ground VSS.The drain electrode of PMOS pipe P10 and NMOS pipe N15 links together, and outputs to the grid of PMOS pipe P11 and NMOS pipe N16, and the drain electrode of PMOS pipe P10 and NMOS pipe N15 simultaneously links together and also outputs to the grid of NMOS pipe 18.The source electrode of PMOS pipe P11 is connected to supply voltage VDDL, and the source electrode that NMOS manages N16 connects ground VSS, and the drain electrode of PMOS pipe P11 and NMOS pipe N16 links together and exports the grid of NMOS pipe 19.The source electrode of NMOS pipe N18 is connected to ground VSS, and drain electrode is connected to holding wire 301.Holding wire 301 is connected to the drain electrode of PMOS pipe P13 and the grid of PMOS pipe P14 simultaneously, and the source electrode of PMOS pipe 13 is connected to supply voltage VDDH.Holding wire 301 is connected to the grid of PMOS pipe P12 and the grid of NMOS pipe N17 simultaneously.The source electrode of PMOS pipe P12 is connected to supply voltage VDDH, and NMOS pipe N17 is connected to ground VSS, and the drain electrode of PMOS pipe P12 and NMOS pipe N17 is connected to holding wire ENBHV simultaneously and exports this control signal converting circuit outside.The source electrode of NMOS pipe N19 is connected to ground VSS, and drain electrode is connected to holding wire 302.Holding wire 302 is connected to the drain electrode of grid and the PMOS pipe P14 of PMOS pipe P13 simultaneously.The source electrode of PMOS pipe P14 is connected to supply voltage VDDH.Holding wire 302 is connected to the grid of PMOS pipe P15 and the grid of NMOS pipe N20 simultaneously.The source electrode of PMOS pipe P15 is connected to supply voltage VDDH, and NMOS pipe N20 is connected to ground VSS, and the drain electrode of PMOS pipe P15 and NMOS pipe N20 is connected to holding wire ENHV simultaneously and exports this control signal converting circuit outside.

In the circuit diagram of whole embodiment, as Fig. 4 and Fig. 5, metal-oxide-semiconductor P0-P5, P12-P15 and N0-N8, N17-N20 are for bearing the high-pressure MOS component of supply voltage VDDH, and metal-oxide-semiconductor P6-P11 and N9-N16 are for bearing the low pressure MOS device of supply voltage VDDL.

Fig. 6 is the circuit diagram of transmission gate TG1 among Fig. 4, is formed in parallel by a PMOS pipe PM0 and a NMOS pipe NM0.The source electrode of PM0 is connected to the port A of transmission gate TG1 with the drain electrode of NM0, and the source electrode of the drain electrode of PM0 and NM0 is connected to another port B of transmission gate TG1 together simultaneously.The grid of PM0 is connected to the negative input end N of transmission gate TG1, and the grid of NM0 is connected to the positive input terminal P of transmission gate TG1.

EN1 and EN2 are the control signals by the output of chip internal core circuit register, be used for controlling the mode of operation of configurable amplifier 101, its level amplitude is 0-VDDL, and configurable amplifier 101 directly is connected with the chip exterior signal, its working power voltage is VDDH, therefore control signal EN1 and EN2 will be carried out level conversion and exports differential signal.The control signal conversion circuit of Fig. 5 mainly is that to make the amplitude of oscillation by the positive feedback that PMOS pipe P13 and P14 form be that the CMOS level signal of VDDL converts the cmos signal that the amplitude of oscillation is VDDH to, thus metal-oxide-semiconductor P0, P1, N5, N6 and transmission gate TG1 in can control chart 4 these be suitable for the high-pressure MOS component of VDDH.

Whether in Fig. 4, resistance R 2 and R 3 are connected between differential signal INP and the INN, have been the effects of outside driver element and transmission line being carried out impedance matching, can come control transmission door TG1 to dispose these two resistance by control signal EN2 and work.Configuration EN2 is that high level can be opened transmission gate TG1, and R2 and R3 are worked, and can add build-out resistor so that this interface circuit not be used in chip exterior, the facilitating chip circuit design.PMOS manages P0, and NMOS pipe N0, N5 and resistance R 0 are formed a biasing circuit, for input signal INP provides suitable dc point.PMOS manages P1, and NMOS pipe N4, N6 and resistance R 1 are formed a biasing circuit, for input signal INN provides suitable dc point.By configuration EN1 is that low level can make PMOS pipe P0, P1 and NMOS manage N5, N6 conducting, thereby these two biasing circuit work can provide dc point.Can determine how this interface circuit uses according to the applicable cases of chip, thereby select these build-out resistors and biasing circuit whether to select for use.General this interface circuit is applicable to that input signal is LVDS and LVPECL level, and every kind of level is that data still are that clock has different usings method according to signal type, and this will describe in detail in the back.

NMOS pipe N7 and N8 amplify differential input signal INP and INN as a pair of difference pipe, make it to be fit to chip internal and handle needs.PMOS pipe P2 and P3 connect into the diode form, as the active load of differential pair N7 and N8.NMOS pipe N1 and N3 manage P2 for PMOS and P3 provides certain bias current, make that signal 111 and 112 can also not remain on a suitable level when having conducting among differential pair N7 and the N8, simultaneously also can restricting signal 111 and 112 voltage swing, select suitable voltage swing can make interface circuit be fit to specific operating frequency, the voltage swing that reduces signal 111 and 112 can improve the operating frequency of interface circuit.

Signal 111 and 112 is based on high power supply voltage VDDH generation, use if be directly inputted in the internal core circuit, can therefore to carry out level conversion because overtension burns MOS device in the internal core circuit, make it to become the signal of suitable internal core circuit power voltage VDDL.Signal 111 and 112 common mode working point are equated by differential pair NMOS pipe, so the electric current I of passing through on PMOS pipe P4 and the P5 1 is: the electric current of the tail electric current NMOS pipe N2 of N7 and N8 and active load PMOS pipe P2 and P 3 decisions are assumed to be V _CM1Suppose channel width and the length of PMOS pipe P4 and P5

$\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="C2007100904270015H1.png,C2007100904270017H1.png"\; state="\{\{state\}\}">I</figure-callout>}1=\mathrm{\&beta;}\frac{W1}{L1}{(\mathrm{VDDH}-V_{\mathrm{CM}1}-|\mathrm{Vtp}\left|\right)}^2---\left(1\right)$

In following formula (1), W1, L1 are channel width and the length of PMOS pipe P4 and P5.Then NMOS manages the V of N9 _GsFor:

$2\mathrm{<figure-callout\; id="1"\; label="I"\; filenames="C2007100904270015H1.png,C2007100904270017H1.png"\; state="\{\{state\}\}">I</figure-callout>}1=\mathrm{\&beta;}\frac{W2}{L2}{(V_{\mathrm{gs}}-\mathrm{Vtn})}^2\&DoubleRightArrow;$

$2\mathrm{\&beta;}\frac{W1}{L1}{(\mathrm{VDDH}-V_{\mathrm{CM}1}-|\mathrm{Vtp}\left|\right)}^2=\mathrm{\&beta;}\frac{W2}{L2}{(V_{\mathrm{gs}}-\mathrm{Vtn})}^2\&DoubleRightArrow;$

$V_{\mathrm{gs}}=\sqrt{\frac{2(\mathrm{<figure-callout\; id="1"\; label="W"\; filenames="C2007100904270015H1.png,C2007100904270017H1.png"\; state="\{\{state\}\}">W</figure-callout>}1/L1)}{(\mathrm{<figure-callout\; id="2"\; label="W"\; filenames="C2007100904270015H1.png"\; state="\{\{state\}\}">W</figure-callout>}2/L2)}}(\mathrm{VDDH}-V_{\mathrm{CM}1}-|\mathrm{Vtp}\left|\right)+\mathrm{Vtn}---\left(2\right)$

In the following formula (2), W2, L2 are channel width and the length of NMOS pipe N9, and Vtp and Vtn are respectively the threshold voltage of PMOS pipe and NMOS pipe, and the common mode working point V of signal 113 and 114 _CM2Be V _Gs, therefore have:

${\mathrm{<figure-callout\; id="2"\; label="V\; CM"\; filenames="C2007100904270015H1.png"\; state="\{\{state\}\}">V</figure-callout>}}_{\mathrm{CM}}=\sqrt{\frac{2(\mathrm{<figure-callout\; id="1"\; label="W"\; filenames="C2007100904270015H1.png,C2007100904270017H1.png"\; state="\{\{state\}\}">W</figure-callout>}1/L1)}{(\mathrm{<figure-callout\; id="2"\; label="W"\; filenames="C2007100904270015H1.png"\; state="\{\{state\}\}">W</figure-callout>}2/L2)}}(\mathrm{VDDH}-V_{\mathrm{CM}1}-|\mathrm{Vtp}\left|\right)+\mathrm{Vtn}---\left(3\right)$

Suppose R4=R5=R, signal 113 with the differential mode voltage of signal 114 is:

V _d＝2I1*R (4)

According to above-mentioned (3) formula and (4) formula, W1/L1 and W2/L2 rationally are set, just can make it to be suitable for the need of work of low pressure MOS device so that the voltage of signal 113 and 114 is between VSS and the VDDL, arrive the purpose of level conversion.

In Fig. 4, PMOS pipe P6, P7 and NMOS pipe N10, N11, N12 form the difference amplifier of an automatic biasing, realize converting the signal 113 and 114 of difference to single-ended signal 115.So-called automatic biasing is meant that the tail electric current supplier of this NMOS pipe differential pair N10 of NMOS pipe N12 and N11 does not adopt applying bias voltage to set its working point, but has adopted the active load PMOS of NMOS pipe N10 to manage the grid voltage of P6 as its bias voltage.Signal 115 is single-ended signals that are between VDDL and the VSS, by just having become the single-ended signal OUT of CMOS level behind the output buffer of being made up of PMOS pipe P8, P9 and NMOS pipe N13, N14, the internal core circuit just can be further processed signal OUT like this.

In Fig. 4, if select R2=R3=50 Ω, then two port INP and INN have accomplished impedance matching to the transmission line of outside 50 Ω.When input signal INP and INN are the LVDS signal, if select EN1 and EN2 be simultaneously high level just can, resistance R 2 is directly connected R3, and with two dc bias circuits disconnections.This moment, the configurable amplifier 101 of this interface circuit was simplified to shown in Figure 7ly, need not add build-out resistor to port again in chip exterior, the external circuit in the time of so just can the facilitating chip use, reduction use cost.

When EN1 is set is high level and EN2 is a low level, then the dc bias circuit in the configurable amplifier 101 and build-out resistor R2 and R3 has been opened from circuit interruption, and it simplifies circuit as shown in Figure 8.This configuration mode is applicable to that promptly LVDS also is applicable to the LVPECL signal.When input signal is the LVDS signal, need between INP/INN, increase to be similar to the R2 configuration resistance the same with R3.When input signal is LVPECL, need be that interface circuit carries out the dc point setting in chip exterior, and whether decision do impedance matching according to operating position.

EN1 is set is low level and EN2 is a high level, then the dc bias circuit in the configurable amplifier 101 and build-out resistor R2 and R 3 have been connected in the interface circuit, it simplifies circuit as shown in Figure 9.This moment, interface circuit can directly adopt the mode of AC coupling to connect, and the external circuit that chip uses is the simplest.

EN1 is set and EN2 is low level, the dc bias circuit in the then configurable amplifier 101 has been connected in the interface circuit, and build-out resistor R2 and R3 have been broken from interface circuit, and it simplifies circuit as shown in figure 10.At this moment, interface circuit is suitable for directly adopting the mode of AC coupling to connect, but needs to require to determine whether needs carry out impedance matching according to chip.

In the actual realization of circuit, according to the processing technology difference, the concrete voltage of VDDH and VDDL may be different.General processing producer can both provide the IO voltage VDDH of 2.5V and 3.3V simultaneously, but the supply voltage VDDL of internal core logic is just different because of technology.In the technology of 0.18um, general internal core logic adopts the supply voltage of 1.8V, then adopts the 1.2V supply voltage in 0.13um technology, and also may adopt the supply voltage of 1V in the technology of 90nm.These all change to some extent along with different chip manufacture producers and processing technology, in this patent, have only and suitably revise the function that the partial circuit device just can be realized patent.

Present embodiment has been set forth a kind of specific implementation method of LVDS/LVPECL interface circuit at a high speed, and a lot of modules also can adopt additive method to realize.For example, can whether adopt the NMOS among Fig. 4 to manage N1 and N3, when signal frequency is low, need not increase the impulse electricity time that these two devices reduce signal, operating frequency is provided according to the signal frequency decision that patent is used.Simultaneously, dc bias circuit and impedance matching circuit also can increase and decrease according to the concrete environment for use of interface circuit.Control circuit (Fig. 5) and transmission gate TG1 (Fig. 6) also can other equivalent way realize.

The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the structure that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.

Claims (11)

1. differential signal interface circuit is characterized in that:

Comprise configurable amplifier (101), level shifting circuit (102) and double rotary single circuit (103), wherein,

Outside input differential signal INP, outside input differential signal INN are input in the configurable amplifier (101), and external control signal EN1, external control signal EN2 and reference voltage VNREF are input in the configurable amplifier (101) simultaneously;

Configurable amplifier (101) output one group of differential signal (111,112) also is input in the level shifting circuit (102); The high-tension power vd DH of outside input imports in configurable amplifier (101) and the level shifting circuit (102) simultaneously;

Level shifting circuit (102) one group of differential signal of output (113,114) enters into double rotary single circuit (103); Double rotary single circuit (103) output single-ended signal (115);

The power vd DL of outside input low-voltage is input in the double rotary single circuit (103); The high-tension power vd DH of outside input connects configurable amplifier (101) and level shifting circuit (102) simultaneously; External reference ground voltage VSS is input in configurable amplifier (101), level shifting circuit (102), the double rotary single circuit (103) as reference ground.

2. differential signal interface circuit according to claim 1 is characterized in that: the output single-ended signal (115) of double rotary single circuit (103) enters in the output buffer (104), output buffer (104) output signal OUT.

3. differential signal interface circuit according to claim 2 is characterized in that: the power vd DL of outside input low-voltage is input in double rotary single circuit (103) and the output buffer (104) simultaneously; External reference ground voltage VSS is input in the output buffer (104) as reference ground.

4. according to claim 1,2 or 3 described differential signal interface circuits, it is characterized in that: outside input differential signal INP, outside input differential signal INN are the LVDS level, or the LVPECL level.

5. according to claim 1,2 or 3 described differential signal interface circuits, it is characterized in that:

Configurable amplifier (101) is by PMOS pipe P0, P1, P2 and P3, and NMOS manages N0, N1, N2, N3, N4, N5, N6, N7 and N8, resistance R 0, R1, R2 and R3, and transmission gate TG1 and control signal converting circuit X201 and control signal converting circuit X202 form; Level shifting circuit (102) is by PMOS pipe P4, P5, and NMOS pipe N9 and resistance R 4, R5 form; Double rotary single circuit (103) is made up of PMOS pipe P6, P7 and NMOS pipe N10, N11, N12; Output buffer (104) is made up of PMOS pipe P8, P9 and NMOS pipe N13, N14.

6. differential signal interface circuit according to claim 5, it is characterized in that external control signal EN1 and external control signal EN2 are input to respectively among control signal converting circuit X201 and the control signal converting circuit X202, export a pair of difference control signal EN1HV/EN1BHV and EN2HV/EN2BHV respectively; Difference control signal EN1HV is input to the grid of PMOS pipe P0 and P1, and the source electrode of PMOS pipe P0 and P1 is all received high-tension power vd DH; An end of resistance R 0 is received in the drain electrode of PMOS pipe P0, and the other end of resistance R 0 and outside input differential signal INP are connected together; Outside input differential signal INP is connected to the drain electrode of NMOS pipe N5 simultaneously, and the grid of NMOS pipe N5 is received difference control signal EN1BHV, and the drain electrode of the source electrode of NMOS pipe N5 and NMOS pipe N0 is connected together; The grid of NMOS pipe N0 is received reference voltage VNREF, and source electrode is connected to ground VSS; Outside input differential signal INP is connected to an end of resistance R 2 simultaneously, and the other end of resistance R 2 is connected to the port (A) of transmission gate TG1; Outside input differential signal INP is input to the grid of NMOS pipe N7 simultaneously, and the source electrode of NMOS pipe N7 is connected to the drain electrode of NMOS pipe N2, and the drain electrode of NMOS pipe N7 connects first holding wire (111); First holding wire (111) is connected to grid and the drain electrode of PMOS pipe P2 simultaneously, forms diode and connects; First holding wire (111) is connected to the drain electrode of NMOS pipe N1 simultaneously, and the grid of NMOS pipe N1 is connected to reference voltage VNREF, and source electrode is connected to ground VSS; The drain electrode of PMOS pipe P1 is connected to an end of resistance R 1, and the other end of resistance R 1 and outside input differential signal INN link together; Outside input differential signal INN is connected to the drain electrode of NMOS pipe N6 simultaneously, and the grid of NMOS pipe N6 is received difference control signal EN1BHV, and the drain electrode of the source electrode of NMOS pipe N6 and NMOS pipe N4 is connected together; The grid of NMOS pipe N4 is received reference voltage VNREF, and source electrode is connected to ground VSS; Outside input differential signal INN is connected to an end of resistance R 3 simultaneously, and the other end of resistance R 3 is connected to another port (B) of transmission gate TG1; Outside input differential signal INP is input to the grid of NMOS pipe N8 simultaneously, and the source electrode of NMOS pipe N8 is connected to the drain electrode of NMOS pipe N2, and the drain electrode of NMOS pipe N8 connects secondary signal line (112); Secondary signal line (112) is connected to grid and the drain electrode of PMOS pipe P3 simultaneously, forms diode and connects; Secondary signal line (112) is connected to the drain electrode of NMOS pipe N3 simultaneously, and the grid of NMOS pipe N3 is connected to reference voltage VNREF, and source electrode is connected to ground VSS; Transmission gate TG1 positive input terminal P meets difference control signal EN2HV, and negative input end N meets difference control signal EN2BHV.

7. differential signal interface circuit according to claim 5 is characterized in that first holding wire (111) is connected to the grid of PMOS pipe P4, and the source electrode of PMOS pipe P4 meets high-tension power vd DH, and the drain electrode of PMOS pipe P4 is connected to the 3rd holding wire (113); The 3rd holding wire (113) is connected to an end of resistance R 4 simultaneously, and the other end of resistance R 4 is connected to the 6th holding wire (116); Secondary signal line (112) is connected to the grid of PMOS pipe P5, and the source electrode of PMOS pipe P5 meets high-tension power vd DH, and the drain electrode of PMOS pipe P5 is connected to the 4th holding wire (114); The 4th holding wire (114) is connected to an end of resistance R 5 simultaneously, and the other end of resistance R 5 is connected to the 6th holding wire (116); The 6th holding wire (116) is connected to grid and the drain electrode of NMOS pipe N9 simultaneously, and the source electrode of NMOS pipe N9 is connected to ground VSS.

8. differential signal interface circuit according to claim 5, it is characterized in that the 3rd holding wire (113) is connected to the grid of NMOS pipe N11, the drain electrode of NMOS pipe N11 is connected to the 5th holding wire (115), and the source electrode of NMOS pipe N11 is connected to the 7th holding wire (117); The 5th holding wire (115) is connected to the drain electrode of PMOS pipe P7 simultaneously, and the grid of PMOS pipe P7 is connected to grid and the drain electrode of PMOS pipe P6, and the source electrode of PMOS pipe P7 is connected to the power vd DL of low-voltage; The 4th holding wire (114) is connected to the grid of NMOS pipe N10, and the drain electrode of NMOS pipe N10 is connected to grid and the drain electrode of PMOS pipe P6, and the source electrode of NMOS pipe N10 is connected to the 7th holding wire (117); The 7th holding wire (117) is connected to the drain electrode of NMOS pipe N12 simultaneously, and the source electrode of NMOS pipe N12 is connected to ground VSS; The grid of PMOS pipe P6 and drain electrode simultaneously is connected to the grid of NMOS pipe N12 together, and the source electrode of PMOS pipe P6 is connected to the power vd DL of low-voltage.

9. differential signal interface circuit according to claim 5 is characterized in that the 5th holding wire (115) is input to the grid of PMOS pipe P8 and NMOS pipe N13, and the source electrode of PMOS pipe P8 is connected to the power vd DL of low-voltage, and the source electrode of NMOS pipe N13 connects ground VSS; The drain electrode of PMOS pipe P8 and NMOS pipe N13 links together and outputs to the grid of PMOS pipe P9 and NMOS pipe N14; The source electrode of PMOS pipe P9 is connected to the power vd DL of low-voltage, and the source electrode of NMOS pipe N14 connects ground VSS; The drain electrode of PMOS pipe P8 and NMOS pipe N13 is connected to output signal OUT together.

10. differential signal interface circuit according to claim 5, it is characterized in that among described control signal converting circuit X201 and the control signal converting circuit X202, input signal EN is connected to the grid of PMOS pipe P10 and NMOS pipe N15, the source electrode of PMOS pipe P10 is connected to the power vd DL of low-voltage, and the source electrode of NMOS pipe N15 connects ground VSS; The drain electrode of PMOS pipe P10 and NMOS pipe N15 links together, and outputs to the grid of PMOS pipe P11 and NMOS pipe N16, and the drain electrode of PMOS pipe P10 and NMOS pipe N15 simultaneously links together and also outputs to the grid of NMOS pipe N18; The source electrode of PMOS pipe P11 is connected to the power vd DL of low-voltage, and the source electrode of NMOS pipe N16 connects ground VSS, and the drain electrode of PMOS pipe P11 and NMOS pipe N16 links together and outputs to the grid of NMOS pipe N19; The source electrode of NMOS pipe N18 is connected to ground VSS, and drain electrode is connected to the 8th holding wire (301); The 8th holding wire (301) is connected to the drain electrode of PMOS pipe P13 and the grid of PMOS pipe P14 simultaneously, and the source electrode of PMOS pipe P13 is connected to high-tension power vd DH; The 8th holding wire (301) is connected to the grid of PMOS pipe P12 and the grid of NMOS pipe N17 simultaneously; The source electrode of PMOS pipe P12 is connected to high-tension power vd DH, and NMOS pipe N17 is connected to ground VSS, and the drain electrode of PMOS pipe P12 and NMOS pipe N17 is connected to holding wire ENBHV simultaneously and exports this control signal converting circuit outside; The source electrode of NMOS pipe N19 is connected to ground VSS, and drain electrode is connected to the 9th holding wire (302); The 9th holding wire (302) is connected to the drain electrode of grid and the PMOS pipe P14 of PMOS pipe P13 simultaneously; The source electrode of PMOS pipe P14 is connected to high-tension power vd DH; The 9th holding wire (302) is connected to the grid of PMOS pipe P15 and the grid of NMOS pipe N20 simultaneously; The source electrode of PMOS pipe P15 is connected to high-tension power vd DH, and NMOS pipe N20 is connected to ground VSS, and the drain electrode of PMOS pipe P15 and NMOS pipe N20 is connected to holding wire ENHV simultaneously and exports this control signal converting circuit outside.

11. differential signal interface circuit according to claim 5 is characterized in that described transmission gate TG1, is formed in parallel by a PMOS pipe PM0 and a NMOS pipe NM0; The source electrode of PMOS pipe PM0 is connected to the port (A) of transmission gate TG1 with the drain electrode of NMOS pipe NM0, and the source electrode of the drain electrode of PMOS pipe PM0 simultaneously and NMOS pipe NM0 is connected to another port (B) of transmission gate TG1 together; The grid of PMOS pipe PM0 is connected to the negative input end N of transmission gate TG1, and the grid of NMOS pipe NM0 is connected to the positive input terminal P of transmission gate TG1.

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