CN100555572C - 半导体装置的制造方法 - Google Patents

半导体装置的制造方法 Download PDF

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CN100555572C
CN100555572C CNB2005800009005A CN200580000900A CN100555572C CN 100555572 C CN100555572 C CN 100555572C CN B2005800009005 A CNB2005800009005 A CN B2005800009005A CN 200580000900 A CN200580000900 A CN 200580000900A CN 100555572 C CN100555572 C CN 100555572C
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森谷敦
井之口泰启
国井泰夫
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International Electric Co., Ltd.
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Abstract

本发明提供一种在晶片130的Si表面选择成长含Si的外延膜的热壁式衬底处理装置，该装置具有收纳晶片130的处理室108，配置在处理室108的外部、加热晶片130的加热部件101，连接处理室108的原料气体供给系统115，排气系统116；使用上述装置，与晶片130的选择成长面相对向地配置Si膜露出的部件，在晶片130上选择成长含Si的外延膜。

Description

半导体装置的制造方法
技术领域
本发明涉及衬底处理装置及半导体装置的制造方法，特别涉及利用热壁式竖型CVD(Chemical Vapor Deposition)装置、热壁式横型CVD装置等热壁式CVD装置在Si晶片等衬底上选择成长Si或SiGe等外延膜的衬底处理装置及使用该衬底处理装置的半导体装置制造方法。
背景技术
在MOSFET(Metal Oxide Semiconductor Field Effect Transistor)中，用于抑制伴随门长微细化的短沟道效果的称为加高源极/漏极(或高架源极/漏极)的技术备受注目。
形成了加高源极/漏极的MOSFET 10的纵剖面简图如图1所示。在被元件分离区域12包围的元件形成硅区域11上，经由门绝缘膜17，形成门电极20。在门电极20的侧面形成侧壁18，在门电极20的上面形成门保护膜19。在元件形成硅区域11，对门电极20自对准地形成源极13及漏极14。仅在源极13及漏极14上分别选择形成加高源极15及加高漏极16。加高源极15及加高漏极16通常利用称为选择成长的技术来形成，该技术仅在Si露出的源极13、漏极14上外延成长Si或SiGe，在其他SiO2或SiN等露出的元件分离区域12等区域内不成长任何膜。
作为Si或SiGe的选择成长的原料气体，使用SiH4或Si2H6、SiH2Cl2等含Si气体，在SiGe的情况下，增加GeH4等含Ge气体。在CVD反应中，如果导入原料气体，则在Si上立刻开始成长，与此相反，在SiO2或SiN上发生称为潜伏期间的成长延迟。在该潜伏期间，仅在Si上成长Si或SiGe，此现象即为选择成长。
发明内容
选择成长几乎全部使用冷壁式枚叶CVD装置。这是因为在热壁式CVD装置的情况下，在高温的石英制外管或内管、舟皿、或邻接的高温的晶片表面，SiH4或Si2H6、SiH2Cl2等原料气体分解成反应性高的SiHx，到达SiO2或SiN上。与SiH4等相比，SiHx在SiO2或SiN上的反应概率高，因此潜伏期间短，导致无法选择成长或可以选择成长的膜厚变得极薄。
但是，随选择成长需要的增加，由于采用冷壁式枚叶装置的生产率低，因此，利用生产率更高的热壁式CVD装置进行选择成长的要求逐渐提高。
因此，本发明的主要目的是提供一种衬底处理装置及使用该衬底处理装置的半导体装置制造方法，该装置是热壁式竖型减压CVD装置或热壁式横型减压CVD装置等热壁式CVD装置，能够进行Si或SiGe的选择成长。
本发明的一个方案提供一种衬底处理装置，是具有以下部分的热壁式衬底处理装置：
收纳至少一个制品用衬底的处理室，
配置在上述处理室的外部、加热上述制品用衬底的加热部件，
连接上述处理室的处理气体供给系统、和排气系统；
该装置能在上述制品用衬底的Si表面选择成长含Si的外延膜；
其中，与上述制品用衬底的选择成长面相对向地配置Si膜露出的部件，在上述制品用衬底上选择成长含Si的外延膜。
另外，本发明的其他方案提供一种衬底处理装置，是具有以下部分的热壁式衬底处理装置：
收纳至少一个制品用衬底的处理室，
配置在上述处理室的外部、加热上述制品用衬底的加热部件，
连接上述处理室的处理气体供给系统、和排气系统；
在上述制品用衬底的一部分选择成长Si或SiGe膜；
其中，与上述制品用衬底的选择成长面相对向地配置与上述制品用衬底不同的其他衬底，即，与在背面露出Si膜的上述制品用衬底不同的其他衬底，在上述制品用衬底上选择成长Si或SiGe膜。
另外，本发明的另一个方案提供一种半导体装置制造方法，该制造方法包括以下工序：使用热壁式衬底处理装置，与上述制品用衬底的选择成长面相对向地配置Si膜露出的部件，在上述制品用衬底的Si表面选择成长含Si的外延膜；
上述热壁式衬底处理装置具有以下部分：
收纳至少一个制品用衬底的处理室，
配置在上述处理室的外部、加热上述制品用衬底的加热部件，
连接上述处理室的处理气体供给系统、排气系统。
另外，本发明的再一个方案提供一种半导体装置制造方法，该方法包括以下工序：使用热壁式衬底处理装置，与上述制品用衬底的选择成长面相对向地配置与上述制品用衬底不同的其他衬底，即，与在背面露出Si膜的上述制品用衬底不同的其他衬底，在上述制品用衬底上选择成长Si或SiGe膜；
上述热壁式衬底处理装置具有以下部分：
收纳至少一个制品用衬底的处理室，
配置在上述处理室的外部、加热上述制品用衬底的加热部件，
连接上述处理室的处理气体供给系统、排气系统。
附图说明
图1为用于说明形成了加高源极/漏极的MOSFET构造的纵剖面简图。
图2为用于说明热壁式竖型减压CVD装置的纵剖面简图。
图3为用于说明热壁式竖型减压CVD装置的反应炉的纵剖面简图。
图4为用于说明形成在制品晶片的背面露出Epi-Si或Poly-Si的晶片时的本发明实施例的纵剖面简图。
图5为用于说明在制品晶片的正上方配置Epi-Si或Poly-Si露出的虚设晶片时的本发明实施例的纵剖面简图。
图6表示未实施本发明的比较例的成膜。
图7表示本发明实施例的情况下的成膜。
具体实施方式
下面，说明本发明的优选实施例。
在MOSFET中，利用竖型热壁式CVD炉，仅在Si露出的源极/漏极部选择成长Epi-Si或Epi-SiGe膜时，如果使用SiH4或Si2H6等含Si气体，则SiH4等原料气体由炉内的高温部分(反应管等)获得热量，不仅在晶片表面、而且在气相中分解为反应性高的SiHx，导致其到达不希望选择成长SiHx的SiO2或SiN上，并发生反应，从而缩短潜伏期间，无法进行选择成长、或即使能够进行选择成长也形成极薄的膜。在本发明的实施例中，将多个制品用晶片(制品晶片)在垂直方向层叠配置，在Si或SiGe的选择成长中，使制品晶片的背面为Epi-Si(EpitaxialSilicon)或Poly-Si(Polycrystalline Silicon)，在各制品晶片的进行选择成长面的正上方，配置其上制品晶片的形成了Epi-Si或Poly-Si的背面，或在各制品晶片的进行选择成长面的正上方，配置Epi-Si或Poly-Si至少在背面露出的虚设晶片，在热壁式CVD装置中进行选择成长。通过在制品晶片的正上方，配置背面为Epi-Si或Poly-Si的制品晶片、或、Epi-Si或Poly-Si露出的虚设晶片，使制品晶片正上方的Epi-Si或Poly-Si吸附SiHx，降低制品晶片表面的SiHx的存在率。结果延长了SiO2或SiN等非成长区域的潜伏期间，可以仅在Si露出的源极/漏极部较厚地选择成长Epi-Si或Epi-SiGe膜。
如果炉内压力低，则由于原料气体的存在概率低，因此原料气体的自分解气体(SiHx)量少，在不欲选择成长的SiO2或SiN上的SiHx的潜伏期间未变短，因此可以进行选择成长，但是由于原料气体的存在概率低，因此成长速度变小，仅成长较薄的膜。
在本实施例中，在制品晶片的正上方配置背面为Epi-Si或Poly-Si的制品晶片、或、Epi-Si或Poly-Si露出的虚设晶片，使Epi-Si或Poly-Si吸附SiHx，降低制品晶片表面的SiHx的存在率，因此，即使在选择成长时的原料气体压力高的情况下，也可以延长SiO2或SiN等非成长区域内的潜伏期间，可以仅在Si露出的源极/漏极部较厚地选择成长Epi-Si或Epi-SiGe膜。选择成长时的处理室压力优选为0.1～1000Pa，更优选为1～200Pa，进一步优选为1～100Pa，在本实施例中约为20Pa。
需要说明的是，希望使选择成长的膜厚较厚时，根据延长SiO2或SiN上的潜伏期间的目的，也可以添加HCl或Cl2等腐蚀性气体。
实施例1
下面，参照附图，更详细地说明本发明的实施例。
图2为用于说明本实施例的热壁式竖型减压CVD装置的纵剖面简图，图3为用于说明本实施例的热壁式竖型减压CVD装置的反应炉的纵剖面简图。
本实施例的热壁式竖型减压CVD装置200具备反应炉100、控制装置141、气体供给装置142、真空排气装置143。参照图3，反应炉100具备基座112、设置在其上的歧管111、外管103、设置在其内部的内管104、设置在外管103的外部的加热器101、包覆加热器101和外管103地设置的绝热材料102。利用加热器101和绝热材料102将外管103内部整体加热。外管103设置在歧管111的上部凸缘118上，内管104设置在歧管111的中段朝内侧突起的凸缘119上。
在密封盖113上搭载舟皿105。如果搭载舟皿105的密封盖113由基座112的开口120插入，升高密封盖113，由密封盖113封闭开口120，则使舟皿105位于内管104内。舟皿105由旋转机构114旋转。在舟皿105上垂直方向层叠搭载多个晶片130。内管104内成为处理晶片130的处理室108。在舟皿下部相当于歧管111的高度部分搭载绝热板107。
在歧管111的侧壁安装排气管116，排气管116连接真空排气装置143。贯穿密封盖113地设置供给管115。供给管115连接在气体供给装置142上。作为Si或SiGe的选择成长原料气体的SiH4、Si2H6、SiH2Cl2、GeH4等由供给管115从内管104的下部导入。然后，升至内管104内后，穿过外管103和内管104之间的间隙，由连接在排气管116上的真空排气装置143进行排气。
降下密封盖113，将舟皿105从内管104内搬出后，由门阀117(参见图2)，封闭基座112的开口120。参照图2，在如上所述地搬出到处理炉100下部的舟皿105和晶片盒152之间设置移载晶片130的移载机151。
加热器101、气体供给装置142、真空排气装置143、旋转机构114、门阀117、移载机151由控制装置141控制。
由晶片盒152投入的晶片(Si衬底)130被移载机151从晶片盒152移载到舟皿105内。晶片105全部移载完成后，将舟皿105插入内管104内，由真空排气装置143将外管103内减压。然后，利用加热器101加热至所希望的温度，温度稳定时，利用气体供给装置142经由供给管115供给原料气体，在晶片(Si衬底)130上，利用CVD反应选择成长Si或SiGe。
需要说明的是，晶片130分为制品晶片、虚设晶片、控制晶片，进而将虚设晶片分为侧面虚设晶片和制品虚设晶片。制品晶片实际上是制成IC等半导体元件的晶片，控制晶片是制作半导体元件时用于控制是否进行所希望的成膜的晶片。制品虚设晶片是在制品晶片上存在缺口时，由于此处气流紊乱或温度均一性变得不均，因此为了防止由此导致的成膜不良而填埋该缺口部的晶片。另外，侧面虚设晶片是包夹制品晶片地配置在舟皿的两端、防止制品晶片区域的热量漏出或防止从反应炉上下飞来的微粒或污染物质附着在制品晶片上的晶片。
在热壁式的情况下，如图3所示，外管103、内管104、舟皿105等石英类与晶片130一同被加热器101加热。此处，如果作为选择成长原料气体的SiH4或Si2H6或SiH2Cl2由气体导入管115供给，则由高温的石英类或晶片130获得热量，不仅在晶片表面、而且在反应炉内的气相中分解成反应性高的SiHx。在选择成长时，希望仅在制品晶片的露出Si的区域(成长区域)成长Si或SiGe，不希望在SiO2或SiN等露出的区域(非成长区域)成长，但是，由于在气相中分解成SiHx，因此上述SiHx容易到达非成长区域，因反应性高而在非成长区域也立即成膜。
在本实施例中，通过制成制品晶片的背面露出Epi-Si或Poly-Si的晶片、或在制品晶片的正上方配置Epi-Si或Poly-Si露出的虚设晶片，总之在任一种情况下均使制品晶片的正上方为Epi-Si或Poly-Si，能够吸附反应性高的SiHx，降低制品晶片表面的SiHx的存在概率。
图4为制品晶片131的背面露出Epi-Si或Poly-Si的晶片时的纵剖面简图，图5为在制品晶片131的正上方配置Epi-Si或Poly-Si的硅层133露出的虚设晶片132时的纵剖面简图。
Epi-Si、Poly-Si等的Si的反应效率比SiO2高约103倍，比SiN高约102倍，因此能够效率良好地捕捉SiHx。由此降低制品晶片131表面的SiHx的存在概率，可以延长非成长区域的潜伏期间。
需要说明的是，将表面形成了Poly-Si的虚设晶片132配置在制品晶片131的正上方的情况下，在将仅搭载虚设晶片132的舟皿105放入反应炉100内、未放入制品晶片131的状态下，通入原料气体，在虚设晶片132上形成Poly-Si，然后，将舟皿105从反应炉100内取出，然后，将制品晶片132搭载在舟皿105上，再将舟皿105插入反应炉100内，进行选择成长。
图6为在制品晶片的正上方的晶片背面露出SiO2时的成膜结果。由图6可知，在作为非成长区域的SiO2上成膜，阻止选择成长。另外，在制品晶片的正上方的晶片背面露出Poly-Si时的成膜结果如图7所示。可知仅在作为成长区域的Si上成长Si，未在作为非成长区域的SiO2上成膜，进行选择成长。
需要说明的是，此时的工序条件如表1所示。
表1
 成膜温度   760℃
 SiH<sub>2</sub>Cl<sub>2</sub>分压   1.3Pa
 HCl分压   0.4Pa
 H<sub>2</sub>分压   20.3Pa
 总压力   22.0Pa
由以上说明可知，在制品晶片的背面露出Epi-Si或Poly-Si的晶片、或在制品晶片的正上方配置Epi-Si或Poly-Si露出的虚设晶片，效率良好地捕捉反应性高的SiHx，由此解决在非成长区域成膜Si或SiGe的问题，可以仅在成长区域选择成长Si或SiGe。
需要说明的是，本发明不仅可以适用于MOSFET时加高源极/漏极的选择成长，也适用于自对准型SiGe-HBT(Hetero-bipolartransistor)基底层的选择成长等其他选择成长。
2004年3月11日提出的日本专利申请2004-69588中公开的全部内容，包括说明书、权利要求书、附图以及说明书摘要被直接引用并编入本申请中。
虽然给出各种典型的实施方案并进行了说明，但本发明并不受到上述实施方案的限定。本发明的范围仅由权利要求书进行限定。
产业实用性
如上所述，本发明的一个方案提供一种热壁式CVD装置、即能够进行Si或SiGe的选择成长的衬底处理装置及使用该衬底处理装置的半导体装置制造方法。
结果本发明特别优选用于利用热壁式CVD装置在Si晶片等衬底上选择成长Si或SiGe等外延膜的衬底处理装置及使用该衬底处理装置的半导体装置制造方法。

Claims (14)

1.一种半导体装置制造方法，其特征为，该方法包括以下工序：使用热壁式衬底处理装置，在处理室内进行使Si在虚设晶片的背面露出的处理，然后，将所述制品用衬底移载到搭载有背面露出Si的虚设晶片的衬底搭载部件上，使所述制品用衬底的选择成长面与所述虚设晶片的Si露出的背面直接对向地进行配置，在所述制品用衬底的Si表面选择成长含Si的外延膜；
所述热壁式衬底处理装置具有以下部分：
收纳至少一个制品用衬底的处理室，
配置在所述处理室的外部、加热所述制品用衬底的加热部件，
连接所述处理室的处理气体供给系统、和排气系统。
2.如权利要求1所述的半导体装置制造方法，其中，将至少2个所述制品用衬底移载到搭载有至少2个所述虚设晶片的所述衬底搭载部件上，在所述衬底搭载部件上，在垂直方向交替层叠搭载至少2个所述制品用衬底和至少2个所述虚设晶片，使至少2个所述虚设晶片的背面分别位于至少2个所述制品用衬底的所述选择成长面的正上方。
3.如权利要求1所述的半导体装置制造方法，其中，在所述背面露出外延Si膜。
4.如权利要求1所述的半导体装置制造方法，其中，在所述背面露出多晶硅膜。
5.如权利要求1所述的半导体装置制造方法，其中，被供给到所述处理室内的处理气体在气层中到达所述制品用衬底前分解的物质被吸附在所述Si的露出部。
6.如权利要求1所述的半导体装置制造方法，其中，所述选择成长时的压力为0.1～1000Pa。
7.如权利要求6所述的半导体装置制造方法，其中，所述选择成长时的压力为1～200Pa。
8.一种半导体装置制造方法，其特征为，该方法包括以下工序：使用热壁式衬底处理装置，在处理室内，进行使Si在与制品用衬底不同的其他衬底的背面上露出的处理，然后将所述制品用衬底移载到搭载有所述背面露出Si的其他衬底的衬底搭载部件上，使所述制品用衬底的选择成长面与所述其他衬底的Si露出的背面直接对向地配置，在所述制品用衬底上选择成长Si或SiGe膜；
所述热壁式衬底处理装置具有以下部分：
收纳至少一个制品用衬底的处理室，
配置在所述处理室的外部、加热所述制品用衬底的加热部件，
连接所述处理室的处理气体供给系统和、排气系统。
9.如权利要求8所述的半导体装置制造方法，其中，将多个所述制品用衬底移载到搭载有多个所述其他衬底的所述衬底搭载部件上，在所述衬底搭载部件上，在垂直方向上交替层叠搭载多个所述制品用衬底与多个所述其他衬底，使多个所述其他衬底的背面分别位于多个所述制品用衬底的选择成长面的正上方。
10.如权利要求8所述的半导体装置制造方法，其中，在所述其他衬底的背面露出外延Si膜。
11.如权利要求8所述的半导体装置制造方法，其中，在所述其他衬底的背面露出多晶硅膜。
12.如权利要求8所述的半导体装置制造方法，其中，被供给到所述处理室内的处理气体在气层中到达所述制品用衬底前分解的物质被吸附在所述Si的露出部。
13.如权利要求8所述的半导体装置制造方法，其中，所述选择成长时的压力为0.1～1000Pa。
14.如权利要求13所述的半导体装置制造方法，其中，所述选择成长时的压力为1～200Pa。
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