CN100552901C

CN100552901C - High voltage PMOS transistor and manufacture method thereof

Info

Publication number: CN100552901C
Application number: CNB2006101182958A
Authority: CN
Inventors: 钱文生
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2006-11-13
Filing date: 2006-11-13
Publication date: 2009-10-21
Anticipated expiration: 2026-11-13
Also published as: CN101183648A

Abstract

The invention discloses a kind of high voltage PMOS transistor and manufacture method thereof, can solve the contradiction that can't obtain superior performance between the puncture voltage of high voltage PMOS transistor and the saturation current simultaneously.Described manufacture method comprises: carry out high pressure N trap and P type buried channel ion and inject; Carrying out lightly doped p type diffusion region ion injects; Carry out the deposit of gate oxide; Carry out the polysilicon gate deposit that the N type mixes; Carry out polysilicon gate and gate oxide etching; Carrying out self aligned lightly-doped source ion injects; Carry out the deposit and the etching of side wall; Make and hide N type polysilicon bar and p type diffusion region with photoresist, carry out the source and leak ion injection formation P type polysilicon bar and source-drain electrode; Remove photoresist.Described high voltage PMOS transistor comprises: polysilicon gate, form by N type polysilicon bar that respectively accounts for the certain-length ratio and P type polysilicon bar.

Description

High voltage PMOS transistor and manufacture method thereof

Technical field

The present invention relates to a kind of manufacture method of high voltage PMOS transistor, relate in particular to a kind of manufacture method with high voltage PMOS transistor of different doping type grid.The invention still further relates to a kind of high voltage PMOS transistor.

Background technology

The PMOS of high tension apparatus generally is the buried channel device, with raising mobility of charge carrier rate and drive current, thus all include only the N type polysilicon bar in the high voltage PMOS, specifically as shown in Figure 1.Simultaneously, in order to improve puncture voltage, very progressive junction is all adopted in the high tension apparatus diffusion region, so just needs bigger channel length, so drive current still is difficult to be improved simultaneously.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of manufacture method of high voltage PMOS transistor, can solve for high voltage PMOS transistor and can't obtain contradiction between high-breakdown-voltage and the high saturation current simultaneously.The present invention also provides a kind of high voltage PMOS transistor for this reason.

For solving the problems of the technologies described above, the invention provides a kind of manufacture method of high voltage PMOS transistor, comprising:

(1) carrying out high pressure N trap and P type buried channel ion injects;

(2) carrying out lightly doped p type diffusion region ion injects;

(3) carry out the deposit of gate oxide;

(4) carry out the polysilicon gate deposit that the N type mixes;

(5) carry out polysilicon gate and gate oxide etching;

(6) carrying out self aligned lightly-doped source ion injects;

(7) carry out the deposit and the etching of side wall;

(8) make and hide N type polysilicon bar and p type diffusion region with photoresist, carry out the source and leak ion and inject and form P type polysilicon bar and source-drain electrode;

(9) remove photoresist.

The present invention also provides a kind of high voltage PMOS transistor, comprising: high pressure N trap substrate; On described substrate, be formed with gate oxide; And in described substrate, being formed with P type source region, P type drain region, p type diffusion region and P type buried channel, described p type diffusion region is formed between P type drain region, P type buried channel and the gate oxide; Be formed with polysilicon gate on described gate oxide, described polysilicon gate is made up of P type polysilicon bar and N type polysilicon bar, and wherein said P type polysilicon bar is formed on the direction near P type source region.

The present invention has adopted technique scheme, has following beneficial effect, promptly by in the manufacturing process of the high voltage PMOS transistor of routine, adding is injected at the P type ion of source polysilicon gate, make the transistorized part polysilicon gate of PMOS be doped to the P type, remaining part is then kept the N type, thereby has solved the contradiction that can't obtain superior performance between the puncture voltage of high voltage PMOS transistor and the saturation current simultaneously; And, in manufacture process,, go back the saturation current of scalable high voltage PMOS, thereby obtain the PMOS transistor of different characteristics by changing N type and P type length ratio partly in the polysilicon gate.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 shows the sectional structure chart of high voltage PMOS transistor of the prior art;

Fig. 2 shows the silicon chip sectional structure chart that carries out high pressure N trap and the injection of P type buried channel ion;

Fig. 3 shows and carries out the silicon chip sectional structure chart that lightly doped p type diffusion region ion injects;

Fig. 4 shows the silicon chip sectional structure chart after the deposit of carrying out gate oxide;

Fig. 5 shows the silicon chip sectional structure chart after the polysilicon gate deposit of carrying out the doping of N type;

Fig. 6 shows the silicon chip sectional structure chart that carries out after polysilicon gate and the gate oxide etching;

Fig. 7 shows the silicon chip sectional structure chart that carries out after autoregistration gets the injection of lightly-doped source ion;

Fig. 8 shows the deposit of carrying out side wall and the silicon chip sectional structure chart after the etching;

Fig. 9 shows the silicon chip sectional structure chart that has formed behind P type polysilicon bar and the source-drain electrode;

Figure 10 shows the sectional structure chart of high voltage PMOS transistor of the present invention.

Embodiment

The manufacture method of high voltage PMOS transistor of the present invention is as follows:

Be sectional structure chart according to manufacturing high pressure RMOS transistor method of the present invention as Fig. 2 to Figure 10, and particularly, Figure 10 is the sectional structure chart of the high voltage PMOS transistor that manufacturing forms according to manufacturing high voltage PMOS transistor method of the present invention.With reference to Fig. 2 to Figure 10, the concrete steps of the manufacture method of high voltage PMOS transistor of the present invention are as follows:

At first, as shown in Figure 2, on the whole surface of high pressure N trap substrate, carry out P type buried channel ion and inject;

Then, as shown in Figure 3, on high pressure N trap substrate, carry out lightly doped p type diffusion region ion and inject, form p type diffusion region, thereby reach the purpose that improves transistorized puncture voltage;

The 3rd step, as shown in Figure 4, deposit one deck gate oxide on the whole surface of high pressure N trap substrate;

In the 4th step, as shown in Figure 5, whole silicon wafer is carried out the polysilicon gate deposit that the N type mixes, thereby on gate oxide, formed one deck N type polysilicon bar;

In the 5th step, as shown in Figure 6, N type polysilicon bar and gate oxide are carried out etching;

In the 6th step, as shown in Figure 7, whole silicon wafer is carried out self aligned lightly-doped source ion inject, thereby on substrate, form P type source region;

In the 7th step, as shown in Figure 8, carry out the deposit and the etching of side wall;

The 8th step, utilize photoresist to hide N type polysilicon bar and p type diffusion region, carry out the source and leak the ion injection, form P type polysilicon bar and P type drain region.At this moment, owing in the polysilicon gate of source extreme direction, formed P type polysilicon, can make transistorized drive current be further improved.And, by in injection process, regulating the length of P type polysilicon, and when the length ratio that makes itself and N type polysilicon bar remains in 20%～50% the scope, the transistorized saturation current of scalable PMOS, thereby obtain high voltage PMOS transistor, and PMOS transistor at this moment can solve the contradiction that can't obtain superior performance between puncture voltage and the saturation current simultaneously with various different qualities.

The 9th step, remove photoresist, finish transistorized manufacturing.With reference to Figure 10, the PMOS transistor arrangement that final manufacturing forms is as follows: comprise high pressure N trap substrate; And on described substrate, be formed with gate oxide; And in described substrate, be formed with P type source region, P type drain region, p type diffusion region and P type buried channel, the structure in wherein said P type buried channel, P type source region and P type drain region is asymmetric, and described p type diffusion region then is formed between P type drain region, P type buried channel and the gate oxide; On described gate oxide, be formed with polysilicon gate, described polysilicon gate is made up of P type polysilicon bar and N type polysilicon bar, wherein said P type polysilicon bar is formed on the direction near P type source region, and the length ratio of itself and described N type polysilicon bar is in 20%～50% scope.

In sum, the present invention passes through in the manufacturing process of the high voltage PMOS transistor of routine, and the P type ion that adds at the source polysilicon gate injects, and makes the transistorized part polysilicon gate of PMOS be doped to the P type, and remaining part is then kept the N type.Thus, the channel part that the P type polysilicon bar is controlled is for exhausting raceway groove, and its threshold voltage is a positive voltage; What the N type polysilicon bar was controlled then is to strengthen raceway groove, and its threshold voltage is a negative voltage; And the threshold voltage of high voltage PMOS remains unchanged.Therefore, when adding negative voltage on the grid, really control is to strengthen channel part, is in normal open state and exhaust raceway groove, and this is just equivalent for the length of the effective raceway groove of high voltage PMOS has reduced, and drive current is improved thus.And because source-drain area, diffusion region and channel region among the present invention all remain unchanged, therefore transistorized breakdown voltage characteristics is not affected.High voltage PMOS transistor of the present invention also can be regulated the saturation current of high voltage PMOS, and do not needed to regulate other any processing step by N type and the P type length ratio partly that changes polysilicon gate in 20%～50% scope.The puncture voltage of high voltage PMOS and the contradiction between the saturation current have been solved thus.And the method for the invention also can be regulated the saturation current of high voltage PMOS, thereby obtain the PMOS transistor of different characteristics by changing N type and P type length ratio partly in the polysilicon gate.

Claims

1, a kind of manufacture method of high voltage PMOS transistor may further comprise the steps:

(1) carrying out P type buried channel ion on the whole surface of high pressure N trap substrate injects;

(2) end that carried out the high pressure N trap substrate of P type buried channel ion injection on described surface carries out lightly doped P type ion injection, forms p type diffusion region;

(3) deposit one deck gate oxide on the whole surface of high pressure N trap substrate;

(4) entire substrate is carried out the polysilicon gate deposit that the N type mixes, thereby on gate oxide, form one deck N type polysilicon bar;

(5) N type polysilicon bar and gate oxide are carried out etching, keep a place and be covered in N type polysilicon bar and gate oxide on part p type diffusion region and the part P type buried channel;

(6) inject not carried out self aligned lightly-doped source ion by the high pressure N trap substrate in the P type buried channel zone of polysilicon gate and gate oxide covering;

(7) carry out the deposit and the etching of side wall;

It is characterized in that, also comprise:

(8) make and hide the N of this place type polysilicon bar with photoresist near the part of p type diffusion region and p type diffusion region part near this place's polysilicon gate, carrying out the P ion injects, the N of this place type polysilicon bar is not formed the P type polysilicon bar by the part that photoresist hides, the part that p type diffusion region is not hidden by photoresist forms P type drain region, forms P type source region at self aligned lightly-doped source ion implanted region;

(9) remove photoresist.

2, a kind of high voltage PMOS transistor comprises: high pressure N trap substrate; On described substrate, be formed with gate oxide; And in described substrate, being formed with P type source region, P type drain region, p type diffusion region and P type buried channel, described p type diffusion region is formed between P type drain region, P type buried channel and the gate oxide; On described gate oxide, be formed with polysilicon gate, described P type buried channel is positioned under the described gate oxide, one end is separated by with P type drain region through p type diffusion region, the other end joins with P type source region, it is characterized in that, described polysilicon gate is made up of P type polysilicon bar and N type polysilicon bar, and wherein said P type polysilicon bar is formed on the direction near P type source region, and the N type polysilicon bar is formed on the direction near P type drain region.