CN101452848A

CN101452848A - MOS transistor production method and structure

Info

Publication number: CN101452848A
Application number: CNA200710094380XA
Authority: CN
Inventors: 钱文生; 吕赵鸿
Original assignee: Shanghai Hua Hong NEC Electronics Co Ltd
Current assignee: Shanghai Huahong Grace Semiconductor Manufacturing Corp
Priority date: 2007-12-06
Filing date: 2007-12-06
Publication date: 2009-06-10

Abstract

The invention discloses a method for manufacturing an MOS transistor and a structure of the MOS transistor. Through a method of twice LDD injection and primary silicon epitaxy, the resistance of a source-drain extension region of the MOS transistor is reduced, thereby reducing serial resistance of source-drain, advancing saturated current of the MOS transistor and simultaneously and effectively inhibiting the occurrence of short channel effect.

Description

MOS transistor manufacture method and structure

Technical field

The present invention relates to a kind of MOS transistor manufacture method, relate in particular to a kind of manufacture method that realizes having the MOS transistor of the resistance that hangs down SDE (source drain extension region, Source/Drain Extension).The invention still further relates to a kind of MOS transistor.

Background technology

In the prior art, when the channel dimensions of the MOS transistor that will realize during,, need to adopt heavy dose of LDD (Lightly Doped Drain, slight doped-drain) to inject usually in order to reduce the resistance of SDE less than 65 microns.Though yet heavy dose of LDD can reduce the resistance of SDE, because the junction depth of SDE is bigger, horizontal proliferation is serious, thereby can aggravate the generation of short-channel effect.

As shown in Figure 1, be the sectional structure chart of the MOS transistor made according to prior art, as can be seen from this figure, owing to adopted heavy dose of LDD to inject, therefore the overlapping region (overlap) between source-drain electrode and the grid is bigger, thereby has aggravated the generation of short-channel effect.

Summary of the invention

The technical problem to be solved in the present invention provides a kind of MOS transistor manufacture method, can reduce the resistance of MOS transistor source drain extension region, can suppress the generation of short-channel effect simultaneously again, and the present invention also provides a kind of MOS transistor for this reason.

For solving the problems of the technologies described above, the invention provides a kind of MOS transistor manufacture method, may further comprise the steps:

(1) form the grid pile layer on substrate, described grid pile layer comprises gate insulation layer and grid;

(2) use described grid as mask, carry out the LDD doping first time, form source region and drain region respectively in the both sides of grid pile layer at substrate surface;

(3) at the top in described source region and drain region selective growth silicon epitaxy layer, as source, the drain region of extension;

(4) use described grid as mask, carry out the LDD doping second time on source, the surface, drain region of described extension.

For this reason, the present invention also provides a kind of MOS transistor, comprising: substrate, grid pile layer, grid curb wall, source region, drain region, and wherein said grid pile layer is made up of gate insulator and grid, and described grid curb wall is arranged on the both sides of described grid pile layer; Described source region and drain region are formed on the described substrate, and are arranged in the both sides of described grid pile layer respectively; Described MOS transistor also comprises: the source region of extension and the drain region of extension, and the source region of described extension be arranged on described source region above, the drain region of described extension then be arranged on described drain region above; And the source region of described source region and extension is together as the source electrode of MOS transistor, and the drain region of described drain region and extension is together as the drain electrode of MOS transistor.

The present invention is owing to adopted technique scheme, has such beneficial effect, promptly by adopting the method for twice a LDD injection and a silicon epitaxy, reduced the resistance of MOS transistor source drain extension region, thereby reduced the series resistance that leak in the source, promote the saturation current of MOS transistor, also effectively suppressed the generation of short-channel effect simultaneously.

Description of drawings

The present invention is further detailed explanation below in conjunction with accompanying drawing and embodiment:

Fig. 1 is the sectional structure chart according to the MOS transistor of prior art manufacturing;

Fig. 2 is the schematic flow sheet of an embodiment of MOS transistor manufacture method of the present invention;

Fig. 3 a-3d makes the pilot process sectional structure chart of MOS transistor for adopting the described method of Fig. 2.

Embodiment

In one embodiment, as shown in Figure 2, the manufacture method of MOS transistor of the present invention may further comprise the steps:

(1) use known method, form the grid pile layer on substrate, described grid pile layer comprises gate insulation layer and grid.Generally speaking, described gate insulator is a silicon oxide layer, and described grid is a polysilicon gate.

(2) use grid as mask, carry out LDD doping first time at substrate surface, and the dosage of institute's impurity is about the magnitude of 1e13～1e14, energy is about 5～10kev, thereby has formed source region and drain region respectively in the both sides of grid pile layer.LDD mixed and was mainly used in the junction depth of control LDD this first time, thereby made that the overlapping region between source and drain areas and the grid is less, specifically can be referring to Fig. 3 a.

(3) at the top in described source region and drain region selective growth one deck silicon epitaxy layer, source, drain region as extension, the source region of described extension and source region are together as the source electrode of MOS transistor, then together as the drain electrode of MOS transistor, structure at this moment is shown in Fig. 3 b for the drain region of described extension and drain region.Wherein, the thickness of described epitaxial loayer should come fixed (technologygeneration) according to technical merit, and preferably, the thickness of described epitaxial loayer should be greater than the junction depth that the first time, LDD mixed, and less than the thickness of described grid.The effect of described epitaxial loayer of growing in the present invention has two: one, can reduce the series resistance that leak in the source; The 2nd, can reduce the junction depth that leak in the source, thereby effectively suppress short-channel effect.

(4) shown in Fig. 3 c, use grid as mask, carry out second time LDD on source, the surface, drain region of extension and mix, and the dosage of institute's impurity is about the magnitude of 1e15, energy is about 10～30kev, and this second time, the LDD doping was mainly used in the resistance of Controlling Source leakage.

Wherein, the impurity energy that above-mentioned first and second time LDD mixes and the concrete selection of dosage can require to decide according to type that will realize pipe and electrical characteristics.

(5) finish after for the second time LDD mixes, according to existing technology, at the two-layer formation grid curb wall of described grid pile layer, be used to guarantee grid and source electrode and drain between insulation.Then, shown in Fig. 3 d,, carry out the source and leak heavy doping again according to existing technology.

According to above-mentioned steps, then formed MOS transistor of the present invention, comprise the source region of substrate, grid pile layer, grid curb wall, source region, drain region, extension, the drain region of extension; Wherein, described grid pile layer comprises gate insulator and grid; Described grid curb wall is arranged on the both sides of described grid pile layer; Described source region and drain region are formed on the described substrate, and are arranged in the both sides of described grid pile layer respectively; The source region of described extension be arranged on described source region above, the drain region of described extension then be arranged on described drain region above.And the source region of described source region and extension is together as the source electrode of MOS transistor, and the drain region of described drain region and extension is together as the drain electrode of MOS transistor.

Claims

1, a kind of MOS transistor manufacture method is characterized in that, may further comprise the steps:

According to the described MOS transistor manufacture method of claim 1, it is characterized in that 2, when carrying out that described first time, LDD mixed, the dosage of institute's impurity is about the magnitude of 1e13～1e14, energy is about 5～10kev.

According to claim 1 or 2 described MOS transistor manufacture methods, it is characterized in that 3, when carrying out that described second time, LDD mixed, the dosage of institute's impurity is about the magnitude of 1e15, energy is about 10～30kev.

According to the described MOS transistor manufacture method of claim 1, it is characterized in that 4, the thickness of described epitaxial loayer is greater than the junction depth that described first time, LDD mixed, and less than the thickness of described grid.

5, a kind of MOS transistor comprises: substrate, grid pile layer, grid curb wall, source region, drain region, and wherein said grid pile layer is made up of gate insulator and grid, and described grid curb wall is arranged on the both sides of described grid pile layer; Described source region and drain region are formed on the described substrate, and are arranged in the both sides of described grid pile layer respectively; It is characterized in that described MOS transistor also comprises: the source region of extension and the drain region of extension, and the source region of described extension be arranged on described source region above, the drain region of described extension then be arranged on described drain region above; And the source region of described source region and extension is together as the source electrode of MOS transistor, and the drain region of described drain region and extension is together as the drain electrode of MOS transistor.