CN114497172A - Dual reduced surface electric field RFLDMOS device for RF amplification - Google Patents

Dual reduced surface electric field RFLDMOS device for RF amplification Download PDF

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CN114497172A
CN114497172A CN202011259285.2A CN202011259285A CN114497172A CN 114497172 A CN114497172 A CN 114497172A CN 202011259285 A CN202011259285 A CN 202011259285A CN 114497172 A CN114497172 A CN 114497172A
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region
type
channel
source
drift
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岳丹诚
彭虎
莫海锋
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Suzhou Huatai Electronics Co Ltd
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Suzhou Huatai Electronics Co Ltd
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7816—Lateral DMOS transistors, i.e. LDMOS transistors
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/0619—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions for preventing surface leakage or controlling electric field concentration for increasing or controlling the breakdown voltage of reverse biased devices by the doping profile or the shape or the arrangement of the PN junction, or with supplementary regions, e.g. junction termination extension [JTE] with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
    • H01L29/0623—Buried supplementary region, e.g. buried guard ring
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
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    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/402—Field plates

Abstract

The invention discloses a double-reduction surface electric field RFLDMOS device for radio frequency amplification, which comprises a substrate and an epitaxial layer, wherein a channel region, a drift region, a well region and a buried layer region are distributed in the epitaxial layer, a drain region is formed in the drift region, an active region and a doped region are formed in the well region, the channel region is also electrically connected with the source region and the drift region respectively, and the source region is also electrically contacted with or combined with the doped region; the source electrode and the drain electrode are respectively electrically connected with the source region and the drain region, the source electrode is also electrically connected with the substrate, and at least part of the drift region is positioned between the field plate and the buried layer region; the substrate, the epitaxial layer, the well region, the buried layer region and the doped region are all of a first doping type, and the channel region, the drift region, the source region and the drain region are all of a second doping type. According to the invention, the buried layer region and the top field plate form a double reduction surface electric field for the electric field of the drift region, so that BV of the device can be improved.

Description

Dual reduced surface electric field RFLDMOS device for RF amplification
Technical Field
The invention relates to an RFLDMOS device, in particular to a RFLDMOS device for double reduction of a surface electric field for radio frequency amplification, and belongs to the technical field of semiconductors.
Background
The RF LDMOS is an N-type MOSFET device designed for a radio frequency power amplifier, and is provided with a transverse channel structure, a drain electrode, a source electrode and a grid electrode are all arranged on the surface of the device, the source electrode is generally connected with the bottom of a substrate through a channel with high impurity concentration in a body and is grounded, a low-concentration N-type drift region is arranged between the channel and the drain electrode, the LDMOS adopts a double diffusion technology, boron and phosphorus are sequentially diffused twice in the same photoetching window, and the length of the channel can be accurately determined by the difference of the transverse junction depths of the two impurity diffusions.
Fig. 1 is a RFLDMOS device structure provided by the present invention, wherein 11 is a P-type heavily doped substrate, 12 is a P-type epitaxial layer, 21 is an N-type drift region, 22 is an N-type heavily doped source region, 23 is an N-type heavily doped drain region, 25' is a P-type well region, 26 is a P-type heavily doped region, 31 is a gate oxide layer, 32 is a polysilicon gate, 33 is a metal silicide for connecting a source region and a source metal electrode, 34 is a sidewall of the gate, 35 is a field plate, 41 is a conductive channel (e.g., a tungsten plug via) connecting the source and the substrate, 42 is a first contact hole metal, 43 is a second contact hole metal, 51 is an insulating dielectric layer, 61 is the source, and 62 is the drain.
The RFLDMOS device in FIG. 1 adopts a P-type channel, the surface of the channel is inverted by applying a positive voltage to a grid electrode to form a conductive channel, the surface channel close to a grid oxide layer is strongly inverted, and the highest current density is formed in the channel; however, since the current is concentrated on the surface of the channel, the following disadvantages are brought about: firstly, due to the existence of the surface scattering effect, the mobility of a channel is reduced, so that the saturation current of the channel is reduced, and meanwhile, the surface scattering causes larger noise to influence the linearity of a device; second, strong surface current density can cause channel Hot Carrier Injection (HCI); thirdly, the strong surface inversion causes the Cgd to be larger when the device is turned on, and the radio frequency performance of the device is influenced.
Disclosure of Invention
The invention mainly aims to provide a double-reduction surface electric field RFLDMOS device for radio frequency amplification, so as to overcome the defects in the prior art.
In order to achieve the purpose, the technical scheme adopted by the invention comprises the following steps:
the embodiment of the invention provides a double-reduction surface electric field RFLDMOS device for radio frequency amplification, which comprises a substrate and an epitaxial layer which are sequentially stacked along a specified direction, wherein a channel region, a drift region, a well region and a buried layer region are distributed in the epitaxial layer, a drain region is formed in the drift region, an active region and a doped region are formed in the well region, the channel region is also respectively in electrical contact with or in electrical combination with the source region and the drift region, and the source region is also in electrical contact with or in electrical combination with the doped region; and the number of the first and second groups,
the source electrode and the drain electrode are respectively electrically connected with the source region and the drain region, the source electrode is also electrically connected with the substrate, the gate electrode and the field plate are positioned above the epitaxial layer, the gate electrode at least covers a part of the channel region and extends to the upper part of the drift region, and at least a part of the drift region is positioned between the field plate and the buried layer region;
the substrate, the epitaxial layer, the well region, the buried layer region and the doped region are all of a first doping type, and the channel region, the drift region, the source region and the drain region are all of a second doping type.
In some more specific embodiments, the dual reduced surface electric field RFLDMOS device for radio frequency amplification comprises a P-type heavily doped substrate, a P-type epitaxial layer, and a source electrode, a drain electrode, a gate electrode and a field plate which are arranged in sequence along a designated direction, wherein the gate electrode and the field plate are arranged above the P-type epitaxial layer,
an N-type drift region, an N-type channel region, a P-type well region and a P-type buried layer region are distributed in the P-type epitaxial layer, the P-type buried layer region extends from the lower edge of the P-type well region to the lower portions of the N-type channel region and the N-type drift region, at least a partial region of the N-type drift region is located between the P-type buried layer and the field plate, the P-type buried layer region and the P-type well region are adjacent to each other in the longitudinal direction of the device, and gaps are reserved between the P-type buried layer region and the N-type channel region as well as between the P-type buried layer region and the N-type drift region in the longitudinal direction of the device;
an N-type heavily doped source region and a P-type heavily doped region are formed in the P-type well region, an N-type heavily doped drain region is formed in the N-type drift region, the N-type heavily doped source region is electrically contacted or electrically combined with the P-type heavily doped region, and the N-type channel region is positioned between the P-type well region and the N-type drift region and is respectively adjacent to the P-type well region and the N-type drift region in the transverse direction of the device;
the grid electrode extends from the upper part of the N-type channel region to the upper part of the N-type drift region; the source electrode and the drain electrode are electrically connected with the N-type heavily doped source region and the N-type heavily doped drain region through first contact hole metal and second contact hole metal respectively, and the source electrode is also electrically connected with the P-type heavily doped substrate through a conductive channel.
Compared with the prior art, the invention has the advantages that:
1) according to the RFLDMOS device for radio frequency amplification and double surface electric field reduction, an N-type doped channel is adopted to form a depletion type NLDMOS device which is applied to radio frequency power amplification RF LDMOS, a channel is transferred from the surface of a silicon substrate (namely an epitaxial layer) to a body to form a buried channel, and because a surface state does not exist in a chip (the surface state exists at an interface as the name suggests, the charge transfer can be scattered by the interface charge), the channel electron scattering noise can be reduced, and the channel electron mobility can be greatly improved;
2) the invention adopts the technology of dual surface electric field reduction, adjusts the electric field of the drift region and the electric fields on the upper surface and the lower surface of the drift region through the buried layer region and the top field plate so as to level the surface electric field, and can improve the breakdown voltage of the device under the condition of not influencing the performance of the device, thereby further improving the performance of the device;
3) according to the RFLDMOS device for radio frequency amplification and double surface electric field reduction, a channel is transferred from the surface to the inside of a body to form a buried channel, so that the effective electron mobility of the channel is improved by more than 30%, the hot carrier injection effect of the channel is effectively inhibited, and the current density of the device can be improved by more than 30% under the same HCI service life;
4) the RFLDMOS device for radio frequency amplification provided by the embodiment of the invention can reduce the on-resistance by 20% under the condition of keeping BV (breakdown voltage), and the current density is improved by more than 50%.
Drawings
Fig. 1 is a schematic cross-sectional view of a conventional RFLDMOS device;
fig. 2 is a dual resurf RFLDMOS device for rf amplification provided in an exemplary embodiment of the invention;
description of reference numerals: the transistor comprises an 11-P type heavily doped substrate, a 12-P type epitaxial layer, a 21-N type drift region, a 22-N type heavily doped source region, a 23-N type heavily doped drain region, a 25, 25' -P type well region, a 26-P type heavily doped region, a 31-gate oxide layer, a 32-polysilicon gate, a 33-metal silicide layer, a 34-side wall of a gate, a 35-field plate, a 41-conductive channel, a 42-first contact hole metal, a 43-second contact hole metal, a 51-insulating dielectric layer, a 61-source electrode and a 62-drain electrode.
Detailed Description
In view of the deficiencies in the prior art, the inventors of the present invention have made extensive studies and extensive practices to provide technical solutions of the present invention. The technical solution, its implementation and principles, etc. will be further explained as follows.
Radio Frequency (RF) Laterally Diffused Metal Oxide Semiconductor (LDMOS) power transistors have very good power capability, gain, linearity, efficiency and reliability and are key components of RF Power Amplifiers (PAs) in base stations for communication systems (GSM, EDGE, W-CDMA), mobile communication terminals, radar, radio frequency heating and lighting fields, etc.
The embodiment of the invention provides a double-reduction surface electric field RFLDMOS device for radio frequency amplification, which comprises a substrate and an epitaxial layer which are sequentially stacked along a specified direction, wherein a channel region, a drift region, a well region and a buried layer region are distributed in the epitaxial layer, a drain region is formed in the drift region, an active region and a doped region are formed in the well region, the channel region is also respectively in electrical contact with or in electrical combination with the source region and the drift region, and the source region is also in electrical contact with or in electrical combination with the doped region; and the number of the first and second groups,
the source electrode and the drain electrode are respectively electrically connected with the source region and the drain region, the source electrode is also electrically connected with the substrate, the gate electrode and the field plate are positioned above the epitaxial layer, the gate electrode at least covers a part of the channel region and extends to the upper part of the drift region, and at least a part of the drift region is positioned between the field plate and the buried layer region;
the substrate, the epitaxial layer, the well region, the buried layer region and the doped region are all of a first doping type, and the channel region, the drift region, the source region and the drain region are all of a second doping type.
Further, the first doping type is P-type, and the second doping type is N-type.
Furthermore, the top surfaces of the well region, the drift region and the channel region are flush with the top surface of the epitaxial layer, the channel region is located between the source region and the drift region, and the channel region is adjacent to the source region and the drift region in the transverse direction of the device.
Further, the thickness of the well region in the longitudinal direction of the device is larger than that of the drift region.
Furthermore, in the longitudinal direction of the device, the thickness of the well region is 0.5-5 μm, the thickness of the drift region is 0.05-5 μm, the thickness of the channel region is 0.01-1 μm, and the thickness of the epitaxial layer is 1-10 μm.
Furthermore, the top surfaces of the source region and the doped region are flush with the top surface of the well region.
Further, the thickness of the doped region in the longitudinal direction of the device is larger than that of the source region.
Further, in the longitudinal direction of the device, the thickness of the doped region is 0.01-2 μm, the thickness of the source region is 0.01um-1um, and the thickness of the well region is 0.05um-5 um.
Further, the top surface of the drain region is flush with the top surface of the drift region.
Further, the thickness of the drain region is 0.01um-1 um.
Furthermore, the well region, the drift region, the channel region and the buried layer region are formed by processing the selected region of the epitaxial layer through an ion implantation process.
Furthermore, the doped region and the source region are formed by processing selected regions of the well region through an ion implantation process.
Further, the drain region is formed by processing a selected region of the drift region through an ion implantation process.
Furthermore, the buried layer region extends from the lower edge of the well region to the lower part of the channel region and the drift region, the buried layer region is adjacent to the well region in the longitudinal direction of the device, and gaps are formed among the buried layer region, the channel region and the drift region in the longitudinal direction of the device.
Further, the length of the buried layer region in the transverse direction of the device is 0.5-10 μm.
Further, the length of the channel region in the transverse direction of the device is 0.1-1 μm.
Further, the length of the drift region in the transverse direction of the device is 0.1-10 μm.
Further, a gate oxide layer is arranged between the grid and the epitaxial layer.
Furthermore, the gate oxide layer comprises silicon dioxide.
Furthermore, an insulating medium layer is further arranged on the epitaxial layer in a laminated mode, the source electrode and the drain electrode are arranged above the insulating medium layer, and the grid electrode and the field plate are arranged inside the insulating medium layer.
Further, the source electrode is electrically connected with the source region through a first contact hole metal, the source electrode is also electrically connected with the substrate through a conductive channel, the drain electrode is electrically connected with the drain region through a second contact hole metal, and the conductive channel penetrates through the epitaxial layer and enters the substrate.
Further, the conductive channel comprises any one of a heavily doped P-type or N-type deep well, a metal through hole and a silicon chip channel.
Furthermore, a metal silicide layer is arranged between the first contact hole metal and the source region.
In some more specific embodiments, the dual reduced surface electric field RFLDMOS device for radio frequency amplification comprises a P-type heavily doped substrate, a P-type epitaxial layer, and a source electrode, a drain electrode, a gate electrode and a field plate which are arranged in sequence along a designated direction, wherein the gate electrode and the field plate are arranged above the P-type epitaxial layer,
an N-type drift region, an N-type channel region, a P-type well region and a P-type buried layer region are distributed in the P-type epitaxial layer, the P-type buried layer region extends from the lower edge of the P-type well region to the lower portions of the N-type channel region and the N-type drift region, at least a partial region of the N-type drift region is located between the P-type buried layer and the field plate, the P-type buried layer region and the P-type well region are adjacent to each other in the longitudinal direction of the device, and gaps are reserved between the P-type buried layer region and the N-type channel region as well as between the P-type buried layer region and the N-type drift region in the longitudinal direction of the device;
an N-type heavily doped source region and a P-type heavily doped region are formed in the P-type well region, an N-type heavily doped drain region is formed in the N-type drift region, the N-type heavily doped source region is electrically contacted or electrically combined with the P-type heavily doped region, and the N-type channel region is positioned between the P-type well region and the N-type drift region and is respectively adjacent to the P-type well region and the N-type drift region in the transverse direction of the device;
the grid electrode extends from the upper part of the N-type channel region to the upper part of the N-type drift region; the source electrode and the drain electrode are electrically connected with the N-type heavily doped source region and the N-type heavily doped drain region through first contact hole metal and second contact hole metal respectively, and the source electrode is also electrically connected with the P-type heavily doped substrate through a conductive channel.
The technical solution, the implementation process and the principle thereof will be further explained with reference to the drawings.
Referring to fig. 2, a dual-reduction surface electric field RFLDMOS device for radio frequency amplification includes a P-type heavily doped substrate 11, a P-type epitaxial layer 12, a gate oxide layer 31, an insulating dielectric layer 51, a source electrode 61 and a drain electrode 62 disposed on top of the insulating dielectric layer 51, a polysilicon gate electrode 32 and a field plate 35 disposed inside the insulating dielectric layer 51;
an N-type drift region 21, an N-type channel region 24, a P-type well region 25 and a P-type buried layer region 27 are distributed in the P-type epitaxial layer 12,
the P-type buried layer region 27 extends from the lower edge of the P-type well region 25 to the lower edge of the N-type channel region 24 and the N-type drift region 21, at least a partial region of the N-type drift region 21 is located between the P-type buried layer 27 and the field plate 35, the P-type buried layer region 27 can be adjacent to and electrically connected with the P-type well region 25 in the longitudinal direction of the device, and gaps are formed between the P-type buried layer region 27 and the N-type channel region 24 as well as between the P-type buried layer region 27 and the N-type drift region 21 in the longitudinal direction of the device;
an N-type heavily doped source region 22 and a P-type heavily doped region 26 are formed in the P-type well region 25, an N-type heavily doped drain region 23 is formed in the N-type drift region 21, the N-type heavily doped source region 22 is electrically contacted with or electrically combined with the P-type heavily doped region 26, the N-type channel region 24 is positioned between the N-type heavily doped source region 22 and the N-type drift region 21, and the N-type channel region 24 is respectively adjacent to the N-type heavily doped source region 22 and the N-type drift region 21 in the transverse direction of the device;
the polysilicon gate 32 extends from above the N-type channel region 24 to above the N-type drift region 21, wherein the polysilicon gate 32 has a sidewall 34; the source 61 and the drain 62 are electrically connected to the heavily doped N-type source region 22 and the heavily doped N-type drain region 23 through the first contact hole metal 42 and the second contact hole metal 43, respectively, and the source 61 is further electrically connected to the heavily doped P-type substrate 11 through the conductive via (e.g., tungsten plug via) 41.
Specifically, the top surfaces of the P-type well region 25, the N-type drift region 21 and the N-type channel region 24 are flush with the top surface of the P-type epitaxial layer 12, the N-type channel region 24 is located between the N-type heavily doped source region 22 and the N-type drift region 21, the N-type channel region 24 is adjacent to the N-type heavily doped source region 22 and the N-type drift region 21 in the transverse direction of the device, and the thickness of the P-type well region 25 in the longitudinal direction of the device is greater than that of the N-type drift region 21.
Specifically, in the longitudinal direction of the device, the thickness of the P-type well region 25 is 0.5-5 μm, the thickness of the N-type drift region 21 is 0.05-5 μm, the thickness of the N-type channel region 24 is 0.01-1 μm, and the thickness of the P-type epitaxial layer 12 is 1um-10 um.
Specifically, the top surfaces of the N-type heavily doped source region 22 and the P-type heavily doped region 26 are level with the top surface of the P-type well region 25, the thickness of the P-type heavily doped region 26 in the longitudinal direction of the device is greater than that of the N-type heavily doped source region 22, the thickness of the P-type heavily doped region 26 is 0.01-2 μm, the thickness of the N-type heavily doped source region 22 is 0.01-1 um, and the thickness of the P-type well region 25 is 0.05-5 um.
Specifically, the top surface of the N-type heavily doped drain region 23 is flush with the top surface of the N-type drift region 21, and the depth of the N-type heavily doped drain region 23 in the N-type drift region 21 is 0.01um to 1 um.
Specifically, the P-type well region 25, the N-type drift region 21, the N-type channel region 24, and the P-type buried layer region 27 are formed by processing a selected region of the P-type epitaxial layer 12 through an ion implantation process, the P-type heavily doped region 26 and the N-type heavily doped source region 22 are formed by processing a selected region of the P-type well region 25 through an ion implantation process, and the N-type heavily doped drain region 23 is formed by processing a selected region of the N-type drift region 21 through an ion implantation process.
Specifically, the length of the P-type buried layer region 27 in the lateral direction of the device is 0.5-10 μm, the length of the N-type channel region 24 in the lateral direction of the device is 0.1-1 μm, and the length of the N-type drift region 21 in the lateral direction of the device is 0.1-10 μm.
Specifically, the gate oxide layer 31 is made of silicon dioxide, and the P-type heavily doped substrate 11 is made of a silicon substrate.
According to the RFLDMOS device for radio frequency amplification and double reduction of the surface electric field, the depletion type NLDMOS device is formed by adopting the N-type doped channel and is applied to the radio frequency power amplification RF LDMOS, the channel is transferred from the surface of the epitaxial layer to the body to form the buried channel, so that the electron mobility of the channel can be greatly improved, the electron scattering noise of the channel is reduced, the hot carrier injection effect is inhibited, the Cgs (gate source capacitance) and the Cgd (gate drain capacitance) are reduced, and the radio frequency power, the efficiency and the linearity of the device are greatly improved; in addition, after the hot carrier injection is restrained, BV (breakdown voltage) becomes the main limitation of further improving the power, the invention adopts a double surface electric field reduction technology (double RESURF is the meaning of the surface electric field reduction technology, a double surface field plate is one technology of reducing the surface electric field, and the other part is reduced to the bottom electric field because the 27P type well region is reduced, the upper surface and the lower surface of the drift region can be considered), and the BV of the device can be improved under the condition of not influencing the performance of the device by forming the double surface electric field through the buried layer region, the top layer field plate and the electric field of the drift region, so the performance of the chip can be further improved.
Specifically, the top field plate is grounded to form a potential zero point, so that the surface electric field distribution is changed; the buried layer region is connected with the source region, and the electric potential is equal to the electric potential of the source region and is grounded, so that a double surface electric field reduction is formed.
According to the RFLDMOS device for radio frequency amplification and double surface electric field reduction, a channel is transferred from the surface to the inside of a body to form a buried channel, so that the effective electron mobility of the channel is improved by more than 30%, the hot carrier injection effect of the channel is effectively inhibited, and the current density of the device can be improved by more than 30% under the same HCI service life; in addition, the double-reduction surface electric field RFLDMOS device for radio frequency amplification provided by the embodiment of the invention can reduce 20% Rdson (on-resistance) under the condition of keeping BV, and the current density is improved by more than 50%.
It should be understood that the above-mentioned embodiments are merely illustrative of the technical concepts and features of the present invention, which are intended to enable those skilled in the art to understand the contents of the present invention and implement the present invention, and therefore, the protection scope of the present invention is not limited thereby. All equivalent changes and modifications made according to the spirit of the present invention should be covered within the protection scope of the present invention.

Claims (10)

1. A dual-reduction surface electric field RFLDMOS device for radio frequency amplification is characterized by comprising a substrate and an epitaxial layer which are sequentially stacked along a specified direction, wherein a channel region, a drift region, a well region and a buried layer region are distributed in the epitaxial layer, a drain region is formed in the drift region, an active region and a doped region are formed in the well region, the channel region is also respectively in electrical contact with or electrically combined with the source region and the drift region, and the source region is also in electrical contact with or electrically combined with the doped region; and the number of the first and second groups,
the source electrode and the drain electrode are respectively electrically connected with the source region and the drain region, the source electrode is also electrically connected with the substrate, the gate electrode and the field plate are positioned above the epitaxial layer, the gate electrode at least covers a part of the channel region and extends to the upper part of the drift region, and at least a part of the drift region is positioned between the field plate and the buried layer region;
the substrate, the epitaxial layer, the well region, the buried layer region and the doped region are all of a first doping type, and the channel region, the drift region, the source region and the drain region are all of a second doping type.
2. The dual reduced surface electric field RFLDMOS device for radio frequency amplification of claim 1, wherein: the first doping type is P type, and the second doping type is N type.
3. The dual resurf RFLDMOS device for radio frequency amplification of claim 1, wherein: the top surfaces of the well region, the drift region and the channel region are parallel to the top surface of the epitaxial layer, the channel region is positioned between the source region and the drift region, and the channel region is respectively adjacent to the source region and the drift region in the transverse direction of the device;
preferably, the thickness of the well region in the longitudinal direction of the device is greater than that of the drift region;
preferably, in the longitudinal direction of the device, the thickness of the well region is 0.5-5 μm, the thickness of the drift region is 0.05-5 μm, the thickness of the channel region is 0.01-1 μm, and the thickness of the epitaxial layer is 1-10 μm.
4. The dual resurf RFLDMOS device for radio frequency amplification of claim 3, wherein: the top surfaces of the source region and the doped region are level to the top surface of the well region;
preferably, the thickness of the doped region in the longitudinal direction of the device is greater than that of the source region;
preferably, in the longitudinal direction of the device, the thickness of the doped region is 0.01-2 μm, the thickness of the source region is 0.01um-1um, and the thickness of the well region is 0.05um-5 um.
5. The dual reduced surface electric field RFLDMOS device for RF amplification of claim 3, wherein: the top surface of the drain region is flush with the top surface of the drift region; preferably, the thickness of the drain region is 0.01um to 1 um.
6. The dual reduced surface electric field RFLDMOS device for RF amplification of claim 3, wherein: the well region, the drift region, the channel region and the buried layer region are formed by processing a selected region of the epitaxial layer through an ion implantation process;
preferably, the doped region and the source region are formed by processing a selected region of the well region through an ion implantation process; preferably, the drain region is formed by processing a selected region of the drift region through an ion implantation process.
7. The dual reduced surface electric field RFLDMOS device for radio frequency amplification of claim 1, wherein: the buried layer region extends from the lower edge of the well region to the lower edge of the channel region and the drift region, the buried layer region is adjacent to the well region in the longitudinal direction of the device, and gaps are reserved between the buried layer region and the channel region as well as between the buried layer region and the drift region in the longitudinal direction of the device;
preferably, the length of the buried layer region in the transverse direction of the device is 0.5-10 μm;
preferably, the length of the channel region in the transverse direction of the device is 0.1-1 μm;
preferably, the length of the drift region in the lateral direction of the device is 0.1-10 μm.
8. The dual reduced surface electric field RFLDMOS device for radio frequency amplification of claim 1, wherein: a gate oxide layer is also arranged between the grid and the epitaxial layer; preferably, the material of the gate oxide layer comprises silicon dioxide.
9. The dual reduced surface electric field RFLDMOS device for radio frequency amplification of claim 1, wherein: an insulating medium layer is further arranged on the epitaxial layer in a laminated mode, the source electrode and the drain electrode are arranged above the insulating medium layer, and the grid electrode and the field plate are arranged inside the insulating medium layer;
and/or the source electrode is electrically connected with the source region through the first contact hole metal, the source electrode is also electrically connected with the substrate through a conductive channel, and the drain electrode is electrically connected with the drain region through the second contact hole metal, wherein the conductive channel penetrates through the epitaxial layer and enters the substrate;
preferably, the conductive channel comprises any one of a heavily doped P-type or N-type deep well, a metal through hole and a silicon chip channel; preferably, a metal silicide layer is further disposed between the first contact hole metal and the source region.
10. The dual resurf RFLDMOS device for radio frequency amplification of claim 1, comprising a heavily P-doped substrate, a P-type epitaxial layer, and a source, a drain, a gate and a field plate disposed in sequence along a designated direction, said gate and field plate being disposed above said P-type epitaxial layer,
an N-type drift region, an N-type channel region, a P-type well region and a P-type buried layer region are distributed in the P-type epitaxial layer, the P-type buried layer region extends from the lower edge of the P-type well region to the lower portions of the N-type channel region and the N-type drift region, at least a local region of the N-type drift region is located between the P-type buried layer and a field plate, the P-type buried layer region is adjacent to the P-type well region in the longitudinal direction of the device, and gaps are reserved among the P-type buried layer region, the N-type channel region and the N-type drift region in the longitudinal direction of the device;
an N-type heavily doped source region and a P-type heavily doped region are formed in the P-type well region, an N-type heavily doped drain region is formed in the N-type drift region, the N-type heavily doped source region is also electrically contacted or electrically combined with the P-type heavily doped region, and the N-type channel region is positioned between the N-type heavily doped source region and the N-type drift region and is respectively adjacent to the N-type heavily doped source region and the N-type drift region in the transverse direction of the device;
the grid electrode extends from the upper part of the N-type channel region to the upper part of the N-type drift region; the source electrode and the drain electrode are electrically connected with the N-type heavily doped source region and the N-type heavily doped drain region through first contact hole metal and second contact hole metal respectively, and the source electrode is also electrically connected with the P-type heavily doped substrate through a conductive channel.
CN202011259285.2A 2020-11-12 2020-11-12 Dual reduced surface electric field RFLDMOS device for RF amplification Pending CN114497172A (en)

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Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1524296A (en) * 2001-03-09 2004-08-25 �����ɷ� Rf power LDMOS transistor
CN101183648A (en) * 2006-11-13 2008-05-21 上海华虹Nec电子有限公司 High voltage PMOS transistor and method of manufacture thereof
CN102074578A (en) * 2009-11-05 2011-05-25 夏普株式会社 Semiconductor device and method for producing the same
CN103855210A (en) * 2012-12-03 2014-06-11 上海华虹宏力半导体制造有限公司 Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1524296A (en) * 2001-03-09 2004-08-25 �����ɷ� Rf power LDMOS transistor
CN101183648A (en) * 2006-11-13 2008-05-21 上海华虹Nec电子有限公司 High voltage PMOS transistor and method of manufacture thereof
CN102074578A (en) * 2009-11-05 2011-05-25 夏普株式会社 Semiconductor device and method for producing the same
CN103855210A (en) * 2012-12-03 2014-06-11 上海华虹宏力半导体制造有限公司 Radio frequency transverse double-diffusion field effect transistor and manufacturing method thereof

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