CN101989540B - Method for doping polycrystalline silicon layer - Google Patents
Method for doping polycrystalline silicon layer Download PDFInfo
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- CN101989540B CN101989540B CN2009100559397A CN200910055939A CN101989540B CN 101989540 B CN101989540 B CN 101989540B CN 2009100559397 A CN2009100559397 A CN 2009100559397A CN 200910055939 A CN200910055939 A CN 200910055939A CN 101989540 B CN101989540 B CN 101989540B
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Abstract
The invention discloses a method for doping a polycrystalline silicon layer. The method comprises the following steps of: forming an N trap, an isolation region and a P trap on a substrate and depositing a gate oxide and the polycrystalline silicon layer on the surface of the substrate; doping the polycrystalline silicon layer above the P trap and the N trap by an ion injection process, wherein a doped ion is a P type element; and applying a mask to the polycrystalline silicon layer above the N trap and doping the polycrystalline silicon layer above the P trap by the ion injection process, wherein the doped ion is an N type element and the dosage of the N type element is more than that of the doped P type element. Due to the adoption of the method, a process flow for doping the polycrystalline silicon layer can be simplified.
Description
Technical field
The present invention relates to field of semiconductor manufacture, the method that particularly a kind of polysilicon layer mixes.
Background technology
Along with the extensive use of electronic equipment, semi-conductive manufacturing process has obtained development at full speed, in semi-conductive manufacturing process, relates to the method that polysilicon layer mixes.Fig. 1~Fig. 3 is the process sectional structure chart of the method that polysilicon layer mixes in the prior art, and the doping method of this polysilicon layer is to two well structures, after forming N trap and P trap on the substrate; Polysilicon layer doping P type element to N trap top; Be used to form the P transistor npn npn, the polysilicon layer doped N-type element to P trap top is used to form the N transistor npn npn; Like Fig. 1~shown in Figure 3, this method may further comprise the steps:
Step 2 referring to Fig. 2, applies mask 107 on the polysilicon layer above the P trap 106, and adopts ion implantation technology that the polysilicon layer 106 above the N trap is mixed, and the ion that is mixed is a P type element, and for example boron or indium are used for follow-up formation P transistor npn npn.
Step 3; Referring to Fig. 3, remove the mask 107 that on the polysilicon layer above the P trap 106, is applied, and on the polysilicon layer above the N trap 106, apply mask 108; Adopt ion implantation technology that the polysilicon layer 106 above the P trap is mixed; The ion that is mixed is a N type element, and for example phosphorus or arsenic are used for follow-up formation N transistor npn npn.
In above-mentioned steps; When the polysilicon layer to N trap top mixes; Need on the polysilicon layer above the P trap, apply mask 107; And when the polysilicon layer of P trap top mixed, need to remove the mask 107 that is applied on the polysilicon layer of P trap top, and on the polysilicon layer above the N trap, apply mask 108.This shows that this method relates to the process that applies the process of mask and once remove mask twice, the technological process more complicated that this just makes the polysilicon layer doping.
Summary of the invention
In view of this, the method that the object of the present invention is to provide a kind of polysilicon layer to mix can be simplified the technological process that polysilicon layer mixes.
For achieving the above object, technical scheme of the present invention specifically is achieved in that
The method that a kind of polysilicon layer mixes; On substrate, form N trap, isolated area and P trap; And behind substrate surface deposition gate oxide and polysilicon layer; This method comprises: adopt ion implantation technology that the polysilicon layer above P trap top and the N trap is mixed, and the ionic type that is mixed is a P type element; On the polysilicon layer above the N trap, applies mask, and adopt ion implantation technology that the polysilicon layer of P trap top is mixed, and the ionic type that is mixed is N type element that the dosage of N type element is greater than the dosage of institute's doped P-type element.
The dosage of said P type element is 1 * 10
15Individual/cm
2To 3 * 10
15Individual/cm
2
Said P type element is boron or indium
The dosage of said N type element is 3 * 10
15Individual/cm
2To 5 * 10
15Individual/cm
2
Said N type element is phosphorus or arsenic.
Visible by above-mentioned technical scheme; On substrate, form N trap, isolated area and P trap, and behind substrate surface deposition gate oxide and polysilicon layer, adopt ion implantation technology that the polysilicon layer above P trap top and the N trap is mixed; And the ionic type that is mixed is a P type element; On the polysilicon layer above the N trap, apply mask then, and adopt ion implantation technology that the polysilicon layer above the P trap is mixed, and the ionic type that is mixed is a N type element; The dosage of N type element is greater than the dosage of institute's doped P-type element; Therefore, the method that polysilicon layer provided by the present invention mixes only relates to the process that once applies mask, has simplified the technological process that polysilicon layer mixes.
Description of drawings
Fig. 1~Fig. 3 is the process sectional structure chart of the method that polysilicon layer mixes in the prior art.
Fig. 4 is the flow chart of the method for polysilicon layer doping provided by the present invention.
Fig. 5 is the process sectional structure chart of step 401 in the polysilicon layer provided by the present invention method of mixing.
Fig. 6 is the process sectional structure chart of step 402 in the polysilicon layer provided by the present invention method of mixing.
Fig. 7 is the process sectional structure chart of step 403 in the polysilicon layer provided by the present invention method of mixing.
Embodiment
For making the object of the invention, technical scheme and advantage clearer, below with reference to the accompanying drawing embodiment that develops simultaneously, to further explain of the present invention.
Core concept of the present invention is: at first adopt ion implantation technology that the polysilicon layer above P trap top and the N trap is mixed; And the ionic type that is mixed is a P type element; On the polysilicon layer above the N trap, apply mask then; And adopt ion implantation technology that the polysilicon layer of P trap top is mixed, and the ionic type that is mixed is N type element, the dosage of N type element is greater than the dosage of institute's doped P-type element; This method only relates to the process that once applies mask, has simplified the technological process that polysilicon layer mixes.
Fig. 4 is the flow chart of the method for polysilicon layer doping provided by the present invention, and as shown in Figure 4, this method may further comprise the steps:
This step can adopt the method for prior art, does not repeat them here.
Need to prove, when the ion that is mixed is P type element, be example with boron; The boron atom in replacing the mother crystal structure atom and when constituting covalent bond, will form a hole because of lacking a valence electron, so the hole number in the semiconductor rolls up; The hole becomes charge carrier, when the ion that is mixed is N type element, is example with phosphorus; Phosphorus atoms in replacing the mother crystal structure atom and when constituting covalent bond, the 5th unnecessary valence electron is easy to break away from the constraint of phosphorus atoms nuclear and becomes free electron, so the free electron number in the semiconductor rolls up; Free electron becomes charge carrier, therefore, and in step 402; After to whole polysilicon layer doping P type element, the hole becomes charge carrier, in step 403; Only to the polysilicon layer doped N-type element of N trap top, along with the doping of N type element, the quantity of free electron increases gradually in the polysilicon layer; And with the hole neutralization takes place and make the decreased number in hole, when the dosage of N type element during greater than the dosage of institute's doped P-type element in the step 402, free electron becomes charge carrier.
The concrete dosage of the N type element that is mixed in the concrete dosage of institute's doped P-type element and the step 403 in the step 402 is decided according to actual conditions, when need in the polysilicon layer above the P trap, dopant dose being the P type element of Q1, and need dopant dose is the N type element of Q2 in the polysilicon layer above the N trap time; Theoretically, the dosage of institute's doped P-type element is Q1 in the step 402, and the dosage of the N type element that is mixed in the step 403 is Q1+Q2; But; Because N type element and P type element have different characteristic, therefore N type element doping extremely has been doped with the polysilicon layer of P type element after, be accompanied by the neutralization in free electron and hole; Other chemistry or physical reactions also possibly take place; Therefore, strictly, the dosage and the Q1+Q2 of the N type element that is mixed in the step 403 have certain error; In practical application, the dosage of institute's doped P-type element is generally 1 * 10 in the step 402
15Individual/cm
2To 3 * 10
15Individual/cm
2, the dosage of the N type element that is mixed in the step 403 is generally 3 * 10
15Individual/cm
2To 5 * 10
15Individual/cm
2
So far, this flow process finishes, and can get into follow-up technological process.
It is thus clear that; At first adopt ion implantation technology that P trap top and polysilicon layer above the N trap are mixed, and the ionic type that is mixed is P type element, on the polysilicon layer above the N trap, applies mask then; And adopt ion implantation technology that the polysilicon layer above the P trap is mixed; And the ionic type that is mixed is a N type element, and the dosage of N type element this shows greater than the dosage of institute's doped P-type element; This method only relates to the process that once applies mask, and this has just simplified the technological process that polysilicon layer mixes.
The above is merely preferred embodiment of the present invention, is not to be used to limit protection scope of the present invention.All within spirit of the present invention and principle, any modification of being done, be equal to replacement and improvement etc., all should be included within protection scope of the present invention.
Claims (5)
1. the polysilicon layer method of mixing; On substrate, form N trap, isolated area and P trap; And behind substrate surface deposition gate oxide and polysilicon layer; This method comprises: adopt ion implantation technology that the polysilicon layer above P trap top and the N trap is mixed, and the ionic type that is mixed is a P type element; On the polysilicon layer above the N trap, applies mask, and adopt ion implantation technology that the polysilicon layer of P trap top is mixed, and the ionic type that is mixed is N type element that the dosage of N type element is greater than the dosage of institute's doped P-type element.
2. method according to claim 1 is characterized in that, the dosage of said P type element is 1 * 10
15Individual/cm
2To 3 * 10
15Individual/cm
2
3. method according to claim 2 is characterized in that, said P type element is boron or indium
4. method according to claim 1 is characterized in that, the dosage of said N type element is 3 * 10
15Individual/cm
2To 5 * 10
15Individual/cm
2
5. method according to claim 4 is characterized in that, said N type element is phosphorus or arsenic.
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CN2009100559397A CN101989540B (en) | 2009-08-05 | 2009-08-05 | Method for doping polycrystalline silicon layer |
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CN2009100559397A CN101989540B (en) | 2009-08-05 | 2009-08-05 | Method for doping polycrystalline silicon layer |
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CN101989540B true CN101989540B (en) | 2012-07-25 |
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Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5753548A (en) * | 1996-09-24 | 1998-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for preventing fluorine outgassing-induced interlevel dielectric delamination on P-channel FETS |
CN101183648A (en) * | 2006-11-13 | 2008-05-21 | 上海华虹Nec电子有限公司 | High voltage PMOS transistor and method of manufacture thereof |
-
2009
- 2009-08-05 CN CN2009100559397A patent/CN101989540B/en active Active
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5753548A (en) * | 1996-09-24 | 1998-05-19 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method for preventing fluorine outgassing-induced interlevel dielectric delamination on P-channel FETS |
CN101183648A (en) * | 2006-11-13 | 2008-05-21 | 上海华虹Nec电子有限公司 | High voltage PMOS transistor and method of manufacture thereof |
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