CN100533706C - SOI衬底材料和形成具有不同取向的含Si的SOI和下覆衬底的方法 - Google Patents

SOI衬底材料和形成具有不同取向的含Si的SOI和下覆衬底的方法 Download PDF

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Publication number
CN100533706C
CN100533706C CNB200580036878XA CN200580036878A CN100533706C CN 100533706 C CN100533706 C CN 100533706C CN B200580036878X A CNB200580036878X A CN B200580036878XA CN 200580036878 A CN200580036878 A CN 200580036878A CN 100533706 C CN100533706 C CN 100533706C
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China
Prior art keywords
layer
contain
ion
crystal orientation
wafer
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Expired - Fee Related
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CNB200580036878XA
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English (en)
Chinese (zh)
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CN101048862A (zh
Inventor
M·利昂格
D·萨达纳
G·沙希迪
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Core Usa Second LLC
GlobalFoundries Inc
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International Business Machines Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1914—Preparing SOI wafers using bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers

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  • Element Separation (AREA)
  • Recrystallisation Techniques (AREA)
CNB200580036878XA 2004-11-18 2005-11-17 SOI衬底材料和形成具有不同取向的含Si的SOI和下覆衬底的方法 Expired - Fee Related CN100533706C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/992,150 2004-11-18
US10/992,150 US7141457B2 (en) 2004-11-18 2004-11-18 Method to form Si-containing SOI and underlying substrate with different orientations

Publications (2)

Publication Number Publication Date
CN101048862A CN101048862A (zh) 2007-10-03
CN100533706C true CN100533706C (zh) 2009-08-26

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CNB200580036878XA Expired - Fee Related CN100533706C (zh) 2004-11-18 2005-11-17 SOI衬底材料和形成具有不同取向的含Si的SOI和下覆衬底的方法

Country Status (6)

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US (2) US7141457B2 (enExample)
EP (1) EP1829098A1 (enExample)
JP (1) JP5236290B2 (enExample)
CN (1) CN100533706C (enExample)
TW (1) TWI374522B (enExample)
WO (1) WO2006053890A1 (enExample)

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* Cited by examiner, † Cited by third party
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JP2004119943A (ja) * 2002-09-30 2004-04-15 Renesas Technology Corp 半導体ウェハおよびその製造方法
US7531392B2 (en) * 2006-02-27 2009-05-12 International Business Machines Corporation Multi-orientation semiconductor-on-insulator (SOI) substrate, and method of fabricating same
US7285480B1 (en) * 2006-04-07 2007-10-23 International Business Machines Corporation Integrated circuit chip with FETs having mixed body thicknesses and method of manufacture thereof
US7732309B2 (en) 2006-12-08 2010-06-08 Applied Materials, Inc. Plasma immersed ion implantation process
US20080153271A1 (en) * 2006-12-18 2008-06-26 Applied Materials, Inc. Safe handling of low energy, high dose arsenic, phosphorus, and boron implanted wafers
US7651902B2 (en) * 2007-04-20 2010-01-26 International Business Machines Corporation Hybrid substrates and methods for forming such hybrid substrates
US7750406B2 (en) * 2007-04-20 2010-07-06 International Business Machines Corporation Design structure incorporating a hybrid substrate
US7749829B2 (en) 2007-05-01 2010-07-06 Freescale Semiconductor, Inc. Step height reduction between SOI and EPI for DSO and BOS integration
US7696573B2 (en) * 2007-10-31 2010-04-13 International Business Machines Corporation Multiple crystallographic orientation semiconductor structures
JP2012089639A (ja) * 2010-10-19 2012-05-10 Sumitomo Electric Ind Ltd 単結晶炭化珪素基板を有する複合基板
US9676168B2 (en) 2010-11-19 2017-06-13 Lamart Corporation Fire barrier layer and fire barrier film laminate
US8970032B2 (en) 2011-09-21 2015-03-03 Infineon Technologies Ag Chip module and method for fabricating a chip module
US9275911B2 (en) 2012-10-12 2016-03-01 Globalfoundries Inc. Hybrid orientation fin field effect transistor and planar field effect transistor
US10299407B2 (en) 2015-06-29 2019-05-21 Microsoft Technology Licensing, Llc Differently oriented layered thermal conduit
EP3742476B1 (en) * 2019-05-20 2024-11-06 Infineon Technologies AG Method of implanting an implant species into a substrate at different depths
KR102877317B1 (ko) 2020-10-30 2025-10-27 삼성전자주식회사 반도체 웨이퍼 및 그 제조 방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531375B1 (en) * 2001-09-18 2003-03-11 International Business Machines Corporation Method of forming a body contact using BOX modification
US20040061200A1 (en) * 2002-09-30 2004-04-01 Renesas Technology Corp. Semiconductor wafer and manufacturing method thereof
EP1453096A1 (en) * 2001-12-04 2004-09-01 Shin-Etsu Handotai Co., Ltd Pasted wafer and method for producing pasted wafer
US20040195622A1 (en) * 2003-04-07 2004-10-07 United Microelectronics Corp. Semiconductor structure with silicon on insulator

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JP2600299B2 (ja) * 1988-06-24 1997-04-16 ソニー株式会社 半導体装置の製造方法
JPH0590117A (ja) * 1991-09-27 1993-04-09 Toshiba Corp 単結晶薄膜半導体装置
JP3571734B2 (ja) * 1993-04-19 2004-09-29 セイコーインスツルメンツ株式会社 集積回路
US5726440A (en) * 1995-11-06 1998-03-10 Spire Corporation Wavelength selective photodetector
JP3512701B2 (ja) * 2000-03-10 2004-03-31 株式会社東芝 半導体装置及びその製造方法
JP2002299591A (ja) * 2001-03-30 2002-10-11 Toshiba Corp 半導体装置
US6541356B2 (en) * 2001-05-21 2003-04-01 International Business Machines Corporation Ultimate SIMOX
US6998353B2 (en) * 2001-11-05 2006-02-14 Ibis Technology Corporation Active wafer cooling during damage engineering implant to enhance buried oxide formation in SIMOX wafers
KR20040072738A (ko) * 2002-01-23 2004-08-18 스피나커 세미컨덕터, 인크. 변형 반도체 기판과 쇼트키 또는 쇼트키 콘택트와 유사한콘택트를 형성하는 소스 및/또는 드레인을 갖는 전계 효과트랜지스터
US20030194846A1 (en) * 2002-04-11 2003-10-16 International Business Machines Corp. Medium dose simox over a wide BOX thickness range by a multiple implant, multiple anneal process
US6835983B2 (en) * 2002-10-25 2004-12-28 International Business Machines Corporation Silicon-on-insulator (SOI) integrated circuit (IC) chip with the silicon layers consisting of regions of different thickness
US7329923B2 (en) 2003-06-17 2008-02-12 International Business Machines Corporation High-performance CMOS devices on hybrid crystal oriented substrates
US7291886B2 (en) * 2004-06-21 2007-11-06 International Business Machines Corporation Hybrid substrate technology for high-mobility planar and multiple-gate MOSFETs
JP2006040911A (ja) * 2004-07-22 2006-02-09 Renesas Technology Corp 半導体装置及びその製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6531375B1 (en) * 2001-09-18 2003-03-11 International Business Machines Corporation Method of forming a body contact using BOX modification
EP1453096A1 (en) * 2001-12-04 2004-09-01 Shin-Etsu Handotai Co., Ltd Pasted wafer and method for producing pasted wafer
US20040061200A1 (en) * 2002-09-30 2004-04-01 Renesas Technology Corp. Semiconductor wafer and manufacturing method thereof
US20040195622A1 (en) * 2003-04-07 2004-10-07 United Microelectronics Corp. Semiconductor structure with silicon on insulator

Also Published As

Publication number Publication date
CN101048862A (zh) 2007-10-03
TWI374522B (en) 2012-10-11
US7141457B2 (en) 2006-11-28
JP2008521229A (ja) 2008-06-19
EP1829098A1 (en) 2007-09-05
US20080128866A1 (en) 2008-06-05
TW200701408A (en) 2007-01-01
JP5236290B2 (ja) 2013-07-17
US20060105507A1 (en) 2006-05-18
WO2006053890A1 (en) 2006-05-26
US7759772B2 (en) 2010-07-20

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Effective date of registration: 20171113

Address after: Grand Cayman, Cayman Islands

Patentee after: GLOBALFOUNDRIES INC.

Address before: American New York

Patentee before: Core USA second LLC

Effective date of registration: 20171113

Address after: American New York

Patentee after: Core USA second LLC

Address before: New York grams of Armand

Patentee before: International Business Machines Corp.

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CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090826