CN100527406C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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CN100527406C
CN100527406C CNB200710143735XA CN200710143735A CN100527406C CN 100527406 C CN100527406 C CN 100527406C CN B200710143735X A CNB200710143735X A CN B200710143735XA CN 200710143735 A CN200710143735 A CN 200710143735A CN 100527406 C CN100527406 C CN 100527406C
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朱星中
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Abstract

本发明提供一种半导体器件及半导体器件的制造方法。该半导体器件可包括：半导体衬底；层间介电层，形成于该半导体衬底上，具有镶嵌图案；扩散阻碍件，形成于镶嵌图案中，且由三价材料制成；籽晶层，形成于该扩散阻碍上；以及铜互连件，形成于该籽晶层上。在一个实施例中，该三价材料为CoFeB。本发明将非结晶层用作扩散阻碍件来避免铜的扩散，提高了半导体器件的性能。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件，特别涉及具有扩散阻碍层的半导体器件及其制造方法。
背景技术
通常，用金属互连将半导体器件中的器件电性互连。铝(Al)、铝合金和钨常用作金属互连的材料。
然而，由于半导体器件高度集成，所以此类金属因其低熔点和高特性阻抗的特点而难以利用。铜(Cu)、金(Au)、银(Ag)、钴(Co)、铬(Cr)和镍(Ni)都具有优良的导电性并可用作金属互连的材料。尤其是铜和铜合金，其具有低特性阻抗、优良的电子迁移(electron migration，EM)和应力迁移(stress migration，SM)的可靠性，而且制造成本低，因此得到了广泛应用。
使用铜的金属互连件通常是用镶嵌工艺制造的。镶嵌工艺通过光处理工艺和蚀刻工艺在绝缘层中形成沟槽，然后在该沟槽中填充导电材料，如钨、铝或铜。然后，通过回蚀(etch-back)或化学机械抛光除去大部分导电材料，保留所需互连部分，从而形成具有与该沟槽对应的形状的互连件。
但是，铜不适合于干法蚀刻工艺而且不易附着于SiO2。铜具有低热动力学稳定性(thermo-dynamical stability)和低抗腐蚀能力。另外，铜可用作扩散入硅中的深层掺杂剂从而在带隙中产生受体和供体状态，因此导致漏电流或器件的故障。
所以，本领域需要一种能够用于铜的有效扩散阻碍层。
发明内容
本发明的实施例提供一种半导体器件，其中将非结晶层用作扩散阻碍件来避免铜的扩散，从而提高半导体的性能。
根据一个实施例，提供一种半导体器件，该半导体器件包括：半导体衬底；层间介电层，形成于该半导体衬底上，具有镶嵌图案；扩散阻碍件，形成于该镶嵌图案中，并且由三价材料，例如CoFeB制成；籽晶层，形成于该扩散阻碍件上；以及铜互连件，形成于该籽晶层上。
根据一个实施例，提供一种半导体器件的制造方法，包括：在半导体衬底上形成层间介电层，并在该层间介电层中形成镶嵌图案；在该层间介电层上以预定厚度沉积三价材料例如CoFeB，从而形成扩散阻碍件；在该扩散阻碍件上沉积籽晶层；以及在镶嵌图案中填充铜互连件。
本发明的上述以及其他目的和特征将在以下的详细说明中伴随附图进一步清晰。
附图说明
图1为CoFeB的强度和角度关系的曲线图。
图2为无退火的情况下CoFeB的强度和溅射时间关系的曲线图。
图3为200℃铜退火的情况下CoFeB的强度和溅射时间关系的曲线图。
图4到图8为根据本发明实施例的半导体器件的制造方法的截面图。
具体实施例
以下参照附图详细解释本发明实施例。
图1到图3为强度和角度或溅射时间曲线图。这些图对应于具有钽(Ta)层、第一铜层、IrMn层、第二铜层和CoFeB层的半导体器件。所述钽层、第一铜层、IrMn层、第二铜层和CoFeB层分别沉积到50
Figure C200710143735D0004113715QIETU
、20
Figure C200710143735D0004113715QIETU
、100
Figure C200710143735D0004113715QIETU
、6
Figure C200710143735D0004113715QIETU
和100
Figure C200710143735D0004113715QIETU
。然后从CoFeB层进行溅射。
参照图1，溅射粒子的强度取决于溅射角度。
在图1的曲线中示出，每种材料由于其特性而在一个预定角度有一个顶点。因此可确定，当对CoFeB层进行溅射时，如果在某个时刻出现了由于CoFeB的特性产生的顶点，则CoFeB具有晶体结构。此外，如果在特定角度并未出现由于CoFeB特性产生的顶点，则CoFeB具有非结晶结构。
如图1所示，在介于大约44度与大约46度之间的溅射角度具有强度顶点不是出自CoFe自身的特性。因此，CoFeB是一种具有非结晶结构的三价材料。
此处，在大约41度处出现了由于IrMn的特性产生的强度顶点。
在钽、铜、IrMn、铜和CoFeB堆叠的结构中，溅射依CoFeB、铜、IrMn、铜和钽的顺序进行。通过确认观察到的铜仅在预定时区随溅射时间增加，该结构帮助确定能否避免铜的扩散。
如图2所示，形成该堆叠结构后，在溅射进行大约1.6分钟之后出现了一个顶点，在大约2.25分钟的溅射时间之后出现了另一顶点。
在首次溅射后0.5分钟内，溅射铁和钴，并极弱地溅射铜。所以，铜的扩散被CoFeB所抑制。基于这些测试，可见非结晶三价材料可针对铜提供改善的扩散阻碍件。在一个实施例中，将CoFeB用作铜的扩散阻碍件。在另一实施例中，将作为非结晶三价材料的CoFeN用作铜的扩散阻碍件。
在一个实施例中，本发明提供利用诸如CoFeB之类三价材料作为扩散阻碍层的半导体器件的制造方法。
参照图4，在一个实施例中，第一层间介电层2和第二层间介电层3堆叠在半导体衬底1上，该衬底具有器件电极或导电层构成的层。然后，针对第一层间介电层2和第二层间介电层3进行光处理工艺和蚀刻工艺，从而形成镶嵌图案10。在进一步的实施例中，可在第一层间介电层2与半导体衬底1之间形成第一蚀刻阻止层，当蚀刻第一层间介电层2时该第一蚀刻阻止层用作蚀刻停止点。第一蚀刻阻止层可直接在半导体衬底1上形成。在第一层间介电层2上，可在第一层间介电层2与第二层间介电层3之间形成第二蚀刻阻止层。在某些实施例中，第二蚀刻阻止层可使用等离子体增强型CVD(PECVD)设备形成为氮化物层(SiN)。
参照图5，在一个实施例中，扩散阻碍件4形成于所形成的镶嵌图案10所暴露的部分。扩散阻碍件4帮助避免铜从镶嵌图案10中的铜互连件扩散进入层间介电层2和3。
扩散阻碍件4可通过物理气相沉积(PVD)法沉积三价材料而形成。在一个实施例中，三价材料为CoFeB。在另一实施例中，三价材料为CoFeN。在众多实施例中使用CoFeB作为扩散阻碍件4，CoFeB的构成比例设定为：约30％到约70％范围内的钴(Co)：约70％到约30％范围内的铁(Fe)：约5％到约10％范围内的硼(B)。扩散阻碍件4的厚度可为500
Figure C200710143735D0004113715QIETU
到1000
Figure C200710143735D0004113715QIETU
。
为了达到加强半导体器件的层间连接的导电性的目的，在CoFeB中钴和铁的构成比例与硼的构成比例高度相关。
参照图6，可在扩散阻碍件4上形成籽晶层5。籽晶层5作用为向填充在镶嵌图案10中的铜互连件稳定提供电子，从而加速铜互连件的生长。在一个实施例中，可通过化学气相沉积(CVD)在籽晶层5上沉积铜。
参照图7，在一个实施例中，通过电解铜电镀或化学气相沉积法在籽晶层5上形成用于层间互连的铜，从而形成铜互连件7。当填充铜互连件时，籽晶层5可扩散进入铜互连件7，同时加速铜的生长。
参照图8，在一个实施例中，形成铜互连件7后，进行CMP工艺，从而对铜互连件7的表面进行平坦化。
在众多实施例中，用作扩散阻碍件4的材料为三价非结晶材料。非结晶三价材料针对半导体器件中的铜扩散提供改善的阻碍。在一个实施例中，扩散阻碍件4为CoFeB。在另一实施例中，扩散阻碍件为CoFeN。
在本说明书中，任何涉及“一个实施例”、“一实施例”、“示范实施例”等之处，都意味着所描述的与该实施例相关的特殊的特性、结构或特征是包括在本发明的至少一个实施例中的。在本说明书中多处出现的此类描述并非必然都指向相同的实施例。另外，当描述与任一实施例相关的特殊的特性、结构或特征时，应理解成在本领域技术人员的能力范围内可使得该特性、结构或特征与其他实施例相关地起作用。
虽然已经参照多个实施例详细介绍本发明，但是本领域技术人员在本发明的精神和原理内，当可作各种修改、等同替换、或改进。特别是，在本发明的说明书、附图和权利要求的公开范围之内能够进行各部件和/或部件组合安排中的各种修改、等同替换、或改进。此外，本领域技术人员显然可对各部件和/或部件组合安排作各种修改、等同替换、或改进。

Claims (4)

1.一种半导体器件，包括：
半导体衬底；
层间介电层，在该半导体衬底上，具有镶嵌图案；
扩散阻碍件，形成于镶嵌图案中，包括CoFeB；
籽晶层，形成于在该扩散阻碍件上；以及
铜互连件，形成于该籽晶层上。
2.如权利要求1所述的半导体器件，其特征在于，该扩散阻碍件的厚度为500
Figure C200710143735C0002174225QIETU
到1000
Figure C200710143735C0002174225QIETU
。
3.一种半导体器件的制造方法，包括：
在半导体衬底上形成层间介电层；
在该层间5介电层中形成镶嵌图案；
在该层间介电层上沉积CoFeB以形成扩散阻碍件；
在该扩散阻碍件上沉积籽晶层；以及
将铜互连件填充到该镶嵌图案中。
4.如权利要求3所述的方法，其特征在于，该扩散阻碍件的厚度为500
Figure C200710143735C0002174225QIETU
到1000
Figure C200710143735C0002174225QIETU
。
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JP2008042199A (ja) 2008-02-21
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