TW484203B - Method to deposit a platinum seed layer for use in selective copper plating - Google Patents

Abstract

A method of fabricating single and dual damascene copper interconnects is achieved. A semiconductor substrate layer is provided. Conductive traces are provided in an isolating dielectric layer. An intermetal dielectric layer is deposited overlying the conductive traces and the isolating dielectric layer. The intermetal dielectric layer is patterned to from trenches to expose the top surfaces of the underlying conductive traces. A barrier layer is deposited overlying the intermetal dielectric layer, the exposed conductive traces, and within the trenches. A platinum ionic seed solution is coated inside the trenches and overlying the barrier layer. A platinum seed layer is deposited from the ionic seed solution by exposing the platinum ionic seed solution to ultraviolet light. A copper layer is deposited by electroless plating to form copper interconnects, where the copper layer is only deposited overlying the platinum seed layer in the trenches, and where the deposition stops before the copper layer fills the trenches. The exposed barrier layer is polished down to the top surface of the intermetal dielectric layer. An encapsulation layer is deposited overlying the copper interconnects and the intermetal dielectric layer to complete the fabrication of the integrated circuit device.

Description

484203 V. Description of the invention (ο [Background of the invention] (1) Field of the invention The present invention relates to the manufacture of semiconductor substrates, and more particularly to the formation and insertion of inlaid inner conductors in the manufacture of integrated circuits. (2) Description of the conventional arts As the size of integrated circuit features continues to decrease, this becomes advantageous for the use of copper instead of aluminum to make metal wiring, copper Has a lower resistivity than aluminum, and therefore can form higher speed connections as a known line width. However, the disadvantage of copper is that copper is more difficult to etch reliably than aluminum, in order to make copper traces. Therefore, alternative design methods such as damascene and dual damascene structures have been used. By using damascene technology, copper wire etching can be removed. However, the trench is first cut into the isolation dielectric at the designed conductive trace The material is then deposited to fill the trench. A lapping process is used to etch back any overfilled copper in the trench. In this way, the mosaic method provides The use of copper in the wire. Refer to Figure 1, which shows a part of the complete conventional dual-mosaic structure. It describes a substrate layer 10, which includes all the bottom layers, components, joints, and isolation. The deposition of conductive trace 18 in layer 14 and other features that have been formed before the definition, dielectric layer 2 2 is overlaid on isolation layer 14 and partially over conductive trace 18. The opening is shown to be formed in the dielectric layer 22 to expose the top surface of the conductive trace 18, a trench is also formed in the dielectric layer 22, and a barrier layer 30 is to be formed.

484203 V. Description of the invention (2) Deposited on the dielectric layer 22 and the exposed conductive traces 丨 8, the purpose of the barrier layer 3 is to prevent the subsequently deposited steel from diffusing into the conductive traces 18 or the dielectric In layer 22, because the copper layer will be deposited using electroless plating, a crystal layer 34 is deposited on the barrier layer 30, and the purpose of the crystal layer 34 is to provide a thin layer of activating atoms to catalyze In the electroless plating process, the crystal layer 34 may be composed of copper, platinum, or palladium. The crystal layer 34 is typically deposited by a physical vapor deposition (pvD) or chemical vapor deposition (CVD) process. Referring to FIG. 2, the results of electroless plating of the copper layer 38 are shown. It is assumed that copper is the copper crystal layer 34. During the deposition process, the crystal layer 34 is absorbed in the copper layer 38. It is noted that copper Layer 3 8 is deposited on the wafer everywhere and covers the barrier layer 30. The copper layer 38 is deposited because the crystal layer 3 4 is also deposited on the wafer everywhere. In order to form the inner wires, the excess must be removed. Both the copper layer 38 and the excess barrier layer 30 are typically obtained by a chemical mechanical polishing (CMP). Referring now to FIG. 3, during the CMP process, the copper layer 38 is ground to a plug, a The sealant layer 42 is deposited on the copper layer 38 to protect the copper from oxidation in the subsequent process steps. In conventional techniques, this will facilitate the removal of the CMP process used to grind away the copper layer 38. In order to complete this step, 'it is only helpful for the deposition of copper needed, and likewise' this will help simplify the use of crystal layers 3 4 process, and make the cost less. Several conventional techniques seek to improve the electroless mining process used in the metallization of integrated circuits. US Patent No. 5,674,787 (Zhao et al.) Teaches a process for selectively depositing copper to form inner conductor plugs. A copper ion

Page 8 484203 V. Description of the invention (3) The seed crystal layer is used in the electroless copper electroplating process. A dielectric layer is deposited and anisotropic silver is etched to form a dielectric resistance barrier on the sidewall of the conductive trench. An adhesive layer is covered with copper plugs by electroless plating. U.S. Patent No. 5,723,387 (Chen) discloses a device and process for forming copper inner conductors. Platinum or palladium ions are used as a crystal layer to activate electroless plating of the copper layer. The copper layer is not selective. It must be deposited on the ground and electroplated after CMP. U.S. Patent No. 4,574,095 (Baum et al.) Teaches a process for the selective deposition of copper by the formation of a palladium crystal layer, photoinduced decomposition of a gaseous compound, at a wavelength of 249 nm, electroless plating A copper layer is then deposited where the palladium layer is deposited. US Patent No. 5,824, 59 9 (Svhachain-Diamond et al.) Teaches a process by electroless plating instead of selectively depositing a copper layer, an aluminum layer is deposited over the copper crystal layer to prevent Oxidation of the crystalline layer before power mining. U.S. Patent No. 5,308,796 (Feldman et al.) Discloses a process for selectively depositing a copper layer over a metal silicide layer. U.S. Patent No. 4,692,349 (Georgiou et al.) Discloses a process in which electroless keys or nickel are used to form via plugs. [Summary of the Invention] A main object of the present invention is to provide an efficient and extremely manufacturable method for manufacturing an integrated circuit having a copper inner conductor. Another object of the present invention is to provide a method for manufacturing copper inner conductors by depositing copper using an electroless plating process. Another object of the present invention is to provide a method for manufacturing copper inner conductors', which is selectively deposited on a steel layer system, so that a small or no amount of copper needs to be removed by chemical mechanical grinding.

484203 V. Description of the invention (4) Another purpose of the present invention is to produce copper in electroless electroplating, which is deposited by photoreduction effected by a platinum crystal layer. According to the objective method of the present invention, a semiconductor is provided. In the dielectric layer, a metal interlayer dielectric layer is exposed, and the metal layer exposes the bottom conductive traces to the metal interlayer dielectric layer. The exposed ion seed solution is coated with a crystal layer and exposed to ultraviolet light from the platinum ion seed solution. Light, once a steel inner wire is formed, it is tied to the steel, and the copper layer fills the groove and is ground until the metal layer is dielectrically connected to the steel inner wire and the metal layer is overlaid on the sealant layer. Brief description] is to provide a method for selecting copper wires by copper, 'selective electroless plating of copper'. The platinum crystal layer is obtained by using a platinum ion solution to obtain the substrate, and the dielectric between the dielectric layers is exposed. The copper layer system passed through the trench is only completed by the top dielectric of the previous sink layer, resulting in a conductive trace system. The deposited layer system is resisted by the surface. 0 8 0 8 0 Substrate layer conductive trace resistance Barrier layer The inner and overlying conductors on the traces are formed by overlying the surface where the overlying stops stop by electroless deposition. On one layer, the 14 2 2 3 4 4 2 5 copper-made inner conductor system of the integrated circuit is provided in the overlying conductive case The exposed barrier layer is fabricated by passivation with a barrier layer system and a trench on the barrier layer by plating platinum ions into the trench. Isolation layer, dielectric layer, crystal layer, sealant layer, the new method of isolation layer, an isolation trace and trench formation, and the platinum, the first seed crystals are dissolved to the surface layer, the barrier layer, the deposition layer, and the system is sunk.

484203 V. Description of the invention 5 8 7 0 7 6 8 0 8 8 10 4 112 12 0 12 8 13 6 [It is better to form the inner part of the inner conductor of the conductor, double-embedded the current part, the conductor, the cooked steel structure The surface, and the line 5 8 such as the electrical layer 6 2 series dielectric layer 'in the sunken (5) conductive trace barrier layer platinum crystal layer copper layer passive state isolation layer second barrier metal layer crystal layer sealant The comparison of the layer examples is better. The shape of this line is only formed by comparing this technique. Isolation layer technology is best deposited after 6 2 is best and the line protective layer is separated from the interlayer dielectric layer. [Detailed description of the preferred embodiment is shown in FIG. 12 and FIG. In the preferred embodiment, the artisan should provide that the substrate 50 series contains 5 4 before the deposition. The middle system is provided to cover the conductive traces and is planarized by an oxide group, up to 6 2 7 4 7 8 8 4 1 0 0 1 0 8 1 1 6 12 4 13 2 14 0 The description of the present disclosure indicates that the double-inlay system of the present invention shows that the present invention has all the isolation layer lines 58 formed, and variously, the metal interlayer dielectric layer platinum. Ionic seed solution, ultraviolet light sealant layer, semiconductor substrate, conductive traces, conductive vias, plugging barrier layer, copper layer, passivation protective layer, applied to double inlaid steel, invented to be applied to a single town, and features to be applied to a single- or funnel structure A partially completed integrated circuit will be used in the manufacture of steel. The present invention can be applied to other bottom layers, components, and other features of bonding. The conductive trace 54 is a metal interlayer dielectric isolation layer 54, such as a low-k metal layer. Frosted glass (FSG) metal interlayer dielectric layer 6 2 series

Page 11 484203 V. Description of the invention (6) It is deposited to reach a top surface of the layer between the bottom layer and the bottom layer. The second part is well-known as the current dielectric barrier barrier diffusion as a low (TaN) dielectric. The layer 70 reaches the first layer. • The copper layer, the crystal, or the electricity to be charged can effectively form a dielectric layer 62 on the 5th conductive type, and then the ground is engraved for the purpose of example. groove. In reference to the sixth layer 62, the purpose of conducting 70 is to use the adhesion of the layers of the group of sheets that are still in contact with the resistance path, by depositing-at about 50 angstroms to the electroless plating layer referred to in the seventh can be electroplated Otherwise the thickness of the electroplated layer catalyzed by the forged compound is between 4,00 angstroms and 1,800 angstroms. In the figure, the metal interlayer dielectric layer 62 is patterned with trenches. Many conventional techniques can be used to form the trenches. First, the gold that is not protected by a photoresist mask is etched to form a narrower via hole trench. The conductive trace 5 8 is a metal interlayer dielectric layer that is not protected by a photoresist mask to form a wider inner conductor groove. For this comparison, combining the via hole groove and the inner conductor groove will be a simple diagram. The barrier layer 70 is deposited on the exposed surface of the trace 58 and the trench prevents the subsequent oxidation of the copper conductive layer 58 and the subsequent formation of the copper wire diameter. The barrier layer 70 is formed by One button (Ta), and the first sheet and the nitride button are used to improve the second sheet, and the system is a low-resistivity barrier layer tantalum (Ta) and a nitride button (TaN), and is shaped as 80 Angstroms. Between thickness. The figure describes an important aspect of the present invention. Before plating, a crystal layer must survive in the reaction as a thruster, and be plated with an alloy and a plating layer. This type of crystal layer is typically composed. In this embodiment, It is copper, or should be a kind of atomic nucleus. In this invention, a metal group of a nitride group is provided in the crystalline metal layer groove, and the barrier is formed by the feature that the deposition solution is absorbed by another layer.

484203 V. Description of Invention (7) --- consists of. The platinum crystal layer system is formed in a simple and novel method. First, a platinum ion seed solution 74 is coated and connected to the barrier layer 70. The platinum ion seed solution 74 is preferably applied by a spin coating. A significant amount of a solution is gathered in the trenches as a thin layer passes through the wafer, as shown in FIG. 7, and the platinum ion seed solution 74 of the present invention is formed by ptCl4 (gasification Platinum) or NazPtCl 6 (gas platinum) and dissolved in isopropanol. Referring now to FIG. 8, following the spin coating of the platinum ion seed solution 74, the circle system is exposed to visible or ultraviolet light 78, and the light source 78 is composed of a spectral wavelength of less than 488 nanometers. Exposure of the solution 7 4 to the light source 7 8 causes the light of the platinum cation 2 in the solution to be reduced to a neutral surface. Platinum is deposited to form a platinum crystal layer 7 6. For example, if the ion seed solution 7 4 is composed of N a β The composition of t C 1 minus isopropanol 'the ionic species in the solution is PtC 1 e2-' The next demonstration reaction occurred in the ion seed solution 74, which exposed the light source 7 8 to less than 4 8 8 nm. At the spectral frequency: hv ptcl62- + CH3-C-CH3— Pt. + CH3CH0

I

• OH crystal layer 7 6 is thus deposited on the barrier layer 70 in the trench. This process for forming a platinum crystal layer, ie, the subsequent deposition of copper by electroless plating, represents a Significant simplification is compared to conventional techniques that use some form of physical vapor deposition (PVD) or chemical vapor deposition (CVD) to deposit crystal layers.

Page 13 484203 V. Description of the invention (8) At this time, the barrier layer 70 can be polished off to the top surface of the interlayer dielectric layer 62. This step is not mandatory for the process sequence, and can be postponed until the copper After the deposition of the layers, this non-mandatory disadvantage is that the > interlayer dielectric layer 62 will be exposed to the copper electromineral solution, and some copper can be absorbed into the dielectric material by this method.

Referring to FIG. 9, which shows another feature of the present invention, a copper layer 80 is deposited on the platinum crystal layer 76 by electroless plating, and the copper layer fills the trench to form a copper inner conductor. Before the trench is completely filled with the copper layer 80, the deposition step is stopped periodically, because the steel layer 80 is only formed in the trench where the platinum crystal layer 76 exists, and does not extend beyond the interlayer dielectric layer 62. As is customary, usually it is not necessary to grind off the excess copper material. To grind the gray copper layer 80, the amount of grinding should be very small. The 4 steel layers can reach 3, 0 0 0 Angstroms to 1 7 , Thickness between 50 0 Angstroms. The steel layer 80 deposition system is performed in a copper-containing solution of an electroless deposition mechanism. Two different deposition solutions are disclosed here in a preferred example. The M-first copper-containing solution is composed of a concentration of about 3. 丨G / L Cu Cu Sulfate), edt diamine at a concentration of about 20.0 g / L

= Acetic acid) disodium salt, Na2S0 u HCH (U T with a concentration of about 20.0 g / L) and a concentration of about 40.0 g / L

And polyethylene glycol with a concentration of about 6.6 g / liter; sodium sulfate), and the base number (PH) was adjusted to about 7.0 using NaOH, and the acid produced by this solution was warmed between 9 (TC). The degree of m was maintained at about 1 (TC to—The second copper-containing solution is composed of a solution of about 8.51 ° (copper sulfate) and a concentration of about 37%: liter of CuS04 · 2ml / liter of HCH0

Page 14 484203 V. Description of the invention (9) (formic acid) and a di-sodium salt of EDTA (ethylenediaminetetraacetic acid) at a concentration of about 57.3 g / liter 'The pH value of this solution Adjusted to about n. 2 and the temperature was held at about 65 ° C. Referring now to FIG. 10, the barrier layer 70 is ground to the top surface of the interlayer dielectric layer 62. If the barrier layer 70 is ground before the copper layer 80 is deposited, this step can be omitted. The polishing step is performed using a conventional chemical mechanical polishing (CCMP). Referring now to FIG. 11, an adhesive layer 84 is deposited on the copper inner conductor 80 and the interlayer dielectric layer 62, and the sealing layer 84 provides electrical isolation from the top surface of the copper layer 80. Preferably, the sealant layer 84 is composed of silicon nitride, and is usually deposited to a thickness between 200 angstroms and 100 angstroms. It is preferable that the pure state protective layer 8 8 composed of plasma nitride is formed and covered on the sealant layer 8 4 to complete the manufacture of the integrated circuit element. Referring now to FIG. 12, it is explained that a completed single damascene copper inner conductor constituted by the present invention, and a conductive trace 108 is provided in the isolation layer 104 overlying the semiconductor substrate 100, one A conductive via plug consisting of crane or copper is formed in a second isolation layer 112. Then, the principle and characteristics of the present invention will be described by way of example. A metal interlayer dielectric layer 12 is deposited on the conductive via plug Π 6 and the second isolation layer 11 2. The metal interlayer dielectric layer 1 2 0 is Patterned to form a trench to bottom conductive via plug 1 1 6, a barrier layer such as a button or tantalum nitride 1 24 is deposited overlying the interlayer dielectric layer 1 2 0, the exposed conductive via plug 11 6, and in the trench, a platinum crystal layer 1 2 8 is deposited on the barrier layer 1 2 4. As in the previous embodiment, a copper layer 1 3 2 is formed by electroless plating. Is deposited to fill the trench, and

484203 V. Description of the Invention (ίο) Therefore, a copper inner wire is formed, and the exposed barrier layer 12 4 is ground to the top surface of the metal interlayer dielectric layer 1 2 0. A sealing layer such as silicon nitride i 3 6 is coated. Deposited on the copper inner wire and the interlayer dielectric layer. Finally, the passive protective layer 140 is deposited on the sealant layer to complete the manufacture of the integrated circuit element. The object of the present invention is to provide a selective electric copper with extremely manufacturable wires, which is manufactured by integrated circuit elements :; system 1 =-flip crystal layer 'double inlay and single inlay: soil =. Traverse already used this method

Although the present invention has been described with reference to its preferred implementation, those skilled in the art should understand that θ? Specifically stated and said changes may be made without departing from the spirit of the present invention, ^ in terms of form and details a ' Of it.

484203 Schematic illustrations Figures 1 to 3 are cross-sectional views illustrating the use of copper inner conductor structures for part of a complete conventional technique. Figures 4 to 12 are cross-sectional views illustrating the use of the present invention for manufacturing copper inner conductors.

Circle I Page 17

Claims (1)

484203 VI. Application Patent Scope 1. A method for forming copper inner conductors in the manufacture of integrated circuit components, comprising: providing a semiconductor substrate; depositing a dielectric layer overlying an isolation layer; patterning the dielectric Layer to form a trench; deposit a barrier layer overlying the dielectric layer and within the trench; apply an ion seed solution to cover the barrier layer; from the ion seed solution The deposition of a crystalline layer exposes the ion seed solution to light; a copper layer is deposited over the crystalline layer by electroless deposition, thereby forming a copper inner conductor, wherein the copper layer is deposited only in the trench And wherein the deposition step is stopped before the copper layer fills the trench; the barrier layer is polished away to the top surface of the dielectric layer, so that the barrier layer stays in the trench only; An encapsulation layer is connected to the copper inner wire and the dielectric layer; and the manufacturing of the integrated circuit is completed. 2. The method according to item 1 of the scope of patent application, wherein the barrier layer includes a group and a nitride button, and is deposited to a thickness of between 50 angstroms and 800 angstroms. 3. The method according to item 1 of the scope of the patent application, wherein the ion seed solution includes isopropyl alcohol and one of the groups consisting of PtCl4 and Na2PtCl. 4. The method according to item 1 of the scope of patent application, wherein the step of depositing the crystal layer from the ion seed solution is performed by using the ion seed Page 18 484203 VI. Scope of patent application The solution is exposed to visible or ultraviolet light and consists of a spectral wavelength shorter than 4.8 nm. 5. The method as described in item 1 of the scope of the patent application, wherein the crystal layer system is started. 6. The method according to item 1 of the scope of patent application, wherein the step of depositing a copper layer by electroless plating is performed in a solution including CuS04, 5H20 (copper sulfate), Disodium salt of EDTA (ethylenediaminetetraacetic acid), HCH0 (formaldehyde), Na2S04 · 10H20 (sodium sulfate). 7. The method according to item 1 of the scope of patent application, wherein the step of depositing a copper layer by electroless plating is performed in a solution, the solution includes: CuS04 · 5H20 (copper sulfate), HCH0 (Formaldehyde), and disodium salt of EDTA (ethylenediaminetetraacetic acid). 8. The method according to item 1 of the scope of patent application, wherein the sealant layer is composed of silicon nitride and is deposited to a thickness between 200 angstroms and 1,000 angstroms. 9. The method according to item 1 of the scope of patent application, wherein the step of grinding away the barrier layer is performed before the step of depositing the copper. 1 0 · A method for forming copper inner conductors in the manufacture of integrated circuit elements, comprising: providing a semiconductor substrate; depositing a dielectric layer overlying an isolation layer; patterning the dielectric layer to form A trench; depositing a barrier layer overlying the dielectric layer and within the trench; 484203 VI. Application for patent scope Coating a platinum ion seed solution overlying the barrier layer. 'Deposit a platinum crystal layer from the platinum ion seed solution' to expose the #ion seed solution to light ; Depositing a steel layer over the heterocrystalline layer by electroless deposition 'thus forming a copper inner conductor, wherein the copper layer is deposited only in the trench' and wherein before the copper layer fills the trench, Stopping the deposition step; grinding away the barrier layer to the top surface of the dielectric layer so that the barrier layer only stays in the trench; Depositing an adhesive layer overlying the copper inner conductor and the dielectric layer; and completing the fabrication of the integrated circuit. 11. The method as described in item 10 of the scope of the patent application, wherein the barrier layer includes tantalum and a nitride button, and is deposited to a thickness between 50 angstroms and 800 angstroms. 12. The method according to item 10 of the scope of patent application, wherein the platinum ion seed solution comprises isopropion, and is composed of one of PtCl4 and Na2Ptci. 1 3 · The method as described in Item 10 of the scope of patent application, wherein the step of depositing a copper layer by electroless recording is performed in a solution, the solution includes: CuS04 · 5H2〇 ( Copper sulfate), EDTA (ethylene diamine tetra Disodium salt of acetic acid), HCH0 (formaldehyde), Na2S04 · ioh20 (sodium sulfate 14 · The method as described in item 10 of the patent application scope, wherein the step of depositing a steel layer by electroless plating, The system is carried out in a solution including CuS04, 5H2O (copper sulfate), HCH0 (formaldehyde), and Page 20 484203 6. Scope of patent application Disodium salt of EDT A (ethylene diamine tetraacetic acid). 15 · The method as described in item 10 of the scope of patent application, wherein the step of depositing the platinum crystal layer from the ship ion seed solution is by exposing the platinum ion seed solution to visible or ultraviolet light , Is composed of a spectral wavelength shorter than 4.8 nm. [16] The method as described in item 10 of the scope of patent application, wherein the step of grinding away the barrier layer is performed before the step of depositing the copper. 17. · A method for forming copper inner conductors in the manufacture of integrated circuit components, including: Providing a semiconductor substrate; depositing a dielectric layer overlying the isolation layer; patterning the dielectric layer to form a trench; depositing a barrier layer overlying the dielectric layer and in the trench; coating A platinum ion seed solution is covered on the barrier layer, wherein the platinum ion seed solution includes isopropyl alcohol and is composed of one of the groups of PtCl4 and Na 2P t C 1; Depositing a platinum crystal layer in the platinum ion seed solution, exposing the platinum ion seed solution to light shorter than 4.8 nm; A copper layer is deposited on the flip layer by electroless deposition, thereby forming a copper inner conductor, wherein the copper layer is deposited only in the trench, and before the copper layer fills the trench, Stop the deposition step; grind away the barrier layer to the top surface of the dielectric layer so that the barrier layer stays in the trench only; deposit an adhesive layer overlying the copper inner conductor and the dielectric On the floor; and Page 21 484203 6. Scope of patent application Complete the manufacture of integrated circuits. 18 · The method as described in item 17 of the scope of patent application, wherein the step of depositing a copper layer by electroless plating is performed in a solution, the solution includes: CuS04 · 5H20 (copper sulfate) , Disodium salt of EDTA (ethylenediaminetetraacetic acid), HCH0 (formaldehyde), Na2S04 · 10H2O (sodium sulfate). 19. The method according to item 17 of the scope of patent application, wherein the step of depositing a copper layer by electroless plating is performed in a solution including CuS04 · 5H20 (copper sulfate), HCH0 (Formaldehyde), and disodium salt of EDTA (ethylenediaminetetraacetic acid). 2 0. The method according to item 17 of the scope of patent application, wherein the step of grinding away the barrier layer is performed before the step of depositing the copper. f Page 22