CN100502029C - 相变化存储器件及其形成方法 - Google Patents

相变化存储器件及其形成方法 Download PDF

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CN100502029C
CN100502029C CN200710105141.XA CN200710105141A CN100502029C CN 100502029 C CN100502029 C CN 100502029C CN 200710105141 A CN200710105141 A CN 200710105141A CN 100502029 C CN100502029 C CN 100502029C
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phase change
change element
memory
bit line
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CN101079438A (zh
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龙翔澜
刘瑞琛
陈逸舟
陈士弘
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Macronix International Co Ltd
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Abstract

本发明公开一种存储器件，包括：存储元件阵列，其形成于半导体晶片上；字线平行阵列，其沿着第一方向延伸、并将每一存储元件连接至数据来源；以及位线平行阵列，其沿着第二方向延伸、并将每一存储元件连接至数据来源，第二方向与第一方向形成锐角。每一位线与每一存储元件之间的连结为相变化元素，此相变化元素由具有至少二固态相的存储材料所形成。

Description

相变化存储器件及其形成方法
联合研究合约的当事人
纽约国际商业机械公司、台湾旺宏国际股份有限公司及德国英飞凌技术公司(Infineon Technologies A.G.)为联合研究合约的当事人。
技术领域
本发明涉及非易失性存储结构，并尤其涉及使用相变化存储元件的存储阵列。
背景技术
以相变化为基础的存储材料被广泛地运用于读写光盘以及非易失性存储阵列中。这些材料包括有至少两种固态相，包括如大部分为非晶态的固态相，以及大体上为结晶态的固态相。激光脉冲用于读写光盘中，以在二种相中切换，并读取此种材料在相变化后的光学性质。
如硫属化物及类似材料的这些相变化存储材料，可通过施加其幅度适用于集成电路中的电流，而引起晶相变化。一般而言，非晶态的特征为其电阻高于结晶态，此电阻值可轻易测量得到而用以作为指示。这种特性则引发使用可编程电阻材料以形成非易失性存储器电路等兴趣，此电路可用于随机存取读写。
从非晶态转变至结晶态一般为低电流步骤。从结晶态转变至非晶态(以下指称为重置(reset))一般为高电流步骤，其包括短暂的高电流密度脉冲以融化或破坏结晶结构，其后此相变化材料会快速冷却，抑制相变化的过程，使得至少部份相变化结构得以维持在非晶态。理想状态下，引起相变化材料从结晶态转变至非晶态的重置电流幅度应越低越好。欲降低重置所需的重置电流幅度，可通过减低在存储器中的相变化材料元件的尺寸、以及减少电极与此相变化材料的接触面积而达成，因此可针对此相变化材料元件施加较小的绝对电流值而达成较高的电流密度。
此领域发展的一种方法致力于在集成电路结构上形成微小孔洞，并使用微量可编程电阻材料填充这些微小孔洞。致力于这些微小孔洞的专利包括：于1997年11月11日公开的美国专利No.5,687,112，，题为“Multibit Single Cell Memory Element Having Tapered Contact”、发明人为Ovshinky；于1998年8月4日公开的美国专利No.5,789,277，题为“Method of Making Chalogenide[sic]Memory Device”、发明人为Zahorik等；于2000年11月21日公开的美国专利No.6,150,253，题为“Controllable Ovonic Phase-Change Semiconductor Memory Deviceand Methods of Fabricating the Same”、发明人为Doan等。
在以非常小的尺度制造这些装置、以及满足生产大尺寸存储装置时所需求的严格工艺变化时，则会遭遇到问题。较佳地提供种存储单元结构，其包括有小尺寸以及低重置电流，以及用以制造此等结构的方法，其可满足生产大尺寸存储装置时的严格制程变化规格。较佳地，提供一种工艺与结构，其兼容于同一集成电路的周边电路的制造工艺。
发明内容
本发明的一个目的是公开一种存储器件，其包括：存储元件阵列，其形成于半导体晶片上；字线平行阵列，其沿着第一方向延伸、并将每一存储元件连接至数据来源；以及位线平行阵列，其沿着第二方向延伸、并将每一存储元件连接至数据来源；第二方向与第一方向形成锐角。每一位线与每一存储元件之间的连结为相变化元素，此相变化元素由具有至少二固态相的存储材料所形成。
本发明的另一个目的是公开一种形成存储器件的方法，包括：提供存储元件阵列，其形成于半导体晶片上；形成字线平行阵列，其沿着第一方向延伸、并将每一存储元件连接至数据来源；形成位线平行阵列，其沿着一第二方向延伸、并将每一存储元件连接至数据来源，该第二方向与该第一方向形成锐角；以及其中每一该位线与每一该存储元件之间的连结为相变化元素，该相变化元素由具有至少二固态相的存储材料所形成。
附图说明
图1示出公知存储阵列的实例。
图2示出包括有相变化存储元件的存储阵列实施例的上视图。
图3示出图2的实施例的剖面图。
图4为剖面图，示出包括有相变化存储元件的存储阵列的替代实施例。
图5a、5b示出图1的实施例的操作方式。
图6示出图3与图4的实施例的一种实施配置。
主要元件符号说明
10             存储阵列
11             存储单元
11a，11b       存储元件
13             栓塞
14             衬底
15             通孔
16             漏极区域
17             源极区域
18             字线
19             源极栓塞
20             源极线
22             漏极电极
22a，22b       漏极电极
24             位线
26，26a，26b   相变化存储元件
27             区域
28             隔离材料
100            金属1
200             金属2
300             金属3
900             存储单元
900a，900b      存储元件
902             衬底
904             漏极
906             源极
908             共同源极线
910             字线
912，920        栓塞电极
914，918        电极
916             相变化材料导桥
920             栓塞电极
922             位线
具体实施方式
本发明参照图1-4详细描述关于使用相变化存储单元的存储阵列、以及用以制造这类存储单元与阵列的方法。可以了解的是，在本文所述及、以及在附图中所描绘的实施例，仅为说明目的。同时，本领域的技术人员能通过本发明的说明，而了解其他实施例与实施例的变化。本发明的其他变化均落入本发明的范围中，而本发明的范围则由权利要求书所界定。
通过了解制造相变化存储单元的先前技术，有助于了解本发明的内容。此领域目前的最新进展，公开于美国专利申请No.11/155,067，发明名称为“Thin Film Fuse Phase Change RAM and ManufacturingMethod”，申请日为2005年6月17日，受让人与本发明为同一人，该申请列为本申请的参考。图1示出了在该申请中所教示的基本存储单元结构900。需要注意的是，存储单元900包括存储元件900a与900b，每一此元件储存一位数据，如此领域中所周知。如图所示，此单元制造于衬底902上，其中活性(active)区域904、906利用公知技术而形成。共同源极线908提供电源，而字线910则作用为此MOS晶体管的栅极，此晶体管则包括了源极906与漏极904。栓塞电极912将漏极904连接至一对分离的电极914、918，此二电极通过相变化材料导桥916所连接。另一栓塞电极920将第二电极918连接至位线922。如此领域所周知，存储阵列通过排列许多这些单元而形成，且在一存储阵列中，字线910及位线922形成网状阵列，其具有二组彼此垂直的连接线。此外，还需注意的是本例所公开的结构包括了三层，其中晶体管位于第一金属层(包括电极914与918)与第二金属层(包括位线922)下。
本发明的一个实施例示出于图2(上视图)与图3(沿着A-A线的剖面图)。此实施例公开了存储阵列10，其包括存储单元11，而每一存储单元则包括存储元件11a与11b。每一存储元件包括活性区域16与17，其形成于衬底14上，而源极线20位于源极区域17上，且字线18位于源极区域17与漏极区域16之间。源极线与字线均是彼此平行的，如上所述。然而，位线24并不垂直于字线，而是与字线形成一角度B，并通过相变化存储元件26而连接至漏极电极22。
存储单元的实施例中，相变化存储元件26包括了相变化存储材料，相变化材料可包括硫属化物为基础的材料以及其它材料。硫属化物包括下列四元素中的任一种：氧(O)、硫(S)、硒(Se)、以及碲(Te)，形成元素周期表上第VI族的部分。硫属化物包括将硫属元素与更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其它物质如过渡金属等结合。硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素，例如锗(Ge)以及锡(Sn)。通常，硫属化合物合金包括下列元素中一个以上的化合物：锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已经被在技术文件中进行了描述，包括下列合金：镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中，可以尝试大范围的合金成分。此成分可以下列特征式表示：TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为，在沉积材料中所包含的平均碲浓度远低于70％，典型地低于60％，并在一般型态合金中的碲含量范围从最低23％至最高58％，且最佳的为介于48％至58％的碲含量。锗的浓度高于约5％，且其在材料中的平均范围从最低8％至最高30％，一般低于50％。最佳地，锗的浓度范围介于8％至40％。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比，其为所有组成元素总和为100％。(Ovshinky‘112专利，栏10～11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada，”Potential of Ge-Sb-TePhase-change Optical Disks for High-Data-Rate Recording”，SPIEv.3109，pp.28-37(1997))更一般地，过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金，可与锗/锑/碲结合以形成相变化合金，其包括有可编程的电阻性质。可使用的存储材料的特殊范例，如Ovshinsky‘112专利中栏11-13所述，其范例在此列入参考。
相变化材料能在此单元活性通道区域内依其位置顺序在材料为大致非晶状态的第一结构状态与大致结晶固体状态的第二结构状态之间切换。这些材料至少为双稳态的。“非晶”一词用以指称一相对较无次序的结构，其比单晶更无次序性，而带有可检测的特征，如比结晶态更高的电阻值。“结晶态”用以指称相对较有次序的结构，其比非晶态更有次序，因此包括有可检测的特征例如比非晶态更低的电阻值。典型地，相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其它受到非晶态与结晶态的改变而影响的材料特中包括，原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物，提供从非晶态至结晶态之间的灰色地带。此材料中的电性质也可能随之改变。
相变化合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出，较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大致非晶态。较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大致结晶态。在较短、较大幅度脉冲中的能量够大，因此足以破坏结晶结构的键结，同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下，可决定特别适用于特定相变化合金的适当脉冲量变曲线。在本文的后续部分，此相变化材料以GST代称，同时应该了解，也可使用其它类型的相变化材料。在本文中所描述的一种适用于PCRAM中的材料，为Ge2Sb2Te5。
可用于本发明其它实施例中的其它可编程的存储材料包括，掺杂N2的GST、GexSby、或其它以不同结晶态变化来决定电阻的物质；PrxCayMnO3、PrSrMnO、ZrOx、TiOx、NiOx、WOx、经掺杂的SrTiO3或其它利用电脉冲以改变电阻状态的材料；或其它使用电脉冲以改变电阻状态的物质；四氰代二甲基苯醌(7，7，8，8-tetracyanoquinodimethane，TCNQ)，甲烷富勒烯(methanofullerene 6)、6苯基C61丁酸甲酯(6-phenyl C61-butyric acidmethyl ester，PCBM)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何其它聚合物材料其包括有以电脉冲而控制的双稳态或多稳态电阻态。
图3为单一存储元件11a的剖面图，其显示了图2的实施例的进一步细节。在此，隔离材料28围绕并包覆所示的元素；可以了解的是，此材料也被使用在图1与图2所示的实施例中，但为了简洁起见而省略了。此绝缘材料较佳包括二氧化硅、聚酰亚胺、氮化硅、或其他介质填充材料。在实施例中，此填充层包括相当优良的热与电绝缘体，提供导桥所需的热与电绝缘效果。
为了简洁起见，此视图省略了活性区域，但字线18与源极线20、与源极栓塞19仍在图中。栓塞13连接至漏极，且此栓塞通过沉积在通孔15中的金属而连接至漏极电极22。位线24与漏极电极22位于同一层中，且这些元素由相变化元素26而连接彼此。此栓塞元素与源极线较佳由如钨等耐火金属所构成。其他适合的耐火金属包括钛、钼、铝、钽、铜、铂、铱、镧、镍、与钌，以及此等金属的氧化物与硅化物。举例而言，氮化钛、氧化钌、或氧化镍等材料，均为公知有效的耐火材料。字线较佳地由多晶硅或适合的硅化物，如此领域中所周知。
非常明显的是，在图2与图3中的结构，与图1中的结构有很大的差别。公知技术中，需要位线垂直至字线，因此位线与漏极电极必须位于不同层。在此，改变位线的方向则允许位线与漏极电极位于同一层，使得相变化元素可以直接连接电极与位线。因此，本发明的结构可以利用远少于公知技术的成本与时间制造。
一般将建立连接路径的半导体层称为“金属”层，而每一金属层则以各自的工艺步骤而制造。如图1所示的先前技术需要至少三层金属层，以制造相变化存储元件。图2与3的实施例则仅使用二层金属层就完成此结构，分别称为金属1与金属2(标号100与200)。在此结构中，可使用铜金属。例如铝、氮化钛、与含钨材料的金属化类型，也可使用于本实施例中。同时，也可使用如经掺杂的多晶硅等非金属导电材料。
在图4中所显示的替代实施例，在衬底14与电极/相变化元素/位线层之间，使用了额外的金属层，标示为金属3(标号300)。此制造方式可由于在晶片上需要形成相邻结构，或有需要将位线与字线如图所示地排列、以符合这些元素与同一晶片上的其他元件接合时所需要的高度。无论如何，此实施例所需要的工艺步骤，仍少于先前技术制造相同结构时所需要的工艺步骤数目，因为相同的公知结构会需要二层结构以形成漏极电极22、相变化元素26以及位线24，使得使用者必须采用四层金属层结构，而非三层结构。或者，在正常工艺后使用金属化工艺，并如上所述地形成相变化元素。
图3与图4中所示的实施例的操作方式，显示于图5a与5b中。如图所示，相变化元素26在漏极电极22与位线24之间形成电流路径。在存储单元的实施例中，此相变化元素的厚度(在此所谓的厚度，指图中垂直方向的尺寸)可以非常微小。此元素的厚度可以通过在漏极电极22、绝缘材料28、与位线24的上表面上、利用薄膜沉积技术沉积而形成。较佳地，存储单元的实施例具有相变化元素，其厚度约为50nm或以下。其他存储单元的实施例具有相变化元素，其厚度约为20nm或以下。在其他实施例中，相变化元素的厚度约为10nm或以下。可以了解的是，根据特定应用的需求，相变化元素的厚度甚至可利用如原子层沉积等薄膜沉积技术而少于10nm，只要此厚度足以使得相变化元素达成其作为存储元件的目标(具有至少二固态相，且可通过施加至第一与第二电极之间的电压或电流，而可逆地引发)即可。
在漏极电极22与位线24之间施加电压，会使得电流在相变化元素中流动，而够大的电流则会在此元素中产生焦耳热效应，尤其是在图5b中所示的区域27。电流幅度的选择，可在此元素中产生非晶态或结晶态，如上所解释。或者，可以施加低电流，以读取储存在相变化元素中的数据位。
如上所述，如元素11a与11b的二相变化存储元件，组成了相变化存储单元。图6示出了在上述实施例中，为了达成其效果所需的位线与电极排列方式。如图所示，漏极电极22a与22b电接触至存储单元电路，如箭头I所指示。较佳地，每一此电极直接位于活性区域上并接触至活性区域，如图3所示。二电极之间的一条线路与位线24成斜角的相对关系，而每一相变化元素26a、26b则将电极与位线结合，因此允许位线及电极可位于同一层中，如图所示。
虽然本发明已参照优选实施例进行了描述，应该了解的是，本发明并不受限于其详细描述内容。替换方式及修改方式已于先前描述中建议，并且其它替换方式及修改方式是本领域的技术人员可想到的。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件结合而达成与本发明实质上相同结果的，皆不脱离本发明的范围。因此，所有这些替换方式及修改方式意欲落在本发明所附的权利要求书及其等价物所界定的范围中。任何在前文中提及的专利申请以及公开文本，均列为本申请的参考。

Claims (20)

1.一种存储器件，包括：
存储元件阵列，其形成于半导体晶片上；
字线平行阵列，其沿着第一方向延伸、并将每一存储元件连接至数据来源；
位线平行阵列，其沿着第二方向延伸、并将每一存储元件连接至数据来源，该第二方向与该第一方向形成锐角；以及
其中每一该位线与每一该存储元件之间的连结为相变化元素，该相变化元素由具有至少二固态相的存储材料所形成。
2.如权利要求1所述的存储器件，其中
每一该存储元件包括漏极电极；
该相变化元素将位线在该漏极电极处连接至存储元件；以及
其中该位线、该相变化元素、以及该漏极电极均位于该半导体晶片的同一层。
3.如权利要求1所述的存储器件，其中该相变化元素由锗、锑、与碲所形成的组合物所构成。
4.如权利要求1所述的存储器件，其中该相变化元素包括由下列组中的两个以上材料所形成的组合物：锗(Ge)、锑(Sb)、碲(Te)、硒(Se)、铟(In)、钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)、银(Ag)、硫(S)、以及金(Au)。
5.如权利要求1所述的存储器件，其中该相变化元素位于该存储元件的该位线上。
6.如权利要求1所述的存储器件，其中该存储元件包括多个顺续形成的金属层，且其中该相变化元素位于所有这些金属层上。
7.如权利要求6所述的存储器件，其中包括有两层金属层。
8.如权利要求6所述的存储器件，其中包括有三层金属层。
9.如权利要求1所述的存储器件，其中该相变化元素的厚度介于10至50nm之间。
10.如权利要求1所述的存储器件，其中该相变化元素的厚度少于10nm。
11.一种形成存储器件的方法，包括：
提供存储元件阵列，其形成于半导体晶片上；
形成字线平行阵列，其沿着第一方向延伸、并将每一存储元件连接至数据来源；
形成位线平行阵列，其沿着一第二方向延伸、并将每一存储元件连接至数据来源，该第二方向与该第一方向形成锐角；以及
其中每一该位线与每一该存储元件之间的连结为相变化元素，该相变化元素由具有至少二固态相的存储材料所形成。
12.如权利要求11所述的方法，其中还包：
形成漏极电极于每一该存储元件内；
连接位线在该漏极电极处至存储元件于该相变化元素处；以及
其中该位线、该相变化元素、以及该漏极电极均位于该半导体晶片的同一层。
13.如权利要求11所述的方法，其中该相变化元素由锗、锑、与碲所形成的组合物所构成。
14.如权利要求11所述的方法，其中该相变化元素包括由下列组中的两个以上材料所形成的组合物：锗(Ge)、锑(Sb)、碲(Te)、硒(Se)、铟(In)、钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)、银(Ag)、硫(S)、以及金(Au)。
15.如权利要求11所述的方法，其中该相变化元素位于该位线上。
16.如权利要求11所述的方法，其中更包含：顺续形成多个金属层，且其中该相变化元素位于所有这些金属层上。
17.如权利要求16所述的方法，其中包括有两层金属层。
18.如权利要求16所述的方法，其中包括有三层金属层。
19.如权利要求11所述的方法，其中形成该相变化元素的厚度介于10至50nm之间。
20.如权利要求11所述的方法，其中形成该相变化元素的厚度少于10nm。
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