CN100485651C - 总线系统及操作总线系统的方法 - Google Patents
总线系统及操作总线系统的方法 Download PDFInfo
- Publication number
- CN100485651C CN100485651C CNB2004800148145A CN200480014814A CN100485651C CN 100485651 C CN100485651 C CN 100485651C CN B2004800148145 A CNB2004800148145 A CN B2004800148145A CN 200480014814 A CN200480014814 A CN 200480014814A CN 100485651 C CN100485651 C CN 100485651C
- Authority
- CN
- China
- Prior art keywords
- glitch
- bus
- circuit
- signal
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/40—Bus structure
- G06F13/4063—Device-to-bus coupling
- G06F13/4068—Electrical coupling
- G06F13/4072—Drivers or receivers
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Logic Circuits (AREA)
- Dc Digital Transmission (AREA)
- Cable Transmission Systems, Equalization Of Radio And Reduction Of Echo (AREA)
- Electronic Switches (AREA)
- Semiconductor Integrated Circuits (AREA)
- Aiming, Guidance, Guns With A Light Source, Armor, Camouflage, And Targets (AREA)
- Manipulation Of Pulses (AREA)
Abstract
Description
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP03101537.3 | 2003-05-27 | ||
EP03101537 | 2003-05-27 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1799037A CN1799037A (zh) | 2006-07-05 |
CN100485651C true CN100485651C (zh) | 2009-05-06 |
Family
ID=33483989
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2004800148145A Expired - Fee Related CN100485651C (zh) | 2003-05-27 | 2004-05-17 | 总线系统及操作总线系统的方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7439759B2 (zh) |
EP (1) | EP1631912B1 (zh) |
JP (1) | JP2007503789A (zh) |
CN (1) | CN100485651C (zh) |
AT (1) | ATE371898T1 (zh) |
DE (1) | DE602004008621T2 (zh) |
WO (1) | WO2004107190A1 (zh) |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7337419B2 (en) * | 2004-07-29 | 2008-02-26 | Stmicroelectronics, Inc. | Crosstalk noise reduction circuit and method |
JP2009124380A (ja) * | 2007-11-14 | 2009-06-04 | Seiko Epson Corp | ノイズリダクション回路、および電子機器 |
CN101470682B (zh) * | 2007-12-26 | 2011-06-08 | 北京中电华大电子设计有限责任公司 | Usb自调节驱动方法及电路 |
JP5353061B2 (ja) | 2008-05-27 | 2013-11-27 | 富士通株式会社 | 伝送遅延解析装置、伝送遅延解析プログラム、伝送遅延解析方法 |
CN101510859B (zh) * | 2009-03-20 | 2011-08-10 | 贵州航天电器股份有限公司 | 一种可进行总线切换的耦合器 |
US7834657B1 (en) * | 2010-01-12 | 2010-11-16 | Freescale Semiconductor, Inc. | Inverter circuit with compensation for threshold voltage variations |
US9541990B2 (en) * | 2015-04-21 | 2017-01-10 | Cypress Semiconductor Corporation | Asynchronous transceiver for on-vehicle electronic device |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3614208C2 (de) * | 1986-04-26 | 1995-05-11 | Asea Brown Boveri | Anordnung zum Anschluß einer Leistungsausgabeschaltung an eine Buskoppeleinrichtung |
US5565803A (en) * | 1995-05-31 | 1996-10-15 | Hughes Aircraft Company | Digital input threshold switching circuit |
US6084433A (en) * | 1998-04-03 | 2000-07-04 | Adaptec, Inc. | Integrated circuit SCSI input receiver having precision high speed input buffer with hysteresis |
JP3667690B2 (ja) * | 2001-12-19 | 2005-07-06 | エルピーダメモリ株式会社 | 出力バッファ回路及び半導体集積回路装置 |
-
2004
- 2004-05-17 EP EP04733412A patent/EP1631912B1/en not_active Expired - Lifetime
- 2004-05-17 AT AT04733412T patent/ATE371898T1/de not_active IP Right Cessation
- 2004-05-17 US US10/558,145 patent/US7439759B2/en not_active Expired - Fee Related
- 2004-05-17 WO PCT/IB2004/050718 patent/WO2004107190A1/en active IP Right Grant
- 2004-05-17 DE DE602004008621T patent/DE602004008621T2/de not_active Expired - Lifetime
- 2004-05-17 CN CNB2004800148145A patent/CN100485651C/zh not_active Expired - Fee Related
- 2004-05-17 JP JP2006530870A patent/JP2007503789A/ja not_active Withdrawn
Also Published As
Publication number | Publication date |
---|---|
WO2004107190A1 (en) | 2004-12-09 |
CN1799037A (zh) | 2006-07-05 |
ATE371898T1 (de) | 2007-09-15 |
JP2007503789A (ja) | 2007-02-22 |
EP1631912A1 (en) | 2006-03-08 |
US20060244481A1 (en) | 2006-11-02 |
DE602004008621T2 (de) | 2008-06-05 |
DE602004008621D1 (de) | 2007-10-11 |
US7439759B2 (en) | 2008-10-21 |
EP1631912B1 (en) | 2007-08-29 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6184737B1 (en) | Signal transmission with reduced ringing of signals | |
US7362622B2 (en) | System for determining a reference level and evaluating a signal on the basis of the reference level | |
KR101006090B1 (ko) | 반도체 메모리 장치 | |
US8040150B2 (en) | Impedance adjustment circuit | |
US20050068082A1 (en) | Method and apparatus for accommodating delay variations among multiple signals | |
US7940102B2 (en) | Edge rate control for I2C bus applications | |
CN100485651C (zh) | 总线系统及操作总线系统的方法 | |
US6184717B1 (en) | Digital signal transmitter and receiver using source based reference logic levels | |
CN101521492B (zh) | 阻抗匹配电路及其相关方法 | |
KR100656456B1 (ko) | 반도체 메모리의 온 다이 터미네이션 장치 및 방법 | |
EP1599816B1 (en) | Method and circuit arrangement for determining power supply noise | |
EP3474027B1 (en) | Method for identifying a fault at a device output and system therefor | |
US20120200159A1 (en) | Semiconductor device | |
CN100568376C (zh) | 用于抑制电压抖动的电路及其方法 | |
US20230080033A1 (en) | Methods and circuits for slew-rate calibration | |
US7557638B2 (en) | Circuit for suppressing voltage jitter and method thereof | |
US6294931B1 (en) | Systems and methods for maintaining board signal integrity | |
US7920007B2 (en) | Apparatus for outputting data of semiconductor integrated circuit | |
Rossi et al. | Risks for signal integrity in system in package and possible remedies | |
KR100233272B1 (ko) | 입력 버퍼의 그라운드 바운스 노이즈 억제 회로 | |
KR20090049696A (ko) | 기준 전압 생성 회로 및 이를 이용한 반도체 메모리 장치의내부 전압 생성 회로 | |
WO2019133460A1 (en) | Reducing noise effects in electrostatic discharge circuits | |
JP2002208969A (ja) | 半導体装置 | |
JPH10320268A (ja) | メモリ実装判別回路およびこれを用いたメモリコントロール回路 | |
US20060139083A1 (en) | Modifying clock signals output by an integrated circuit |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
ASS | Succession or assignment of patent right |
Owner name: NXP CO., LTD. Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V. Effective date: 20071026 |
|
C41 | Transfer of patent application or patent right or utility model | ||
TA01 | Transfer of patent application right |
Effective date of registration: 20071026 Address after: Holland Ian Deho Finn Applicant after: Koninkl Philips Electronics NV Address before: Holland Ian Deho Finn Applicant before: Koninklijke Philips Electronics N.V. |
|
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090506 Termination date: 20150517 |
|
EXPY | Termination of patent right or utility model |