CN100481417C - 半导体元件 - Google Patents
半导体元件 Download PDFInfo
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- CN100481417C CN100481417C CNB2004100841450A CN200410084145A CN100481417C CN 100481417 C CN100481417 C CN 100481417C CN B2004100841450 A CNB2004100841450 A CN B2004100841450A CN 200410084145 A CN200410084145 A CN 200410084145A CN 100481417 C CN100481417 C CN 100481417C
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Abstract
本发明是关于一种半导体元件,其包括具有一个顶端表面的一个半导体芯片、包括位在电极垫上的第一部分以及由第一部分延伸出来的第二部分的一个导电物件、以及封住半导体芯片的顶端表面以及导电物件的一个封装树脂。第二部分的顶端表面会被封装树脂暴露出来,而一部分的第二部分的顶端表面会自封装树脂的表面凹陷,一个外部终端会形成在第二部分的顶端表面上。
Description
技术领域
本发明涉及一种半导体元件,特别是涉及一种具有较高可靠度的半导体元件。
背景技术
当将一种半导体元件使用到一种可携带元件中时,半导体元件尺寸的缩小是有必要的,因此发展出一种称为芯片尺寸封装(以下简称CSP)的封装,此CSP在尺寸上会与一个半导体芯片相近,一种CSP称为晶圆级芯片尺寸封装(Wafer Level Chip Size Package:WCSP)或是(Wafer Level ChipScale Package:WCSP)。
在WCSP中使用到的一种外部终端的结构的说明可见参考资料1:日本专利第3217046号以及参考资料2:日本专利早期公开第2002-170427号。
在习知的WCSP中,一个柱状电极的顶端表面会与一个封装树脂的表面等平面,而在柱状电极的顶端表面上会形成一个外部终端,因此外部终端以一个小的面积与柱状电极相连,连接的可靠度可能会降低。
由此可见,上述现有的半导体元件仍存在有诸多的缺陷,而亟待加以进一步改进。为了解决现有的半导体元件的缺陷,相关厂商莫不费尽心思来谋求解决之道,但长久以来一直未见适用的设计被发展完成,此显然是相关业者急欲解决的问题。
有鉴于上述现有的半导体元件存在的缺陷,本发明人基于从事此类产品设计制造多年丰富的实务经验及专业知识,积极加以研究创新,以期创设一种新型结构的半导体元件,能够改进现有的半导体元件,使其更具有实用性。经过不断的研究、设计,并经反复试作样品及改进后,终于创设出确具实用价值的本发明。
发明内容
本发明的目的在于,克服现有的半导体元件存在的缺陷,而提供一种新型结构的半导体元件,所要解决的技术问题是使其具有较高可靠度,此半导体元件包括一半导体芯片,具有一顶端表面,其中该顶端表面包括一电极垫;一导电物件,包括位于该电极垫上的一第一部分以及由该第一部分延伸的一第二部分;以及一封装树脂,会封住该半导体芯片的该顶端表面以及该导电物件。第二部分的顶端表面会被封装树脂暴露出来,此第二部分的顶端表面的一部分会由封装树脂的表面凹陷,一个外部终端会形成在第二部分的该顶端表面上,从而更加适于实用,且具有产业上的利用价值。
上述说明仅是本发明技术方案的概述,为了能够更清楚了解本发明的技术手段,并可依照说明书的内容予以实施,以下以本发明的较佳实施例并配合附图详细说明如后。
本发明的具体实施方式由以下实施例及其附图详细给出。
附图说明
图1(A)是根据本发明第一实施例的一种半导体封装的剖面图。
图1(B)是根据本发明第一实施例的一种半导体元件的剖面图。
图2(A)至2(C)是根据第一实施例的半导体封装的制造步骤的剖面图。
图3(A)至3(C)是根据第一实施例的半导体封装的制造步骤的剖面图。
图4(A)至4(C)是根据第一实施例的半导体封装的制造步骤的剖面图。
图5是根据第一实施例的半导体封装的制造步骤的剖面图。
图6(A)与6(B)是根据第一实施例的另外实施例的半导体封装的制造步骤的剖面图。
图7(A)是根据本发明第二实施例的一种半导体封装的剖面图。
图7(B)是根据本发明第二实施例的一种半导体元件的剖面图。
图8(A)至8(C)是根据第二实施例的半导体封装的制造步骤的剖面图。
图9(A)至9(C)是根据第二实施例的半导体封装的制造步骤的剖面图。
图10(A)是根据本发明第三实施例的一种半导体封装的剖面图。
第10(B)图是根据本发明第三实施例的一种半导体元件的剖面图。
图11(A)至11(C)是根据第三实施例的半导体封装的制造步骤的剖面图。
图12(A)至12(C)是根据第三实施例的半导体封装的制造步骤的剖面图。
图13(A)至13(C)是根据第三实施例的半导体封装的制造步骤的剖面图。
图14是第三实施例的半导体封装的制作步骤剖面图。
图15是第三实施例的另一种实施例的半导体封装剖面图。
图16是本发明的另一种实施例的半导体封装剖面图。
图17是本发明的另一种实施例的半导体封装剖面图。
10、200、400、600、800:半导体封装(WCSP)
12:半导体芯片 12a:半导体芯片的顶端表面
14、53:电极垫 14a:电极垫的顶端表面
15:保护层 16:绝缘层
17:导电物件 18:第一部分
18a:第一表面 24、44、84:外部终端
20、201、70、701、80、801:柱状部分
20a、201a、701a、801a、80a:柱状部分的顶端表面
242、442、842:核心部分 244、444、844:金属层
246、2461、446、4461、8461:焊层
30、301:封装树脂 30a:封装树脂的表面
35:凹室 75、85、90:凹陷部分
35b、85b:凹室的侧边表面 50:主机板
100、700、900:半导体元件 18、91:重新分配部分
18a:重新分配部分的表面 40:半导体晶圆
241、840、841:焊球 37、77、89:助焊剂
42、72、83:罩幕图案 351、352:凹陷部分
441:焊料柱 87:焊料
86:上盖部分 95:树脂柱
85a:凹陷部分85的底部表面
92:重新分配部分91的第一部分
93:重新分配部分91的第二部分
96:柱状部分 97:第一柱状部分
98:第二柱状部分
具体实施方式
以下结合附图及较佳实施例,对依据本发明提出的半导体元件其具体结构、特征及其功效,详细说明如后。
请参阅图1(A)和图1(B)所示,是本发明第一实施例的一种半导体封装的剖面图和本发明第一实施例的一种半导体元件的剖面图。半导体封装10在一个半导体芯片12的顶端表面12a上会有复数个电极垫14,在本实施例中,半导体封装10为WCSP型,像是铝的电极垫14会电性连接到形成在半导体芯片12的顶端表面中的一个电路元件,一层像是二氧化硅或是氮化硅的保护层15以及一层像是聚亚醯胺(polyimide)的绝缘层16会形成在半导体芯片12的顶端表面12a上,电极垫14的顶端表面14a会被保护层15与绝缘层16暴露出来,绝缘层16具有一个吸收热应力的功能,电极垫14会电性连接到一个导电物件17,此导电物件17包括一个第一部分18与一个第二部分20,第一部分18会设置在电极垫14上,第一部分18包括一个与电极垫14的顶端表面14a接触的第一表面18a,以及一个设置在绝缘层16上并沿着半导体芯片12的顶端表面12a延伸的延伸部分,第一部分18一般称为重新分配部分,第二部分20会形成在第一部分18上并有一个顶端表面20a,此第二部分20也称为柱状部分20,重新分配部分18与柱状部分20由铜构成,半球形的外部终端24会形成在柱状部分20的顶端表面20a上,外部终端24的位置可以被重新分配部分18平移,外部终端24包括一个核心部分242、一个形成在核心部分242上的金属层244、以及一层形成在金属层244上的焊层246,像是环氧基树脂的封装树脂30会形成在半导体芯片12的顶端表面12a上。
在实施例中,柱状部分20的顶端表面20a的一部分会自封装树脂30的一个表面30a凹陷,在图1所示的半导体封装中,柱状部分的顶端表面20a的整个表面会由封装树脂30的表面30a凹陷,一个凹陷的凹室部分35会形成在封装树脂30中,也就是说外部终端24可能会与封装树脂30的一个侧边表面35b以及柱状部分20的顶端表面20a接触,结果外部终端24会牢牢的黏附住柱状部分20。
接着,说明包括一个主机板50的半导体元件100。
主机板50具有电极垫53如图1(B)所示,通过将外部终端24连接到电极垫53会将半导体封装10装设在主机板50上。
在本实施例中,外部终端24会准确的与柱状部分20接触,因此半导体封装10可以准确的与主机板50接触,结果半导体封装可以以较高的可靠度与主机板50连接。
请参阅图2(A)至图5说明一种半导体封装10的制造方法。
首先,提供一个包括半导体芯片12的半导体晶圆40,每一个半导体芯片12在其顶端表面12a上都有电极垫14。
接着,在晶圆40的整个表面上形成一层像是二氧化硅的保护层15以及一层像是聚亚醯胺的绝缘层16,如图2(A)所示。移除在电极垫14上的一部分保护层15以及绝缘层16。
接着,在绝缘层16以及暴露出来的电极垫14上用溅镀的方法形成一层铜层;然后通过图案化铜层来得到重新分配部分18,如图2(B)所示,重新分配部分18的表面18a会与电极垫14接触;之后在重新分配部分18上形成柱状部分201,如图2(C)所示,此柱状部分201有一个400μm的直径以及100μm的高度。
接着,通过涂布一层环氧树脂在晶圆40上形成一层封装树脂层301,如图3(A)所示,涂布是通过旋涂法来达成,接着研磨封装树脂层301暴露出柱状部分201的顶端表面201a,如图3(B)所示。
之后,在晶圆30上形成一个罩幕图案42,如图3(C)所示,柱状部分201的顶端表面201a会被罩幕图案42暴露出来,接着通过蚀刻一部分的柱状部分201会在封装树脂30的顶端表面中30a形成凹陷部分35对应于柱状部分201,如图4(A)所示,此蚀刻可以是一道使用像是氢氯酸或氢氟酸等高度酸性溶液的一道湿蚀刻方法。
凹陷凹室35的深度约为柱状部分201直径的2%至10%,在本实施例中,凹陷凹室35的深度为20μm。
之后,在凹陷部分35中填入助焊剂37,如图4(B)所示,此助焊剂37的功能就是会移除形成在柱状部分201上的氧化层并改善焊料对柱状部分201的附着力,此助焊剂37是通过顶针传递(pin transfer)法来进行。
接着,焊球241会通过助熔剂37被放置在凹陷部分35上,焊球241的直径为500μm,此焊球241包括塑料的核心部分242、形成在核心部分242上的金属层244、以及形成在金属层244上的焊层2461,这个多层的焊球241可以通过核心部分242吸收热应力,因此产生在焊层2461中的撞击声(clack)可以被抑制下来。
金属层244的材料是选自熔点在摄氏900度以上的材料,金属层244的材料可以选自金(Au)、银(Ag)、铜(Cu)、铂(Pt)、钯(Pd)、钴(Co)、镍(Ni)、以及铁(Fe)。
在本实施例中,焊层2461的熔点为摄氏350度,焊球241的材料可以是一种由锡(Sn)与铅(Pb)组成的合金构成,或是由一种由铟(In)、锡(Sn)与铅(Pb)组成的合金构成。
接着,外部终端24的形成是通过加热焊球241,如图5所示,在熔化以后,将剩余的助焊剂移除,用一个介于焊层2461与金属层244的熔点之间的一温度来加热焊球241。
在本实施例中,助焊剂37会在焊球241加热之前抓住焊球241,因此外部终端24可以很准确的放置在设定位置上。
因此,外部终端的一部分焊料会埋入凹陷凹室35中,外部终端24与柱状部分20之间的附着力可以得到改善。
在形成外部终端24以后,通过裁切成菱形片可以得到个别的WCSP 10,如图1所示。
接着,将说明把WCSP 10安置到主机板50上的方法。首先,让外部终端24与电极垫53接触藉以把WCSP 10放置在主机板50上。
然后,用一个介于焊层246与金属层244的熔点之间的一温度来加热焊球241,结果WCSP 10会通过填满柱状部分20与电极垫53之间的焊层246与主机板50电性相接,如图1(B)所示。
在本实施例中,柱状部分20的整个顶端表面20a会被移除以形成凹陷凹室35,在柱状部分20的顶端表面20a中会形成一个凹陷区域351,如图6(A)所示,抑或者在柱状部分20的一部分顶端表面20a内形成一个凹陷区域352,如图6(B)所示。
接着,参照图7(A)至图9(C)说明第二实施例的半导体封装200。
在本实施例中,外部终端44会形成在一个柱状部分70上,如图7(A)所示,此外部终端44具有一个柱状轮廓排列在柱状部分70延伸的方向中,一部分的外部终端44会埋入到形成在柱状部分70内的凹陷部分75中,外部终端44包括一个像是塑料的核心部分442、形成在核心部分442上的一层金属层444、以及形成在金属层444上的一层焊层446,此外部终端44是沙钟状,也就是说外部终端44的中间部分会比外部终端44的两端窄,沙钟状的外部终端44会减少在外部终端44中的应力。
在图8(A)至图9(C)中说明一种半导体封装200的制造方法。
半导体晶圆的提供步骤到树脂封装步骤的进行会与第一实施例相同,在封装步骤以后的半导体晶圆之处理如图8(A)所示,在此实施例中,柱状部分701的直径为500μm,而柱状部分701的高度为100μm。
接着,在封装树脂上形成一个罩幕图案72,如图8(B)所示,此罩幕图案72在柱状部分701上具有开口。
之后,在用湿蚀刻法在柱状部分701的顶端表面701a中形成凹陷部分75,如图8(C)所示,在此实施例中,凹陷部分75的深度为25μm。
凹陷部分75的功能有存贮助焊剂、支撑外部终端44以及改善柱状部分70与外部终端44之间的附着力,因此凹陷部分75的深度范围为柱状部分701的直径的2%至10%。
接着,将助焊剂77放到凹陷部分75,如图9(A)所示。
之后,焊料柱441会插入到凹陷部分75中,如图9(B)所示,焊料柱441的直径为400μm,而此焊料柱441的烧度为500μm。
此焊料柱441包括像是塑料的核心部分442、形成在核心部分442上的金属层444、以及形成在金属层444上的焊层4461。
接着,通过加热焊料柱441还形成外部终端44,将剩余的助焊剂37移除,如图9(C)所示,此加热步骤会在介于焊层4461的熔点以及金属层44的熔点之间的一温度下进行。
因此,在加热之前焊料柱441会被助焊剂37支撑住,外部终端44可以准确的形成,因此一部分的外部终端44会埋入凹陷部分75中,外部终端44与柱状部分70的连接是很坚固的。
在形成外部终端44以后,通过裁切成菱形片就可以得到个别的WCSP200,如图7(A)所示。
接着,会说明一种将WCSP 200装置到主机板50上的方法,首先让外部终端44与电极垫53接触藉以把WCSP 200放置在主机板50上。
然后,用一个介于焊层446与金属层444的熔点之间的一温度来加热外部终端44,结果WCSP 200会通过填满柱状部分70与电极垫53之间的焊层446与主机板50电性相接,如图7(B)所示。
接着,参考图10(A)至图15说明第三实施例的一种半导体封装400。
在本实施例中,焊料87会填入凹陷部分85,然后焊球840与填入的焊料87相接,焊球与填入的焊料87会构成外部终端84,如图10(A)所示。
因此,外部终端84会埋入凹陷部分85中,此外部终端84会与凹陷部分85的一个侧边表面85b以及凹陷部分85的底部表面85a相接触,结果外部终端84可以准确的与柱状部分80附着在一起。
接着,参照图11(A)至图15说明一种半导体封装400的制造方法。
半导体晶圆的提供步骤到树脂封装步骤的进行会与第一实施例相同,在封装步骤以后的半导体晶圆的处理如图11(A)所示,在此实施例中,柱状部分801的直径为500μm,而柱状部分801的高度为100μm。
接着,在封装树脂上形成一个罩幕图案82,如图11(B)所示,此罩幕图案82在柱状部分801的一部分顶端表面801a上具有开口。
之后,在用蚀刻柱状部分801暴露出来的部分以在柱状部分801的顶端表面801a中形成凹陷部分85,如图11(C)所示,在此实施例中,凹陷部分85的直径范围为柱状部分801的直径的10%至50%,凹陷部分85的深度范围为柱状部分801高度的20%至70%。
接着,凹陷部分85会被焊料87填满,如图12(A)所示,此焊料填充步骤是用电镀方法进行。
之后,利用电镀方法在凹陷部分85上形成一个比如为铜的上盖部分86,如图12(B)所示,然后在半导体晶圆40的表面上形成一层封装树脂301,如图12(C)所示。此封装树脂301会包覆上盖86,焊料87会被上盖部分86包覆,因此假如在封装步骤期间焊料87被加热的话,埋入的焊料87不会流出,之后通过研磨封装树脂301与上盖部分86会形成一层暴露出埋入的焊料87的顶端表面87a的一层封装层30,如图13(A)所示。
接着助焊剂89会供应到埋入的焊料87上,如图13(B)所示,此助焊剂89是用顶针传递法提供。
之后将焊球841放到助焊剂89上,如图13(C)所示,此焊球841包括核心部分842、形成在核心部分842上的金属层844、以及形成在金属层844上的焊层8461。焊球841的直径为500μm。
接着,通过加热焊球841还形成外部终端84,如图14所示,此加热步骤会在介于焊层8461的熔点以及金属层84的熔点之间的一温度下进行。在加热步骤中,埋入的焊料87以及焊球841的焊层8461会被熔化并焊接起来,结果一部分的外部终端84会埋入凹陷部分85中,接着移除剩余的助焊剂。
在形成外部终端84以后,通过裁切成菱形片就可以得到个别的WCSP400,如图10(A)所示。
WCSP 400会被装置到主机板50上,而得到一个半导体元件500,如图10(B)所示。
一个凹陷部分90会形成在埋入焊料87的周围,如图15所示,此凹陷部分90也会位在柱状部分80的顶端表面80a上,因此此凹陷部分会抓住助焊剂89,焊球841移动的机会就比较小。
另外,在第一实施例中提到的半导体封装10的重新分配部分18与柱状部分20可以变成一种树脂柱95与重新分配部分91的组合,如图16(A)所示。此重新分配部分91包括一个第一部分92位于该半导体芯片12的顶端表面12a上,以及一个第二部分93由第一部分92往树脂柱95的顶端表面延伸,再者当半导体封装600是被装置在主机板50上时,可以得到半导体元件700,如图16(B)所示。
此外,在第一实施例中提到的半导体封装10的重新分配部分18与柱状部分20可以变成一种柱状部分96形成在电极垫14上,如图17(A)所示。此柱状部分96包括一个第一柱状部分97以及一个形成在第一柱状部分97上的第二柱状部分98。再者,当当半导体封装800是被装置在主机板50上时,可以得到半导体元件900,如图17(B)所示。
以上所述,仅是本发明的较佳实施例而已,并非对本发明作任何形式上的限制,虽然本发明已以较佳实施例揭露如上,然而并非用以限定本发明,任何熟悉本专业的技术人员,在不脱离本发明技术方案范围内,当可利用上述揭示的技术内容作出些许更动或修饰为等同变化的等效实施例,但凡是未脱离本发明技术方案的内容,依据本发明的技术实质对以上实施例所作的任何简单修改、等同变化与修饰,均仍属于本发明技术方案的范围内。
Claims (13)
1、一种半导体元件,其特征在于该半导体元件包括:
半导体芯片,具有顶端表面,其中所述顶端表面包括电极垫;
导电物件,包括位于所述电极垫上的第一部分以及由所述第一部分延伸的第二部分,其中所述的导电物件的所述第二部分的顶端表面包括凹陷部分;
封装树脂,封住所述半导体芯片的所述顶端表面以及所述导电物件的一部分,其中所述导电物件的所述第二部分的所述顶端表面的至少一部分是暴露在位于所述封装树脂的上方表面中的凹室中;以及
外部终端,位于所述导电物件的所述第二部分的所述顶端表面上。
2、根据权利要求1所述的半导体元件,其特征在于其中所述的第二部分的所述顶端表面的全部是暴露在所述封装树脂的所述凹室中。
3、根据权利要求1所述的半导体元件,其特征在于其中所述的导电物件之所述第二部分包括柱状电极部分。
4、根据权利要求3所述的半导体元件,其特征在于其中所述的凹室中的所述第二部分的所述顶端表面之深度为所述柱状电极部分之直径的2%至10%。
5、根据权利要求3所述的半导体元件,其特征在于其中所述的凹室的直径为所述柱状电极部分的直径之10%至50%,而所述凹室之深度为所述柱状电极部分之高度的20%至70%。
6、根据权利要求1所述的半导体元件,其特征在于其中所述的外部终端为半球状。
7、根据权利要求1所述的半导体元件,其特征在于其中所述的外部终端为柱状。
8、根据权利要求7所述的半导体元件,其特征在于其中所述的柱状外部终端包括沙钟状的部分。
9、根据权利要求1所述的半导体元件,其特征在于其中所述的外部终端包括具有塑胶的核心部分,以及形成在所述核心部分上的焊层。
10、根据权利要求9所述的半导体元件,其特征在于还包括金属层,所述金属层设置在所述核心部分与所述焊层之间,且其中所述金属层的熔点会比所述焊层的熔点高。
11、根据权利要求1所述的半导体元件,其特征在于其中所述的导电物件的所述第一部分包括在所述半导体芯片上延伸的导线部分以及形成在所述导线部分上的柱状部分。
12、根据权利要求1所述的半导体元件,其特征在于其中所述的第二部分包括突出部分以及由所述第一部分延伸往所述突出部分的顶端表面的延伸部分。
13、一种半导体元件,其特征在于该半导体元件包括:
半导体芯片,具有顶端表面,其中所述顶端表面包括电极垫;
导电物件,包括位于所述电极垫上的第一部分以及由所述第一部分延伸的第二部分;
封装树脂,封住所述半导体芯片的所述顶端表面以及所述导电物件的一部分,其中所述封装树脂包括:凹室,所述凹室位于所述封装树脂的顶端表面中,且其中所述导电物件的所述第二部分的顶端表面的至少一部分会被所述封装树脂暴露出来,所述第二部分位于所述凹室中的一个深度,且定义有一凹陷区域;以及
外部终端,位于所述第二部分的所述顶端表面上。
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US7786588B2 (en) * | 2006-01-31 | 2010-08-31 | International Business Machines Corporation | Composite interconnect structure using injection molded solder technique |
US7719121B2 (en) * | 2006-10-17 | 2010-05-18 | Tessera, Inc. | Microelectronic packages and methods therefor |
JP4922891B2 (ja) * | 2006-11-08 | 2012-04-25 | 株式会社テラミクロス | 半導体装置およびその製造方法 |
TW200906260A (en) * | 2007-07-20 | 2009-02-01 | Siliconware Precision Industries Co Ltd | Circuit board structure and fabrication method thereof |
JP2009266979A (ja) * | 2008-04-24 | 2009-11-12 | Shinko Electric Ind Co Ltd | 半導体装置 |
KR101517598B1 (ko) * | 2008-07-21 | 2015-05-06 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR101096030B1 (ko) * | 2008-09-10 | 2011-12-19 | 주식회사 하이닉스반도체 | 반도체 칩 및 이를 이용한 반도체 패키지 |
US9627254B2 (en) * | 2009-07-02 | 2017-04-18 | Flipchip International, Llc | Method for building vertical pillar interconnect |
US9620469B2 (en) | 2013-11-18 | 2017-04-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Mechanisms for forming post-passivation interconnect structure |
US20130043573A1 (en) * | 2011-08-15 | 2013-02-21 | Advanced Analogic Technologies (Hong Kong) Limited | Solder Bump Bonding In Semiconductor Package Using Solder Balls Having High-Temperature Cores |
JP5922419B2 (ja) * | 2012-01-31 | 2016-05-24 | 株式会社東海理化電機製作所 | 無線通信システム |
US8884443B2 (en) * | 2012-07-05 | 2014-11-11 | Advanced Semiconductor Engineering, Inc. | Substrate for semiconductor package and process for manufacturing |
US9184143B2 (en) | 2013-12-05 | 2015-11-10 | Taiwan Semiconductor Manufacturing Company Ltd. | Semiconductor device with bump adjustment and manufacturing method thereof |
US20160343646A1 (en) * | 2015-05-21 | 2016-11-24 | Qualcomm Incorporated | High aspect ratio interconnect for wafer level package (wlp) and integrated circuit (ic) package |
US9960321B2 (en) * | 2015-07-01 | 2018-05-01 | Sensor Electronic Technology, Inc. | Multi-layered contact to semiconductor structure |
JP2017183571A (ja) | 2016-03-31 | 2017-10-05 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
JP7251951B2 (ja) * | 2018-11-13 | 2023-04-04 | 新光電気工業株式会社 | 半導体装置及び半導体装置の製造方法 |
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US6337445B1 (en) * | 1998-03-16 | 2002-01-08 | Texas Instruments Incorporated | Composite connection structure and method of manufacturing |
JP3217046B2 (ja) | 1998-12-03 | 2001-10-09 | 九州日本電気株式会社 | Bga型icパッケージ |
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US6869831B2 (en) * | 2001-09-14 | 2005-03-22 | Texas Instruments Incorporated | Adhesion by plasma conditioning of semiconductor chip surfaces |
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US7180185B2 (en) * | 2003-06-13 | 2007-02-20 | Oki Electric Industry Co., Ltd | Semiconductor device with connections for bump electrodes |
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