CN100444239C - Display apparatus and portable terminal - Google Patents

Abstract

The invention provides a displayer and a portable terminal which contains the displayer. The displayer comprises a display area unit formed by arranging each pixel with an electro-optic device in a matrix way, a vertical driving circuit used to select the pixels of the display area unit through a line unit, a horizontal driving circuit used to supply image signals to each pixel of the line selected by the vertical driving circuit and a supply voltage transformation circuit used to transform the single DC voltage into a plurality of DC voltages with different voltage values and then supply the plurality of DC voltages to the vertical driving circuit and the horizontal driving circuit, wherein, at least one of transistor circuits forming the power voltage transformation circuit is formed on the same substrate with the display area unit through applying the same technological process with the display area unit, thereby reducing the power consumption of the circuit and improving the power transformation efficiency.

Description

Display

The present patent application is that number of patent application is 01807038.8, the applying date is Dec 6 calendar year 2001, denomination of invention is divided an application for the patented claim of " translation circuit and control method thereof, display and portable terminal device ".

Technical field

The present invention relates to supply voltage translation circuit and control method thereof, display and portable terminal device, especially the supply voltage translation circuit and the control method thereof that relate to the charge pumps circuit have the display and the portable terminal device with display of supply voltage translation circuit as power circuit.

Background technology

Portable terminal device is such as portable phone and the nearest wide-scale distribution of PDA (personal digital assistance).One of factor that these portable terminal devices are propagated fast is the LCD of installing as the output display unit of portable terminal device.Reason mainly is, the characteristic of liquid crystal display device is, in order to drive LCD and not require a large amount of power, so it is a kind of display of low-power consumption.

Portable terminal device is used the single power supply voltage battery as power supply.On the other hand, in order by the signal wire in LCD information to be write each pixel of arranging with matrix-style, the logical block of horizontal drive circuit is used different DC voltage with analogue unit.Be used for selecting the DC voltage of the vertical drive circuit application of pixel than the higher absolute value of horizontal drive circuit by each row.Therefore, be installed in liquid crystal display applications supply voltage translation circuit in the portable terminal device or so-called DC-DC transducer (following say that becoming is the DD transducer), being used for single dc voltage conversion is the DC voltage of a plurality of different magnitudes of voltage.

Traditional DD converter applications inductor L in LCD.Yet, along with the reduction of the power consumption of portable terminal device recently and the size DD transducer of charge pumps type usually.Though charge-pump type DD transducer has low relatively current capacity, charge-pump type DD transducer does not require uses inductor as outer member.Therefore charge-pump type DD transducer has advantage: can contribution be arranged to reducing the portable terminal device size.

Fig. 1 illustrates the structure according to the charge-pump type DD transducer of the negative voltage generation type of the 1st conventional case.

At Fig. 1, Pch MOS transistor Qp101 and Nch MOS transistor Qn101 are connected in series to and are used to provide between the power supply and ground (GND) of single DC voltage VCC.Pch MOS transistor Qp101 and Nch MOS transistor Qn101 have the grid that is connected to common point, therefore form CMOS transducer 101.Pulse generation source 102 is added to the switching pulse of preset frequency the grid points of common connection of CMOS transducer 101.

The drain electrode points of common connection of CMOS transducer 101 (node A) is connected with the end of capacitor C101.The other end of capacitor C101 is connected with the anode of diode D101 and the negative electrode of diode D102.The plus earth of diode D101.Load capacitor C102 is connected between the anode and ground of diode D102.

In the DD transducer of the negative voltage generation type that therefore forms, supply voltage VCC multiply by-1, that is, negative dc voltage-VCC is cross-over connection load capacitor C102 and drawing substantially.

Fig. 2 illustrates the DD transformer configuration according to the charge-pump type of the voltage rising type of the 1st conventional case.The basic structure of the charge-pump type DD transducer of voltage rising type is identical with the charge-pump type DD transducer of negative voltage generation type.Say that exactly at Fig. 2, the different diode D101 that only are with the DD transducer of the negative voltage generation type of Fig. 1 of voltage rising type DD transducer are connected between the other end and power supply (VCC) of capacitor C101.In the DD transducer of voltage rising type, supply voltage VCC is twice, that is, DC voltage 2 * VCC is shunt load capacitor C102 and drawing substantially.

Yet, because form thus according to the charge type DD converter applications of the 1st conventional case pass through diode clamp, even so output voltage V out can not reach the magnitude of voltage that multiply by-1 or 2 supply voltage VCC under immunization with gD DNA vaccine, and move the twice of the threshold voltage vt h that is about diode, as seeing from the time diagram of Fig. 3 and Fig. 4.The circuit interior nodes A that the time diagram of Fig. 3 and Fig. 4 is illustrated in Fig. 1 and Fig. 2 respectively to the signal waveform A of C to C.

By charge-pump type DD transducer the problem of the 1st conventional case is improved according to Fig. 5 and the 2nd conventional case shown in Figure 6.At Fig. 5 and Fig. 6, represent with same reference numbers with Fig. 1 and Fig. 2 same section.Fig. 5 illustrates negative voltage generation type DD transducer, and Fig. 6 illustrates voltage rising type DD transducer.The basic structure of two DD transducers is identical.

Negative voltage generation type DD transducer is at first described.At Fig. 5, the other end of capacitor C101 is connected with the drain electrode of Nch MOS transistor Qn102 and the source electrode of Pch MOS transistor Qp102.Load capacitor C102 is connected between the source electrode and ground of Nch MOS transistor Qn102.The grounded drain of PchMOS transistor QP102.

The grid points of common connection of CMOS transducer 101 is connected with the end of capacitor C103.The other end of capacitor C103 is connected with the grid of Pch MOS transistor Qp102 with Nch MOS transistor Qn102 with the anode of diode D101.The plus earth of diode D101.

In the negative voltage generation type DD transducer that therefore forms, output voltage V out reaches the magnitude of voltage that multiply by-1 supply voltage VCC when non-loaded, as seeing from the time diagram of Fig. 7.

On the other hand, the difference of the DD transducer of the DD transducer of voltage rising type as shown in Figure 6 and negative voltage generation type shown in Figure 5 only is that switching transistor Qp103 and Qp103 have opposite conductivity type; And diode D101 is connected between the other end and power supply (VCC) of capacitor C101.In the DD transducer of voltage rising type, the twice of the supply voltage VCC when output voltage V out reaches non-loaded.

The circuit interior nodes A that the time diagram of Fig. 7 and the time diagram of Fig. 8 are illustrated in Fig. 5 and Fig. 6 respectively to the signal waveform A of C to C.

Yet, therefore the charge-pump type DD transducer clamp according to the 2nd conventional case that forms is the switching pulse voltage of switching transistor (MOS transistor Qn102 and Qp102) usefulness, that is, the voltage level of node D is clamped at by diode D101 threshold potential Vth and moves on the magnitude of voltage that is produced.Therefore, enough driving voltages may not offer switching transistor, especially PchMOS transistor Qp102.

Therefore, the transistor size for Pch MOS transistor Qp102 must be provided with more greatly.A class problem that transistor size increase generation increases such as circuit area and circuit capacity descends.In addition, when the pumping operation of saving power mode or icotype temporarily stopped, the clamp level of switching pulse voltage was along with the dutycycle of switching pulse changes and changes.This causes such as the circuit capacity class problem that descends.

When transistor threshold Vth is big and when threshold value Vth changes greatly, it is serious that the problems referred to above all become.When using thin film transistor (TFT) (TFT), when circuit formed on glass substrate, for example, this problem was one and requires careful consideration.The crowd knows that the amorphous silicon that is used to form thin film transistor (TFT) and polysilicon have than low crystallinity of monocrystalline silicon and low conductive mechanism controllability, and therefore the thin film transistor (TFT) that forms has big characteristic variations.

Therefore, the purpose of this invention is to provide the supply voltage translation circuit and the control method thereof that on the small size circuit scale, can access high current capacity, and have with display with the display and portable terminal device of supply voltage translation circuit as power circuit.

Summary of the invention

To achieve these goals, according to the present invention, provide and be applied in the supply voltage translation circuit that output unit has the charge pump circuit of switching device, and the supply voltage translation circuit comprises: be used for starting the 2nd clamp circuit that the controlling impulse voltage of constantly switching device being used is carried out the 1st clamp circuit of diode-clamp and is used for constantly controlling impulse voltage being clamped in the start-up course termination circuit power current potential.The supply voltage translation circuit is used as the power circuit of display.Comprise the display unit of the display of supply voltage translation circuit as portable terminal device.

In the supply voltage translation circuit that therefore forms, (moment of energized) the 1st clamp circuit carries out diode clamp to controlling impulse voltage starting constantly, and the magnitude of voltage of controlling impulse voltage is clamped at because diode threshold voltage moves on the current potential that is produced from circuit power voltage thus.Switching device in output unit moves according to gating pulse, therefore draws output voltage.Stop constantly in start-up course, the magnitude of voltage of controlling impulse voltage is clamped on the circuit power current potential.Therefore the pumping that takes place subsequently at charge pump circuit is in service, provides enough driving voltage to switching device.

The invention provides a kind of display, it comprises: by have the unit, the formed viewing area of each pixel of electro-optical device with the matrix-style arrangement; Be used for selecting the vertical drive circuit of the pixel of unit, above-mentioned viewing area by the delegation unit; Be used for picture signal is supplied with the horizontal drive circuit of each pixel of the row of selecting by above-mentioned vertical drive circuit; With being used for single dc voltage conversion is the DC voltage of a plurality of different magnitudes of voltage, subsequently a plurality of DC voltage is supplied with the supply voltage translation circuit of above-mentioned vertical drive circuit and above-mentioned horizontal drive circuit; Wherein, at least one transistor circuit that forms above-mentioned supply voltage translation circuit is to be formed on the same substrate of unit, above-mentioned viewing area by using the technological process identical with unit, above-mentioned viewing area.

According to another kind of display of the present invention, it comprises: the unit, viewing area forms by each pixel that has electro-optical device with the matrix-style arrangement; Be used for selecting the vertical drive circuit of above-mentioned viewing area unit pixel by the unit of delegation; Be used for picture signal is offered the horizontal drive circuit of each pixel of the row of selecting by above-mentioned vertical drive circuit; With being used for single dc voltage conversion is the DC voltage of a plurality of different magnitudes of voltage, subsequently a plurality of DC voltage are offered the power circuit of above-mentioned at least vertical drive circuit and above-mentioned horizontal drive circuit, reduce the power supply capacity of above-mentioned power circuit thus at power saving mode constantly.

According to another kind of display of the present invention, it comprises: the unit, viewing area that forms by each pixel that has electro-optical device with the matrix form arrangement; Be used for selecting the vertical drive circuit of the pixel of unit, above-mentioned viewing area by the delegation unit; Be used for picture signal is offered the horizontal drive circuit of each pixel of selecting by above-mentioned vertical drive circuit; With being used for single dc voltage conversion is the DC voltage of a plurality of different magnitudes of voltage, subsequently a plurality of DC voltage are supplied with the power circuit of above-mentioned at least vertical drive circuits and above-mentioned horizontal drive circuit, above-mentioned power circuit be according to unit, above-mentioned viewing area on the synchronous synchronizing signal operation of video signal displayed.

The present invention also provides a kind of portable terminal device, and it uses display as the output display unit, and aforementioned display device comprises: the unit, viewing area that forms by each pixel that has electro-optical device with the matrix form arrangement; Be used for selecting the vertical drive circuit of above-mentioned viewing area unit pixel by the delegation unit; Be used for picture signal is supplied with the horizontal drive circuit of each pixel of the row of selecting by above-mentioned vertical drive circuit; And to be used for single dc voltage conversion be the DC voltage of a plurality of different magnitudes of voltage, subsequently a plurality of DC voltage supplied with the supply voltage translation circuit of above-mentioned vertical drive circuit and above-mentioned horizontal drive circuit; Wherein, at least one transistor circuit that forms above-mentioned supply voltage translation circuit is formed on the same substrate of unit, above-mentioned viewing area by using the technological process identical with unit, above-mentioned viewing area.

According to another kind of portable terminal device of the present invention, it uses display as the output display unit, comprises: the unit, viewing area that forms by each pixel that has electro-optical device with the matrix form arrangement; Be used for selecting the vertical drive circuit of above-mentioned viewing area unit pixel by the delegation unit; Be used for picture signal is supplied with the horizontal drive circuit of each pixel of the row of selecting by above-mentioned vertical drive circuit; And to be used for single dc voltage conversion be a plurality of DC voltage with different magnitudes of voltage, subsequently a plurality of DC voltage are supplied with the power circuit of above-mentioned at least vertical drive circuit and above-mentioned horizontal drive circuit, reduced the power supply capacity of above-mentioned power circuit at power saving mode constantly.

According to another portable terminal device of the present invention, it uses display as the output display unit, comprises: the unit, viewing area that forms by each pixel that has electro-optical device with the matrix form arrangement; Be used for selecting the vertical drive circuit of above-mentioned viewing area unit pixel by the delegation unit; Be used for picture signal is supplied with the horizontal drive circuit of each pixel of the row of selecting by above-mentioned vertical drive circuit; And the DC voltage that is used for single DC voltage is converted to a plurality of different magnitudes of voltage, subsequently a plurality of dc voltage values are supplied with the power circuit of above-mentioned at least vertical drive circuit and above-mentioned horizontal drive circuit, above-mentioned power circuit is according to the synchronizing signal operation synchronous with video signal displayed on unit, above-mentioned viewing area.

Description of drawings

Fig. 1 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 1st conventional case.

Fig. 2 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 1st conventional case.

Fig. 3 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the negative voltage generation type of the 1st conventional case.

Fig. 4 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the voltage rising type of the 1st conventional case.

Fig. 5 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 2nd conventional case.

Fig. 6 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 2nd conventional case.

Fig. 7 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the negative voltage generation type of the 2nd conventional case.

Fig. 8 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the voltage rising type of the 2nd conventional case.

Fig. 9 is the circuit diagram that the charge-pump type DD transformer configuration of negative voltage generation type according to the embodiment of the present invention is shown.

Figure 10 is the time diagram that helps to illustrate the charge-pump type DD converter circuit operation of negative voltage generation type according to the embodiment of the present invention.

Figure 11 is the circuit diagram that the charge-pump type DD transformer configuration example of voltage rising type according to the embodiment of the present invention is shown.

Figure 12 is the time diagram of charge-pump type DD converter circuit operation that helps to illustrate the voltage rising type of embodiments of the present invention.

Figure 13 is the skeleton diagram that illustrates according to display device structure example of the present invention.

Figure 14 is the circuit diagram that liquid crystal display displays plot structure example is shown.

Figure 15 is the block scheme that illustrates according to the active matrix-type liquid crystal display device structure example of the 1st application examples.

Figure 16 is the general block diagram that the display of selectivity applied power save mode is shown.

Figure 17 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 1st application example.

Figure 18 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 1st application example.

Figure 19 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 2nd application example.

Figure 20 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the negative voltage generation type of the 2nd application example.

Figure 21 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 2nd application example.

Figure 22 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the voltage rising type of the 2nd application example.

Fig. 23 is the circuit diagrams that illustrate according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 3rd application example.

Figure 24 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the negative voltage generation type of the 3rd application example.

Figure 25 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 3rd application example.

Figure 26 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the voltage rising type of the 3rd practical example.

Figure 27 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 4th application example.

Figure 28 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the negative voltage generation type of the 4th application example.

Figure 29 is the circuit diagram that illustrates according to the voltage rising type charge-pump type DD transformer configuration of the 4th application example.

Figure 30 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the voltage rising type of the 4th application example.

Figure 31 is the block scheme that explanation offers switching pulse the example of the power circuit that is formed by charge-pump type DD transducer.

Figure 32 is the block scheme that explanation offers switching pulse another example of power circuit that is formed by charge-pump type DD transducer.

Figure 33 is the block scheme that illustrates according to the active matrix-type liquid crystal display device structure example of the 2nd application examples.

Figure 34 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 5th application example.

Figure 35 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the negative voltage generation type of the 5th application example.

Figure 36 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 5th application example.

Figure 37 is the time diagram that helps to illustrate according to the charge-pump type DD converter circuit operation of the voltage rising type of the 5th application example.

Figure 38 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 6th application example.

Figure 39 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 6th application example.

Figure 40 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the negative voltage generation type of the 7th application example.

Figure 41 is the circuit diagram that illustrates according to the charge-pump type DD transformer configuration of the voltage rising type of the 7th application example.

Figure 42 is the summary appearing diagram that illustrates according to portable phone structure of the present invention or portable terminal device.

Embodiment

Below with reference to accompanying drawing with depicted in greater detail preferred forms of the present invention.Fig. 9 is the circuit diagram that the charge-pump type DD transformer configuration example of negative voltage generation type is shown, and this transducer is a supply voltage transducer according to the embodiment of the present invention.

At Fig. 9, Ph MOS transistor Qp11 and Nch MOS transistor Qn11 are connected in series to and are used to provide between the power supply and ground (GND) of single direct supply voltage VCC.Pch MOS transistor Qp11 has the grid that is connected with common point with Nch MOS transistor Qn11, forms CMOS transducer 11 thus.Pulse produces the grid points of common connection that source 12 is added to the switching pulse of preset frequency in CMOS transducer 11.

The drain electrode points of common connection (Node B) of CMOS transducer 11 is connected with the end of capacitor C11.The other end of capacitor C11 is connected with on-off element, for example, and the source electrode of the drain electrode of Nch MOS transistor Qn12 and P MOS transistor Qp12.Load capacitor C12 is connected between the source electrode and ground of NchMOS transistor Qn12.

The grid points of common connection of CMOS transducer 11 is connected with the end of capacitor C13.The other end of capacitor C13 is connected with the anode of diode D11.Diode D11 has the negative electrode of a ground connection, and therefore forms the 1st clamp circuit 13.The other end of capacitor C13 also is connected with the grid of Pch MOS transistor Qp12 with Nch MOS transistor Qn12.The grounded drain of Pch MOS transistor Qp12.

Pch MOS transistor Qp13 is connected between the other end and ground of capacitor C13.The grid of Pch MOS transistor Qp13 is provided by the clamp pulse that pulse generation power supply 14 produces, and moves a level that is produced by level shift circuit 15.Pch MOS transistor Qp13, pulse generation power supply 14 and level shift circuit 15 form the 2nd clamp circuit 16, are used for the clamp of the switching pulse voltage of switching transistor (Nch MOS transistor Qn12 and Pch MOS transistor Qp12).

Level shift circuit 15 in the 2nd clamp circuit 16 use be input to the DD transducer supply voltage VCC as positive lateral circuit power supply, the output voltage V out of this circuit of drawing from cross-over connection load capacitor C12 is as the minus side circuit power.Current potential walking circuit 15 moves through the level of clamp pulse of clamp pulse level to the 2 amplitudes (VCC-Vout[V]) of the 1st amplitude that pulse generation power supply 14 takes place (VCC-0[V]), subsequently clamp pulse is offered the grid of Pch MOS transistor Qp13.Therefore, Pch MOS transistor Qp13 carries out the switch operation more reliably.

Below, the circuit operation of the charge-pump type DD transducer of the negative voltage generation type that forms is thus described with reference to the time diagram of Figure 10.The waveform A of time diagram is illustrated respectively in the signal waveform of the circuit interior nodes A of Fig. 9 to G to G.

When energized, (start constantly), diode D11 carries out the 1st " H " level clamping to the output potential of capacitor C13, promptly the current potential that is based upon the node D on the switching pulse that takes place by pulse generation power supply 12 from ground (GND) level, or minus side circuit power current potential is clamped to the current potential that produces by the threshold voltage vt h by diode D11 and moves resulting current potential.

When switching pulse was in " L " level (0V), Pch MOS transistor Qp11 and Qp12 were in conducting state, and so charging capacitor C11.In this case, Nch MOS transistor Qn11 place off state, and therefore the current potential of Node B is in the VCC current potential.Subsequently, when switching pulse was in " H " level (VCC), Nch MOS transistor Qn11 and Qn12 were in conducting state, and the current potential of Node B is in ground level (0V), so the current potential of node C is in-the VCC level.The current potential of node C is in fact by Nch MOS transistor Qn12, and become subsequently output potential Vout (=-VCC).

Next, when output voltage V out rises to a certain degree (when start-up course stops), the level shift circuit 15 that is used for clamp pulse brings into operation.When level shift circuit 15 brings into operation, level shift circuit 15 moves the amplitude VCC-0[V that is produced by pulse generation power supply 14] the clamp pulse level to amplitude VCC-Vout[V] the clamp pulse level, afterwards clamp pulse is added to the grid of Pch MOS transistor Qp13.

In this case, because " L " level of clamp pulse is output voltage V out, promptly-and VCC, so Pch MOS transistor Qp13 enters conducting state reliably.Therefore, the current potential of node D is to be clamped at earth potential (minus side circuit power current potential), rather than the level that is clamped to by being produced by the threshold voltage vt h of diode D11 from ground level moves resulting current potential.Therefore in service in pumping subsequently, especially can provide enough driving voltages for Pch MOS transistor Qp12.

As mentioned above, independently the stage is carried out clamp to gating pulse (switching pulse) voltage that is used for switching device (Nch MOS transistor Qn12 and Pch MOS transistor Qp12) that is provided in the output unit of the DD of charge pumps circuit transducer two, for example at first when starting this circuit, pass through the diode D11 clamp of the 1st clamp circuit 13, after stopping start-up course, pass through the 2nd clamp circuit 16 clamps subsequently.Therefore especially can offer the enough driving voltages of Pch MOS transistor Qp12.

So, because in Pch MOS transistor Qp12, obtain enough switching currents, thus may realize stable DC-DC conversion operation, and improve conversion efficiency.Especially, because obtain enough switching voltages, and need not increase the transistor size of Pch MOS transistor Qp12, so on the small size circuit scale, may realize having the DD conversion of high current capacity.When application has the transistor of high threshold Vth, for example during thin film transistor (TFT), its effect is especially big.

Figure 11 illustrates the structure example of voltage rising type charge-pump type DD transducer.The operation of the basic circuit structure of the charge-pump type DD transducer of voltage rising type and circuit is identical with the charge-pump type DD transducer of negative voltage generation type shown in Figure 9.

Say that accurately at Figure 11, switching transistor and the 2nd clamping transistor (MOS transistor Qp14, Qn14 and Qn13) have the MOS transistor Qn12 in the circuit with Fig. 9, the conductivity type that Qp12 and Qp13 are opposite; Diode D11 is connected between the other end and power supply (VCC) of capacitor C11; And the output voltage V out that level shift circuit 15 is configured to utilize this circuit utilizes ground level as the minus side circuit power as positive lateral circuit power supply.Figure 11 circuit structurally only is that with the difference of Fig. 9 circuit this on the one hand.

The operation of the basic circuit of the charge-pump type DD transducer of voltage rising type also is identical with negative voltage generation type DD transducer shown in Figure 9 exactly.The circuit operation of the charge-pump type DD transducer of voltage rising type only is with the difference of the DD transducer of negative voltage generation type shown in Figure 9: switching pulse voltage (controlling impulse voltage) is at first starting constantly by diode clamp, and stop constantly being clamped at VCC level (positive lateral circuit power supply potential), and drawn as output voltage V out for the magnitude of voltage 2 * VCC of supply voltage VCC twice in start-up course.The time diagram that Figure 12 is circuit interior nodes A that Figure 11 is shown respectively to the signal waveform A of G to G.

[the 1st application examples]

According to aforementioned embodiments, charge-pump type DD transducer (supply voltage translation circuit) be used as display-such as the active matrix-type liquid crystal display device by arranging pixel (this each pixel is used a liquid crystal cells as electro-optical device) to form with matrix-style-feed circuit.Figure 13 illustrates an example of display device structure.Following description will be with active matrix-type liquid crystal display device as an example.

At Figure 13, by the unit, viewing area 22 of arranging a large amount of pixels (each pixel comprises a liquid crystal cells with matrix-style) to form, a pair of upper and lower H driver (horizontal drive circuit) 23U and 23D and a V driver (vertical drive circuit) 24 are installed on transparent dielectric substrate, for example glass substrate 21.Peripheral circuit, also integrated on glass substrate 21 as power circuit 25 and power saving mode control circuit 26.

Glass substrate 21 is being left the 1st substrate a distance deposition the 2nd substrate face-to-face by being formed by the 1st substrate of arranging a large amount of image element circuits (each image element circuit comprises an active device (for example transistor) with matrix-style) to form.By encapsulated liquid crystals material between the 1st and the 2nd substrate, form LCDs.

Figure 14 illustrates unit, viewing area 22 concrete structures, one example.For the simplicity of figure, only get 3 row pixel arrangements (n-1 is capable capable to n+1) and 4 row (m-2 is listed as the m+1 row) and make example.The unit, viewing area 22 of Figure 14 has the vertical scan line of arranging with matrix form ..., 31n-1,31n, 31n+1, .... and data line (signal wire) ..., 32m-2,32m-1,32m, 32m+1 ..., on the intersection point of vertical scan line and data line, arrange unit pixel 33.

Each comprises a thin film transistor (TFT) (hereinafter referred to as TFT) 34 unit pixel 33, it is a pixel transistor, a liquid crystal cells 35, it is an electro-optical device, with a maintenance capacitor 36. in this case, liquid crystal cells 35 be illustrated on the TFT 34 pixel electrode (electrode) that forms and and the opposite electrode (another electrode) of the opposed formation of pixel electrode between the liquid crystal capacitance that produces.

TFT 34 has the vertical scan line of being connected to 31n-1,31n, 31n+1 ... grid and be connected to data line ..., 32m-2,32m-1,32m, the source electrode of 32m+1.The pixel electrode of liquid crystal cells 35 is connected to the drain electrode of TFT 34, and the opposite electrode of liquid crystal cells 35 connects concentric line 37.Keep electric capacity 36 to be connected between the drain electrode and concentric line 37 of TFT 34.Predetermined DC voltage is offered concentric line as common electric voltage Vcom.

Every vertical scan line ... 31n-1,31n, 31n+1 ... an end be connected to the output terminal of the corresponding line of V driver 24 shown in Figure 13.V driver 24 forms by for example shift register.V driver 24 sequentially produces the vertical strobe pulse synchronous with vertical transfer clock VCK (not shown), and provides vertical pulse to vertical scan line ..., 31n-1,31n, 31n+1 is for being forms vertical scanning thus.

Every odd data line ..., 32m-1, the end of 32m+1, for example in unit, viewing area 22, be connected to the output terminal of the respective column of H driver 23U shown in Figure 13, and every even data line ..., 32m-2,32m .... the other end be connected on the output terminal of H driver 23D respective column shown in Figure 13.Figure 15 illustrates the concrete example of H driver 23U and 23D structure.

As shown in figure 15, H driver 23U comprises a shift register 41U, and electrical equipment (data signal input circuit) 42U is latched in sampling, forms the latch cicuit 43U and the DA converter circuit 44U of row order.Shift register 41U and horizontal transfer clock HCK (not shown) are synchronously sequentially exported mobile pulse from each transition phase, realize horizontal scanning thus.Be the mobile pulse that response provides from shift register 41U, sampling latch cicuit 42U is with the dot sequency sampling and latch the input digital image data of predetermined bit.

Form the latch cicuit 43U of row order, latch the Digital Image Data that latchs with the dot sequency form by sampling latch cicuit 42U again, thus Digital Image Data is made the order of embarking on journey by single capable unit, and the single row of output digital image data simultaneously subsequently.DA converter circuit 44U has for example circuit structure of reference voltage selection type.DA converter circuit 44U is transformed to analog picture signal to the signal wire of the Digital Image Data of the latch cicuit 43U output that forms the row order, and subsequently analog picture signal is offered data line in the above-mentioned pixel region unit 22 ..., 32m-2,32m-1,32m, 32m+1.

Similar with top H driver 23U exactly, bottom H driver 23D has a shift register 41D, and sampling latch cicuit 42D forms row latch cicuit 43 and DA translation circuit 44D in proper order.Must be pointed out, be to constitute like this according to this routine LCD, makes that 22 upper and lower positions are arranged in the unit, viewing area for H driver 23U and 23D, and be not limited to this according to this routine LCD; H driver 23U and 23D may only be arranged on one of the upper and lower position, unit, viewing area 22.

As mentioned above, peripheral circuit such as power circuit 25 and power saving mode control circuit 26 also are integrated on the same glass substrate 21 of unit, viewing area 22.Under the situation of the LCD that constitutes like this, be that H driver 23U and 23D are arranged on the upper and lower position, unit, viewing area 22, for example wish peripheral circuit, be deposited on the side that H driver 23U and 23D are not installed such as the power circuit 25 and the power saving mode control circuit of framework region (unit, viewing area 22).

Reason is, because it is as described below, H driver 23U and 23D and V driver relatively have a large amount of elements, therefore usually has very big circuit area, by peripheral circuit-such as the control circuit of power circuit in framework region 25 and power saving mode-on the side that H driver 23U and 23D are not installed is installed, peripheral circuit, can be integrated on the same glass substrate 21 of unit, viewing area 22 such as power circuit 25 and power saving mode control circuit 26, and not reduce effective screen coefficient (the area ratios of the 22 pairs of glass substrate 21 in active zone unit).

Because on the side that is unkitted H driver 23U and 23D, have at the integrated V driver 24 of framework region one side according to the described active matrix-type liquid crystal display device of the 1st application examples, and peripheral circuit is integrated on the opposite side of side framework region such as power circuit 25 and power saving mode control circuit 26.

In this case, the charge-pump type DD transducer (supply voltage translation circuit) according to above-mentioned embodiment is used as power circuit 25.When integrated power supply circuit 25, because TFT 34 is as each pixel transistor of unit, viewing area 22, so TFT is also as the transistor that forms power circuit 25, promptly MOS transistor Qp11 to Qp13 and Qn11 to the transistor of Qn13 and formation level shift circuit 15 and the interior transistor of charge-pump type DD transducer shown in Figure 9.By producing the transistor circuit of using with unit, viewing area 22 identical process at least, make easier manufacturing of circuit and realization more at a low price.

Especially among some transistor circuits, diode D11, MOS transistor Qp12, Qp13, Qn12 and Qn13 and the transistor that forms the withstand voltage level shift circuit 15 of requirement height are except the CMOS transistor 11 of OV-VCC work, when forming, do not require device isolation by TFT.Therefore, diode D11, MOS transistor Qp12, Qp13, Qn12 and Qn13 and the transistor that forms level shift circuit 15 are produced with comparalive ease by using the technological process identical with unit, viewing area 22.In this case, other transistor circuit and like that can on the silicon on the substrate that separates with glass substrate 21, the generation.

Be accompanied by the improvement of nearest TFT performance and the reduction of TFT power consumption, make integrated TFT become and be more prone to.Therefore, by especially on the same glass substrate 21 of the pixel transistor of unit, viewing area 22, adopt the same technological process of TFT integrally to form power circuit 25 or transistor circuit at least, simplification as manufacturing process, may reduce price, and make display thinner and compacter as integrated result.

Must be noted that, in above-mentioned application examples, when forming on glass substrate 21 with unit, viewing area 22 integral body as power circuit 25 and power circuit 25 according to the charge-pump type DD of aforementioned embodiments, power circuit 25 not necessarily integrally forms with unit, viewing area 22.Say that exactly power circuit 25 may be with the outer circuits of doing LCD, and power circuit 25 may form on the substrate 21 that separates with glass substrate also.

Yet, can see that from foregoing description power circuit 25 integrally forms more beneficial with unit, viewing area 22 on same substrate.In addition, because the charge-pump type DD transducer according to aforementioned embodiments provides high current capacity on the small size circuit scale, especially when having the transistor (as TFT) of high threshold Vth, application produces very big effect, so, on same substrate, integrally form power circuit 25 with unit, viewing area 22, reduction is comprised the device price of LCD and makes that device is thinner, compacter a very big contribution.

In order integrally to reduce the power consumption of device, provide the power-saving model control circuit 26 of Figure 13 and Figure 15 to be used for selectivity power saving mode is set.As shown in figure 16, the external information of pattern according to the rules, 26 pairs of power circuits of power saving mode control circuit 25 are implemented the control of power saving modes.At Figure 16, for the simplification of figure, H driver 23U and 23D and V driver 24 in single square frame (actuator unit) jointly illustrate.

(the 1st application example of DD transducer)

Figure 17 illustrates the 1st application example according to the charge-pump type DD transducer of the negative voltage generation type of above-mentioned embodiment (consulting Fig. 9).Represent by same reference numbers in the part that Tu Nei is identical with Fig. 9.

The circuit structure of Figure 17 is identical with Fig. 9 exactly, newly inserted except two input AND circuit 17 in the level before the CMOS transducer 11 of Figure 17.Two input AND circuit 17 receive the switching pulse that taken place by pulse generation power supply 12 as an input, and as another input, in the moment of power saving mode, receive the mode select signal SEL that is in " L " level that provides from power saving mode control circuit 26 shown in Figure 16.

When the mode select signal SEL that power saving mode is in constantly " L " level offers thus the DD transducer according to the described negative voltage generation of the 1st application example type that forms, then AND circuit 17 stops to provide the switching pulse that taken place by pulse generation source 12 circuit in the DD transducer.This supspends the pumping operation of charge-pump type circuit.Therefore, reduced in the DD transducer electric current, thereby saved power by circuitry consumes.

As mentioned above, even by power saving mode is set, supspend clock and offer charge pump circuit, gating pulse (switching pulse) voltage that is used for switching device (Nch MOS transistor Qn12 and Pch MOS transistor Qp12) that then provides in output unit is starting the moment and start-up course termination back by clamp in two separate phases.Therefore stablized at the clamp level of node D.Even therefore the transient period of supplying with at clock/stopping also guaranteeing enough current capacities, and therefore may realize stable DC-DC conversion operation.

Figure 18 illustrates the structure according to the charge-pump type DD transducer of the described voltage rising of the 1st application example type.The basic circuit structure of the charge-pump type DD transducer of voltage rising type and circuit operation are identical with the charge-pump type DD transducer of negative voltage generation type, therefore will omit the circuit structure of voltage rising type charge-pump type DD transducer and the description of circuit operation.

(the 2nd application example of DD transducer)

Figure 19 is the circuit diagram that illustrates according to negative voltage generation type charge-pump type DD transducer the 2nd application example of aforementioned embodiments (seeing Fig. 9).In figure, represent by same reference numbers with Fig. 9 same section.Charge-pump type DD transducer according to the 2nd application example has the function of adjusting output potential.

Adjustment circuit according to the 2nd application example of Figure 19 comprises: the resistance R 1 and the R2 that are one another in series between circuit output end (node E) and power supply (VCC) or ground; Comparer 18 with (-) entry terminal of non-conversion (+) entry terminal of dividing point of resistance R of being connected to 1 and R2 and the conversion that provides by reference voltage (in this example for ground level); Be placed in the level before the CMOS transducer 11, and receive the switching pulse that takes place by pulse generation power supply 12 as an input, and receive comparer 18 relatively export AND circuit 19 as another input.

The structure of Figure 19 is that the structure with Fig. 9 is identical exactly, is new the interpolation except adjusting circuit.The charge pump operation of the circuit of Figure 19 is also identical with the circuit operation of Fig. 9 basically.Figure 20 is the time diagram that is used to help illustrate the operation of Figure 19 circuit.Waveform A in time diagram is illustrated respectively in node A in the circuit of Figure 19 to the signal waveform of H to H.

At the comparer 18 that forms thus output voltage V out and reference voltage (for example ground level) are compared according in the negative voltage generation type DD transducer of the 2nd application example.AND circuit 18 is used to adjust the circuit operation of output voltage V out to for example earth potential (0V) thus according to the pulse of comparative result control supply/shutdown switch.When output voltage V out becomes lower than target voltage, cause feedback, so that stop to provide switching pulse.Its result obtains target voltage by the decision of the intrinsic standoff ratio of resistance R 1 and R2 as output voltage V out.

Even the clock of supplying with charge pump is temporarily stopped by adjustment, but the gating pulse (switching pulse) that is used for switching device (NchMOS transistor Qn12 and Pch MOS transistor Qp12) two separate phases starting constantly and the start-up course termination after also by clamp, as mentioned above.Therefore, stablized at the clamp level of node D.So may realize stable adjustment operation.

Figure 21 illustrates the structure according to the voltage rising type charge-pump type DD transducer of the 2nd application example.Figure 22 is the time diagram that helps to illustrate the circuit operation of Figure 21.Be illustrated respectively in node A in Figure 21 circuit diagram to H to the signal waveform of H at the A of time diagram.

Comparer 18 in the DD transducer of voltage rising type compares output voltage V out and reference voltage (for example reference voltage Vref).AND circuit 18 realizes adjusting the circuit operation of output voltage V out to for example earth potential (0V) thus according to the supply of comparative result gauge tap pulse/stop.

Be higher than target voltage when output voltage V out becomes, then voltage rising type DD transducer causes feedback, so that stop to provide switching pulse.As a result of, obtain target voltage by the decision of the intrinsic standoff ratio of resistance R 1 and R2 as output voltage V out.The charge-pump type DD transducer that other circuit operation is negative voltage generation type basically is identical.

As DD transducer according to aforementioned embodiments (seeing Fig. 9), can be according to the DD transducer (supply voltage translation circuit) of the aforesaid the 1st and the 2nd application example as power circuit 25 according to the active matrix-type liquid crystal display device of the 1st application examples.

When power saving mode externally is prescribed, then aforementioned power is saved circuit 26 and is carried out the control that reduces the source current in H driver 23U and 23D and the V driver 24, and reduce the power supply capacity of power circuit 25, and carry out the power saving mode control on the power circuit 25.

The power saving mode of active matrix-type liquid crystal display device comprises part screen display mode, and wherein information only shows in the part district of unit, viewing area 22; And two level gray scale display modes, wherein to R (red), G (green) and B (orchid) look usefulness 1 bit of all kinds is made 8 kinds of looks and is shown, and this is opposite with normal pattern, for example every kind of R, G, B usefulness 6 bits of all kinds is made 260,000 colored demonstrations there, or the like.

Following of display mode of part screen at for example power saving mode partly shows information specific, for example on the top of display unit 22, and shows specific color at non-display area, and is for example white or black.At non-display area, the white or poison-pen letter breath in all time showings, therefore, for writing information need H driver 23U and 23D again.Therefore, by stopping H driver 23U and 23D, can reduce by one the power consumption that provides for H driver 23U and 23D is provided normally.

Therefore, the active matrix-type liquid crystal display device of power saving mode can reduce power consumption by the H driver 23U that stops non-display area and use and the operation of 23D, has also reduced the power consumption of power circuit 25 by the power supply capacity that reduces power circuit 25.Therefore as a whole, the power consumption of display can further reduce.In addition, the definitions of efficiency of DC-DC conversion is the power consumption/total power consumption of load, so the power consumption of total power consumption=load power consumption+this circuit, therefore by reducing the power consumption of this circuit, may improve conversion efficiency.

Concrete structure with power circuit 25 of power saving mode will be described following.Charge-pump type DD transducer according to aforementioned embodiments or its practical application can be used as power circuit 25.Yet, because power circuit 25 is not to characterize by its particular circuit configurations, so the selected conduct of the charge-pump type DD transducer basic circuit in this case of the 2nd conventional case shown in being equivalent in Fig. 5 and Fig. 6.In addition, as an example part screen display mode (partial mode) is set to power saving mode.

(the 3rd application example of DD transducer)

Figure 23 is the 3rd applied circuit diagram that the charge-pump type DD transducer of negative voltage generation type is shown.In the drawings, with Fig. 9 in identical part represent by same reference numbers.On circuit structure, only be do not have the 2nd clamp circuit 16 (consult 9 and Figure 11) according to the charge-pump type DD transducer of the 3rd application example with difference according to the charge-pump type DD transducer of aforementioned embodiments according to the DD transducer of the charge-pump type of the 3rd application example.

The partial mode control circuit 26 of Figure 23 ' corresponding to the power saving mode control circuit 26 in Figure 13 and Figure 15.The gating pulse of partial mode control circuit 26 ' output " H " level (high level) under mode standard.When power saving mode is set, promptly during the part screen display mode, partial mode control circuit 26 ' is during the non-display area cycle of screen, according to the outer gating pulse of exporting " L " level for information that is used for position, established part viewing area and line number.

Gating pulse is an input that is input to AND circuit 51.AND circuit 51 receives the time clock that is produced by pulse generation power supply 12 and imports as another.51 in AND circuit passes through time clock during the gating pulse cycle is provided.Be added to the grid points of common connection of CMOS transducer 11 as switching pulse by the time clock of AND circuit 51.

The charge-pump type supply voltage translation circuit according to the negative voltage generation type of the 3rd application example that forms thus will be described at the time diagram below with reference to Figure 24.Waveform A in time diagram is illustrated respectively in node A in the circuit of Figure 23 to the signal waveform of E to E.

At first, under mode standard, partial mode control circuit 26 ' output is in the gating pulse of " H " level.Therefore, pass through AND circuit 51, and supply with the grid points of common connection of CMOS transducer 11 subsequently as switching pulse by the time clock that pulse generation source 12 produces.In this case, the output potential of capacitor C13, that is, and according to the node D current potential of switching pulse by diode D11 clamp.

When switching pulse was in " L " level (0V), Pch MOS transistor Qp11 and Qp12 were in conducting state, and therefore capacitor C11 charging.In this case, Nch MOS transistor Qn11 is in off state, and therefore the current potential of Node B is in the VCC level.Subsequently, when switching pulse was in " H " level (VCC), Nch MOS transistor Qn11 and Nch MOS transistor Qn12 were in conducting state, and the current potential of Node B is in ground level (0V), so the current potential of node C is in-the VCC level.The current potential of node C is in fact by Nch MOS transistor Qn12, and become subsequently output voltage V out (=-VCC).

Next, when partial mode (part screen display mode) is set, partial mode control circuit 26 ' during the non-display area of screen, export the gating pulse that is in " L " level for information according to the outer of deciding section viewing area and line number.Subsequently, according to the gating pulse that is in " L " level, AND circuit 51 is forbidden being passed through by the time clock that pulse generation source 12 produces, and therefore, stops switching pulse being supplied with charge pump circuit.

Because switching pulse is not provided, so the pumping of charge pump circuit operation stops.In this case, the power supply capacity of charge pump circuit (current capacity), that is, the power supply capacity of this DD transducer is reduced to and is essentially zero.Specifically, the electric capacity of the power supply capacity of charge pump circuit and the frequency of switching pulse and capacitor C11 is inversely proportional to, and therefore stops to supply with switching pulse and makes the frequency that reduces switching pulse to zero, and therefore reduce power supply capacity to being essentially zero.

From reducing the viewpoint of power consumption, preferably be set the cycle of the power supply capacity (current capacity) that reduces this DD transducer as far as possible.Therefore wish the cycle that is provided with to maximum, for example be not the viewing area cycle 1/2 or more more.

As mentioned above, the power circuit 25 that forms by charge-pump type DD transducer stops the pumping operation of charge-pump type circuit, and therefore is reduced in the power supply capacity of the power circuit 25 during most of cycle of non-display area.Therefore can when the not power consumption of drive system in the non-display cycle, prevent that unnecessary conducting electric current from by charge pump circuit, can reduce the power consumption of power circuit 25 thus.In addition, the reduction of the power consumption of power circuit 25 has improved the DC-DC conversion effectively.

Figure 25 illustrates the structure according to the charge-pump type DD transducer of the voltage rising type of the 3rd application examples.The operation of the basic circuit structure of the DD transducer of voltage rising type and circuit is identical with negative voltage generation type DD transducer.

Say exactly, at Figure 25, switching transistor (MOS transistor Qp13 and Qn13) have with Figure 23 circuit in the MOS transistor Qn12 conduction type opposite with Qp12; And diode D11 is connected between the other end and power supply (VCC) of capacitor C11.The circuit of Figure 25 structurally only is that aspect with the difference of Figure 23 circuit.

The operation of the basic circuit of Figure 25 circuit is identical with Figure 23 circuit exactly also.The circuit operation of Figure 25 circuit does not exist together with Figure 23 circuit and only is: draw the magnitude of voltage 2 * VCC of supply voltage VCC twice as output voltage V out.The time diagram that Figure 26 is respectively Figure 25 circuit interior nodes A to the signal waveform A of E to E.

(the 4th application example of DD transducer)

Figure 27 is the circuit diagram that the 4th application example of negative voltage generation type charge-pump type DD transducer is shown.In the drawings, represent by same reference numbers with Figure 23 same section.The AND circuit 51 that replaces pulse generation source 12 and Figure 23 according to the DD transducer of the 4th application example by VCO (voltage-controlled oscillator) 52.Otherwise the structure of Figure 27 is identical with Figure 23 structure exactly.

Under mode standard, the control voltage that is in " H " level from partial mode control circuit 26 ' come for example is provided for VCO 52, and therefore according to the 1st time clock of control voltage generation preset frequency.Under partial mode, the control voltage that is in " L " level from partial mode control circuit 26 ' come for example is provided for VCO 52, and therefore produces 2nd time clock lower than the 1st clock frequency according to control voltage.The the 1st and the 2nd time clock offers the grid points of common connection of CMOS transducer 11 as switching pulse.

The circuit operation according to the charge-pump type supply voltage translation circuit of the negative voltage generation type of the 4th application example that forms thus will be described below with reference to the time diagram of Figure 28.Waveform A in time diagram is illustrated respectively in node A in Figure 27 circuit to the signal waveform of E to E.

At first, under mode standard, by providing from partial mode control circuit 26 ' next control voltage that is in " H " level, VCO 52 produces the 1st time clock of preset frequencies.The 1st time clock offers the grid common point of CMOS transducer 11 as switching pulse.In this case, the output voltage of capacitor C13, promptly according to the current potential of the node D of switching pulse by diode D11 clamp.

When switching pulse is in " L " level (0V), Pch MOS transistor Qp11 and Qp12 are in conducting state, and therefore capacitor C11 charging.In this case, Nch MOS transistor Qn11 is in off state.And therefore the current potential of Node B is in the VCC level.Subsequently, when switching pulse was in " H " level (VCC), then Nch MOS transistor Qn11 and NchMOS transistor Qn12 were in conducting state, and the current potential of Node B is in ground level (0V), so the current potential of node C is in the a-VCC level.In fact, the current potential of node C is by Nch MOS transistor Qn12, become subsequently output voltage V out (=-VCC).

Next, when partial mode (part screen display mode) was set, part viewing area and line number was outer for information according to the rules, and during the non-display area cycle of screen, partial mode control circuit 26 ' output is in the control voltage of " L " level.The control voltage of " L " level is provided by providing, and VCO 52 produces the 2nd time clock that frequency is lower than the 1st time clock of mode standard.The 2nd pulse offers the grid points of common connection of CMOS transducer 11 as switching pulse.

Afterwards, according to the operation logic same with mode standard, by the pumping operation realization DC-DC conversion of charge pump circuit according to the 2nd time clock, the negative voltage of-VCC is drawn as output voltage V out.In this case, because the frequency ratio standard pattern of switching pulse is low, so reduced the power supply capacity (current capacity) of this DD transducer.Specifically, as mentioned above, the power supply capacity of charge pump circuit and the frequency of switching pulse and electric capacity C11 electric capacity are inversely proportional to.Therefore, reduce the switching pulse frequency and just reduced power supply capacity.

As mentioned above, use VCO 52 as switching pulse generation source, make that switching pulse frequency ratio standard pattern is low, reduced the power supply capacity of power circuit 25 during most of cycle of non-display area thus by the power circuit 25 that charge-pump type DD transducer forms.Therefore make and prevented that in the less non-display cycle of drive system power consumption unnecessary conducting electric current from flowing through charge pump circuit, can reduce the power consumption of power circuit 25 thus.In addition, the power consumption of power circuit reduces and has improved conversion efficiency.

Figure 29 illustrates the structure of the voltage rising type charge-pump type DD transducer of the 4th application examples according to the present invention.The DD transducer of the operation of the basic structure of the DD transducer of voltage rising type and circuit and negative voltage generation type identical.

Specifically, at Figure 29, switching transistor (MOS transistor Qp13 and Qn13) have with Figure 27 circuit in the MOS transistor Qn12 conductivity type different with Qp12; And diode D11 is connected between the other end and power supply (VCC) of capacitor C11.Not existing together of the circuit of Figure 29 and the circuit structure of Figure 27 only is that aspect.

The operation of the basic circuit of Figure 29 circuit is accurate identical with Figure 27 also.The circuit operation of the circuit of Figure 29 only is with not the existing together of circuit of Figure 27: the magnitude of voltage 2 * VCC that draws supply voltage VCC twice as output voltage V out.Figure 30 is respectively at the circuit interior nodes A of Figure 29 time diagram to the signal waveform A of E to E.

As according to the circuit structure of the charge pump circuit of the basic circuit of the charge-pump type DD transducer of the 3rd and the 4th application example as mentioned above only as an example; The circuit structure of charge pump circuit allows various changes, is not limited to the foregoing circuit structure example.

Switching pulse supplied with the typical method on the power circuit 25 in the display with the power circuit 25 that forms by charge-pump type DD transducer, comprise following two kinds of methods, the first is used pierce circuit 27 (being equivalent to the pulse generation source 12 in Fig. 9), and use the time clock that produces by pierce circuit 27 switching pulse as power circuit 25, as description up to now, (see Figure 31).The DC voltage that DC-DC conversion by power circuit 25 obtains is added to actuator unit (23U, 23D and 24) and time control circuit 28.

Other method is to use the switching pulse (see Figure 32) of the horizontal transfer clock of one of various timing signals by time control circuit 28 generations as power circuit 25.The horizontal transfer clock is the clock signal for the circuit operation usefulness of horizontal driving system in the actuator unit (23U and 23D).

The advantage that the former of two methods has is: the clock signal that is used for power circuit 25 operations needn't be got from the outside, so even interrupt or like that at the master clock signal of power saving mode, power circuit 25 also moves with stationary mode.On the other hand, the sizableness when size of this method increase circuit area is made an appointment with assembling pierce circuit 25, and because can not obtain between the video signal displayed synchronously on the running clock of pierce circuit 25 and the unit, viewing area 22, therefore so this method may cause noise, and cause interference on the image or like that.

On the other hand, the advantage of back one method is, can reduce circuit area size sizableness when omitting pierce circuit 27 approximately, and reduce interference in the image and the analog that is caused by noise.Yet, because power circuit 25 needs operation at any time, therefore and the horizontal transfer clock can not stop, and can not stop etc. at power saving mode as the master clock signal on horizontal transfer clock basis, makes it can not realize effective low-power consumption mode thus.

[the 2nd application examples]

In view of the foregoing, display for example is the active matrix-type liquid crystal display device according to the 2nd application examples as described below.Figure 33 is the general block diagram that the active matrix-type liquid crystal display device structure example of the 2nd application examples according to the present invention is shown.In the drawings, represent by same reference numbers with Figure 15 same section.

Active matrix liquid crystal display according to the 2nd application examples is to constitute like this, make with unit, viewing area 12 on the synchronous synchronizing signal of video signal displayed, horizontal-drive signal HD for example, be used as the switching pulse of the power circuit 25 that forms by charge-pump type DD transducer, and make time control circuit 28 be integrated on the same glass substrate 21 of unit, viewing area 22.According to another structure of the active matrix-type liquid crystal display device of the 2nd application examples basically with identical according to the active matrix-type liquid crystal display device of the 1st application examples.

Time control circuit 28 produces various timing signals, with according to outer for horizontal-drive signal HD, vertical synchronizing signal VD and master clock signal MCK used by H driver 23U and 23D and V driver 24.For example, time control circuit 28 provides horizontal starting impulse HST and horizontal transfer clock HCK to H driver 23U and 23D, and provides vertical starting impulse VST and vertical transfer clock VCK to V driver 24.

Synchronizing signal, for example be used as a clock signal with the synchronous horizontal-drive signal of vision signal, it is basic that this clock signal is used as the switch operation of the power circuit 25 that is formed by charge-pump type DD transducer in the active matrix-type liquid crystal display device, and application clock signal provides following effect.The circuit of clocking needs not to be and provides again, because just used horizontal-drive signal HD by time control circuit 28 at first.Therefore, the circuit area that forms on glass substrate 21 can reduce.This causes littler, thinner LCD.

In addition, horizontal-drive signal HD is the result who carries out separated in synchronization by external sync splitter circuit (not shown), for example is that the vision signal from the unit, viewing area 22 is separated, thus horizontal-drive signal HD yes and vision signal is synchronous.Therefore can not take place owing to the asynchronous noise that causes between clock signal and vision signal, and therefore no longer occur because interference in image or the problem like that noise causes.Therefore, can provide LCD with splendid image quality.

Must be noted that horizontal-drive signal HD is used as the signal synchronous with vision signal in the 2nd application examples, but the 2nd application examples is not limited to this.The signal that vertical synchronizing signal VD, the frequency division by horizontal-drive signal HD or vertical synchronizing signal VD obtain or like thatly can be used to provide effect same as described above is because any of these signal is all synchronous with vision signal.Can still also may use from the outside the directly supply voltage of input as the supply voltage of time control circuit 28 by the DC voltage that power circuit 25 produces.

(the 5th application example of DD transducer)

Figure 34 is the circuit diagram of the 5th application example that the charge-pump type DD transducer of negative voltage generation type is shown.In this figure, represent by same reference numbers as same parts in Fig. 9.Horizontal-drive signal HD is for example as the charge-pump type DD transducer of clock signal supply according to the 5th application example.Horizontal synchronization letter signal HD is input to dutycycle translation circuit 53 and pulse generating circuit 54.

Dutycycle translation circuit 53 constitutes by frequency dividing circuit, for example horizontal-drive signal HD is transformed to dutycycle and is roughly 50% time pulse.The time clock that dutycycle conversion by dutycycle translation circuit 53 obtains is supplied with the grid points of common connection of CMOS transducer 11 as switching pulse, and also supplies with pulse generating circuit 54.Pulse generating circuit 54 together with Pch MOS transistor Qp13 and level shift circuit 15 form the 2nd clamp circuit 16 '.

Carry out the resulting time clock generation of dutycycle conversion clamp pulse at the 2nd clamp circuit 16 ' interior pulse generating circuit 54 according to horizontal-drive signal HD with by 53 couples of horizontal-drive signal HD of dutycycle translation circuit.Clamp pulse is added to the grid of Pch MOS transistor Qp13 through level shifter 15.

Form thus, be described below according to the circuit operation of the charge-pump type DD transducer of the negative voltage generation type of the 5th application example time diagram with reference to Figure 35.Waveform A in time diagram represents respectively that to G node A in the circuit diagram of Figure 34 is to the signal waveform of G.

When energized (starting constantly), diode D11 at first carries out " H " level clamping to the output potential of capacitor, promptly according to the resulting time clock of dutycycle conversion (switching pulse) by 53 couples of horizontal-drive signal HD of dutycycle translation circuit, the level that the current potential of node D is clamped to the threshold voltage vt h by diode D11 from earth potential moves the current potential that obtains or the current potential of minus side circuit power.

When switching pulse is in " L " level (0V), then Pch MOS transistor Qp11 and Qp12 are in conducting state, and therefore capacitor C11 charging.In this case, Nch MOS transistor Qn11 is in off state, and therefore the current potential of Node B is in the VCC level.Subsequently, when switching pulse is in " H " level (VCC), then Nch MOS transistor Qn11 and Nch MOS transistor Qn12 are in conducting state, and the current potential of Node B is in earth potential (0V), so the current potential of node C is in-the VCC level.In fact the current potential of node C is by Nch MOS transistor Qn12, subsequently, become output voltage V out (=-VCC).

Next, when output voltage V out rises to a certain degree (when start-up course stops), the level shift circuit 15 that is used for clamp pulse brings into operation.When level shifter 15 brings into operation, then level shifter to make the amplitude that is produced by pulse generating circuit 54 be that the clamp pulse level of VCC-0 (V) is moved to amplitude VCC-Vout[V] the clamp pulse level, afterwards, clamp pulse is added on the grid of Pch MOS transistor Qp13.

In this case, because " L " level of clamp pulse is output voltage V out, promptly,-VCC, so Pch MOS transistor Qp13 enters conducting state reliably, therefore the current potential of node D is clamped to ground level (minus side circuit power current potential), does not move the current potential that obtains and be not clamped to from the level of ground level by the threshold voltage vt h of diode D11.Therefore, in fact can provide enough driving voltages in that pumping subsequently is in service to Pch MOS transistor Qp12.

As mentioned above, play the signal of switching pulse benchmark effect by the power circuit 25 usage level synchronizing signal HD conduct of charge-pump type DD transducer formation, and provide duty cycle circuit 53 in its input stage, so dutycycle translation circuit 53 makes the dutycycle of switching pulse near 50%.Therefore, and compare when the switching pulse according to original appearance, may realize more effectively DC-DC conversion at horizontal-drive signal HD.

Figure 36 illustrates the charge-pump type DD transformer configuration according to the voltage rising type of the 5th application example.The operation of the basic structure of voltage rising type DD transducer and circuit is identical with the DD transducer of negative voltage generation type shown in Figure 34.

Specifically, at Figure 36, switching transistor and clamping transistor (MOS Qp14, Qn14 and Qn13) have with Figure 34 circuit in MOS transistor Qn12, the conductivity type that Qp12 and Qp13 are opposite; Diode D11 is connected between the other end and power supply (VCC) of capacitor C11; And level shift circuit 15 is so constituted, so that do positive lateral circuit power supply with the output voltage V out of this circuit, makes the minus side circuit supply with ground level.Difference on Figure 36 circuit and Figure 34 circuit structure only in that respect.

The operation of the basic circuit of the circuit of Figure 36 is identical with Figure 34 exactly also.The circuit operation of Figure 36 circuit only is with the difference of Figure 34 circuit: switching pulse voltage (controlling impulse voltage) is to start constantly at first by diode clamp, and stop constantly being clamped at VCC level (positive lateral circuit power supply potential) in start-up course, draw the magnitude of voltage 2 * VCC of supply voltage VCC twice as output voltage V out.Figure 36 is illustrated in the time diagram of Figure 35 circuit interior nodes A to the signal waveform A of G to G respectively.

Must be noted that the 5th application example plays the signal of switching pulse benchmark effect with horizontal-drive signal HD conduct, yet also can use vertical synchronizing signal VD.Though the frequency of horizontal-drive signal HD and vertical synchronizing signal VD is extremely different each other, can handle this difference on the frequency by the capacitance that changes capacitor C11 and C13.

The vertical moving clock VCK that timing control circuit 28 by Figure 33 produces also can be used as the clock signal that switch moves the benchmark effect.Because vertical moving clock VCK is the clock signal that produces according to horizontal-drive signal HD, and synchronous with vision signal, so vertical moving clock VCK makes it that effect identical with vertical signal VD with horizontal-drive signal HD may be provided.In addition, vertical moving clock VCK is that to have dutycycle be 50% clock signal inherently, and therefore vertical moving clock VCK has cancelled the demand of dutycycle translation circuit 53 is provided, and therefore the advantage that can correspondingly reduce circuit area is provided.

(the 6th application example of DD transducer)

Figure 38 is the circuit diagram that the 6th application example of negative voltage generation type charge-pump type DD transducer is shown.In the drawings, identical with Figure 34 part is represented by same reference numbers.Charge-pump type DD transducer according to the 6th application example is contained on the LCD of applied power save mode configuration selectively, so that reduce the power consumption of device as a whole, and application level synchronizing signal HD, for example, as the reference clock signal of switch operation usefulness.Must be noted that, as the situation of the 5th application example, vertical synchronizing signal VD, vertical moving clock VCK or the reference clock that may be used as the switch operation like that.

The structure of Figure 38 is identical with Figure 34 exactly, except dual input AND circuit 55 is newly to add in the level that is right after behind dutycycle translation circuit 53.Dual input AND circuit 55 receives the resulting time clock of dutycycle conversion by 53 couples of horizontal-drive signal HD of dutycycle translation circuit as an input, and the mode select signal SEL that is in " L " level that is received in power saving mode and provides constantly imports as another.

When to form thus according to the charge-pump type DD transducer of the 6th application example when power saving mode provides the mode select signal SEL that is in " L " level constantly the time, AND circuit 55 stops to provide time clock to arrive circuit inside according to horizontal-drive signal HD.This temporarily stops at the switch operation (the pumping operation of charge pump) in this DD transducer.Therefore reduce the current drain in the DD transducer, saved power thus.This is for direct input level synchronizing signal HD and the situation of the dutycycle of not conversion horizontal-drive signal HD also is so (to omit the dutycycle translation circuit).

Thus, even temporarily stop clock and provide by power saving mode is set, as previously discussed, gating pulse (switching pulse) voltage that is used for switching device (Nch MOS transistor Qn12 and Pch MOS transistor Qp12) that provides in output unit is starting constantly and start-up course is engraved in two separate phases by clamp when stopping.Stable at the clamp level of node D thus.Therefore, even carrying out the transition to clock and providing/stopping period also can guarantee enough current capacities, thereby can realize stable DC-DC conversion operation.

Figure 39 illustrates the charge-pump type DD transformer configuration according to the voltage rising type of the 6th application example.The operation of the basic circuit structure of voltage rising type DD transducer and circuit is same with the DD transducer of negative voltage generation type shown in Figure 38.

(the 7th application example of DD transducer)

Figure 40 is the charge-pump type DD converter circuit figure of the negative voltage generation type of the 7th application example.In figure, represent by same reference numbers with Figure 34 same section.Charge-pump type DD transducer according to the 7th application example is so constituted, so that not only application level synchronizing signal HD (or vertical synchronizing signal VD) but also use the reference clock signal of vertical moving clock VCK as switch operation usefulness.

The structure of Figure 40 is identical exactly with Figure 34's, except providing selector switch 56 to replace dutycycle translation circuit 53 in the input stage of horizontal-drive signal HD/ vertical transfer clock VCK.Selector switch 56 receives horizontal-drive signal HD and vertical transfer clock VCK imports as two, and selects input according to the space signal that provides in back-up period.Back-up period is to be carved into that other circuit-H shown in Figure 33 drives 23U and 23D, V driver 24 and timing control circuit 28-bring into operation the cycle constantly during from energized.

In charge-pump type DD transducer that form thus, according to the 7th application example, according to the space signal in the back-up period, selector switch 56 is selected horizontal-drive signal HD.In back-up period, H driver 23U and 23D, V driver 24 and timing control circuit 28 are by space signal control, so that make current drain as far as possible little.Reduce power consumption thus.

On the other hand, when selecting switch 56 to select horizontal-drive signal HD, power circuit 25, promptly this DD transducer carries out the switch operation of application level synchronizing signal HD as the operation clock, so that the DC voltage of generation scheduled voltage (in the 7th example-VCC and 2VCC; Yet-VCC and 2VCC are an example).DC voltage is provided to H driver 23U and 23D as supply voltage, V driver 24 and timing control circuit 28.

Therefore, timing control circuit 28 produces vertical transfer clock VCK according to horizontal-drive signal HD.After the some cycles of energized stops, promptly after back-up period, select vertical transfer clock VCK with substitution level synchronizing signal HD by selector switch 56.Use vertical transfer clock VCK subsequently as the operation clock, this DD transducer carries out the switch operation, so that continue DC-DC conversion operation.

Therefore, move to carry out switch as the operation clock, and application vertical transfer clock VCK moves to carry out switch as the operation clock after back-up period stops at energized moment application level synchronizing signal HD.Therefore, rise, also can have the effective DC-DC conversion operation of dutycycle 50%, obtain enough current capacities thus according to vertical transfer clock VCK even stop after-current consumption in back-up period.

Figure 41 illustrates the structure according to the charge-pump type DD transducer of the voltage rising type of the 7th application example.The operation of the basic circuit structure of the DD transducer of up voltage and circuit and negative voltage generation type DD transducer shown in Figure 40 is identical on the voltage.

By with following situation as an example, described the charge-pump type DD transducer according to the 7th application example in the above: charge pump circuit has used the structure of gating pulse (switching pulse) voltage of switching device (NchMOS transistor Qn12 and Pch MOS transistor Qp12) being carried out clamp in two separate phases, for example, at first constantly carry out the 1st clamp starting, stop the back by the 2nd clamp circuit 16 ' carry out clamp in start-up course subsequently by the 1st clamp circuit 13.Yet this circuit structure is an example; The circuit structure of charge pump circuit can have various structures, and is not limited to the above-mentioned example of circuit structure.

Make an example by the situation of getting charge pumps type DD transducer on the active matrix-type liquid crystal display device, described the 1st and the 2nd application examples, and the present invention is not limited to this.Charge-pump type DD transducer also is available for other Active Matrix Display similarly, for example uses the EL display of electroluminescence (EL) device as the electro-optical device of each pixel.

Display according to the present invention is suitable for as business automation equipment, as personal computer, word processor etc., television receiver, and the like demonstration, be particularly suitable for as portable terminal device, as portable phone PDA with and the main body demonstration of making less and compactlyer portable equipment.

Figure 42 is a portable terminal device, has for example used the structure summary outside drawing of portable phone of the present invention.

Have in the front side of device outer case 61 according to the loudspeaker unit 62 of sequence arrangement from the top to bottom output display unit 63, control module 64 and microphone unit 65 according to this routine portable phone.In the portable phone that forms thus, LCD is for example as output display unit 63.Be integrated on the same substrate of unit, viewing area by the power circuit that the charge-pump type DD transducer by aforementioned embodiments or its application example of the 1st to the 7th is formed, the active matrix-type liquid crystal display device that so forms is used as LCD.

Therefore, portable terminal device, application has been installed the active matrix-type liquid crystal display device of the power circuit that is formed by the charge-pump type DD transducer according to aforementioned embodiments or its 1st and the 2nd application example as output display unit 63 as portable phone.Therefore power circuit can obtain high current capacity at the small size circuit scale.Therefore, power circuit has advantage and is: to the power consumption that reduces portable terminal device and further make littler, compacter instrument and make contributions.

In addition, the active matrix-type liquid crystal display device that the power circuit that is formed by the charge-pump type DD transducer according to the 3rd and the 4th application example has been installed by application is as output display unit 63, can reduce the power consumption in the power circuit, and the power supply capacity of drive system when being reduced in power saving mode.Therefore can further be reduced in the power consumption of saving power mode.

In addition, the active matrix-type liquid crystal display device that the power circuit that is formed by the charge-pump type DD transducer according to the 5th～the 7th application example has been installed by application can be used as integral body and reduces size of devices and reduce noise as output display unit 63.Therefore can reduce the terminal body size, improve image quality.Especially when power saving mode, can reduce the power consumption of Circuits System.

Industrial applicability

According to the present invention, in using output unit, has the electricity of the charge pump circuit of switching device During the source voltage conversion circuit, the control impuls voltage that is used for switching device is by two at Startup time Utmost point pipe clamp, and stop constantly in start-up course, according to the voltage by switching device output The control impuls voltage clamp at the circuit power current potential. Therefore, can provide foot for switching device Enough driving voltages, and therefore carry out stable DC-DC conversion operation. Needn't increase device in addition The part size is so can realize supply voltage with high current capacity with the small size circuit scale Translation circuit.

Claims (4)

1. display is characterized by, and comprises:

By have the unit, the formed viewing area of each pixel of electro-optical device with the matrix-style arrangement;

Be used for selecting the vertical drive circuit of the pixel of unit, above-mentioned viewing area by the delegation unit;

Be used for picture signal is supplied with the horizontal drive circuit of each pixel of the row of selecting by above-mentioned vertical drive circuit; With

Be used for single dc voltage conversion is the DC voltage of a plurality of different magnitudes of voltage, subsequently a plurality of DC voltage are supplied with the supply voltage translation circuit of above-mentioned vertical drive circuit and above-mentioned horizontal drive circuit, described supply voltage translation circuit comprises at least one thin film transistor (TFT);

Wherein, above-mentioned at least one thin film transistor (TFT) that forms above-mentioned supply voltage translation circuit by use with the pixel that drives unit, described viewing area in the same process process of thin film transistor (TFT) of above-mentioned electro-optical device be formed on the same substrate of unit, above-mentioned viewing area.

2. according to the display of claim 1, wherein, above-mentioned supply voltage translation circuit is arranged on one of above-mentioned substrate side, and does not arrange above-mentioned horizontal drive circuit on this side.

3. according to the display of claim 1, wherein above-mentioned electro-optical device is a liquid crystal cells.

4. according to the display of claim 1, wherein above-mentioned electro-optical device is an electroluminescent device.

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