JP2003233361A - Power supply circuit of optoelectric device, circuit and method to drive the optoelectric device, the optoelectric device, voltage generating circuit and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To simplify a circuit constitution and to reduce the cost by reducing the number of parts which are to be externally mounted onto a semiconductor substrate due to the difficulty in integrally mounting the parts onto the substrate. <P>SOLUTION: A power supply circuit 400 supplies a potential which is used as a selection voltage for scanning lines of an optoelectric device having pixels corresponding to the crossing points of a plurality of scanning lines and a plurality of data lines. The circuit 400 is provided with a voltage generating circuit 420 which generates a positive polarity selection voltage VSP making an intermediate voltage VC of the voltage to be applied to the data lines as a reference, a capacitor Cp which charges the voltage VSP and inverting circuit 430 which inverts the polarity of the charged voltage using the voltage VC as a reference and outputs the voltage as a negative polarity selection voltage VSN. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit for an electro-optical device, a drive circuit for an electro-optical device, a method for driving an electro-optical device, an electro-optical device, a voltage generation circuit, and an electronic device in which the number of mounted components is reduced.

[0002]

2. Description of the Related Art Generally, an electro-optical device can be classified into various types according to a driving method, an electrode structure, etc., but a plurality of scanning electrodes (or scanning lines) are formed on one substrate, A plurality of data electrodes (or data lines) are formed on the other substrate, and an electro-optical material such as liquid crystal is further sandwiched between these two substrates to display by an electro-optical change based on the potential difference between the electrodes. It can be said that the type that performs is the simplest configuration.

In such an electro-optical device, the selection voltage required to drive the electro-optical material is usually about 2.
The voltage is about 0 to 25V, which is much higher than the input voltage 3 to 5V for operating the logic circuit. For this reason, it is general that a charge pump circuit is used as a power supply circuit of the electro-optical device and a single power supply voltage is boosted by the charge pump circuit to generate a selection voltage.

[0004]

However, in order to generate the selection voltage by using the charge pump circuit, generally, the number of capacitors corresponding to the boosting multiple is required. As described above, in the electro-optical device, since the step-up multiple of the selection voltage to be output with respect to the input voltage is high,
There is a drawback in that a large number of capacitors are required in the charge pump circuit.

Here, the capacitor used in the power supply circuit is
Since the capacitance is large and it is generally difficult to form it on a semiconductor substrate, it is almost always mounted as an external component without being integrated on an IC chip. Therefore, if a large number of capacitors are required, not only will the cost of the entire apparatus be high, but also the mounting process will be complicated and the production efficiency will be reduced.

The present invention has been made in view of the above-mentioned problems, and an object of the present invention is to reduce the number of parts mounted as external parts to simplify the mounting and reduce the cost. A power supply circuit of an electro-optical device capable of achieving
An object of the present invention is to provide a driving circuit for an electro-optical device, a driving method for an electro-optical device, an electro-optical device, a voltage generating circuit, and an electronic device using the electro-optical device.

[0007]

A power supply circuit for an electro-optical device according to the present invention selects a scanning line for an electro-optical device formed by intersecting a plurality of scanning lines and a plurality of data lines. A power supply circuit that supplies a potential used as a voltage, and a voltage generation circuit that generates either one of a positive polarity and a negative polarity selection voltage based on an intermediate value of a signal voltage applied to the data line, A power storage element that stores power based on one selected voltage generated by the voltage generation circuit, and the voltage stored in the power storage element is polarity-inverted with a predetermined value as a reference to select the positive polarity or the negative polarity. And an inverting circuit that outputs the other of the voltages,
The voltage generation circuit includes a switching element, and an inductor that stores electric power between the first and second input potentials when the switching element is turned on, and discharges the stored electric power when the switching element is turned off. And generating either one of the positive polarity and the negative polarity selection voltage with reference to the intermediate value of the signal voltage applied to the data line, based on the electric power emitted from the inductor. In the present invention, either the positive polarity or the negative polarity of the selection voltage to the scanning line is generated by the voltage generation circuit based on the power emitted from the inductor when the switching element is off. Therefore, it is relatively easy to set one selection voltage to a potential larger than the potential difference between the first and second input potentials. Further, in the present invention, the other selection voltage is
The voltage is generated by the inversion circuit, which stores the one selection voltage by the voltage generation circuit and then inverts the polarity.
Therefore, in the first invention, as compared with the conventional configuration, it is difficult to configure a component, particularly a semiconductor substrate, without increasing the power consumption, and therefore, an electricity storage element or the like mounted as an external component can be used. Parts are reduced. Therefore, according to the present invention, simplification of mounting and cost reduction can be achieved. Although a rechargeable secondary battery or the like can be applied as the electricity storage device in the present invention, a capacitor is considered to be suitable in consideration of miniaturization of parts. Further, in the present invention, the voltage generation circuit may further include a circuit that controls ON / OFF of the switching element according to a result of comparison between a voltage based on electric power emitted from the inductor and a target voltage. desirable. With this configuration, since the switching element is controlled to be turned on and off by the feedback of the output voltage, it is possible to stabilize either one of the selection voltages and the other selection voltage whose polarity is inverted regardless of the load. It becomes possible to make it. The switching element is preferably on / off controlled according to a pulse signal, and power generated by controlling the pulse width and the pulse interval can be adjusted.

Further, the power supply circuit of the electro-optical device according to the present invention is used as a selection voltage for the scanning lines for the electro-optical device formed by intersecting a plurality of scanning lines and a plurality of data lines. A power supply circuit for supplying a potential, the voltage generation circuit generating either one of a positive polarity and a negative polarity selection voltage with reference to an intermediate value of a signal voltage applied to the data line, and the voltage generation circuit. A power storage element that stores power based on one of the selected voltages generated by, and the voltage stored in the power storage element is polarity-inverted with a predetermined value as a reference, and either the positive polarity or the negative polarity selection voltage is selected. The voltage generation circuit includes a transformer for inputting a pulse signal to the primary side, and the positive or negative polarity selection is performed based on the secondary side output of the transformer. It is characterized by generating one of a voltage. In the present invention, either the positive polarity or the negative polarity of the selection voltage to the scanning line is generated based on the signal boosted by the transformer in the voltage generation circuit. Therefore, it is possible to relatively easily generate one of the high selection voltages. Further, since the power consumption due to the turning on / off of the switching element is suppressed, it is possible to reduce the power consumption. Further, in the present invention, the other selection voltage is generated by the inverting circuit by storing the one selection voltage by the voltage generation circuit and then inverting the polarity.
Since the configuration on the semiconductor substrate is difficult, the number of parts such as a power storage element mounted as an external part is reduced. Therefore, according to the present invention, simplification of mounting and cost reduction can be achieved. Here, in this invention,
It is preferable that the transformer is a piezoelectric transformer that generates mechanical vibrations by a voltage applied to the primary side and converts the mechanical vibrations into a voltage and outputs the voltage from the secondary side. As described above, when the piezoelectric transformer is used as the transformer, it contributes to downsizing, and it is possible to improve the voltage conversion efficiency by bringing the resonance frequency of mechanical vibration close to the mechanical natural vibration frequency. In addition, the voltage generation circuit according to the present invention further includes a circuit that controls the supply of the pulse signal to the primary side of the transformer according to the comparison result of the voltage based on the secondary side output of the transformer and the target voltage. Configuration is desirable. With such a configuration, the pulse signal is controlled by the feedback of the output voltage, so that either one of the selection voltages and the other selection voltage obtained by reversing the polarity of the selection voltage are stabilized regardless of the load. It becomes possible. In addition, the power generated by controlling the pulse width and pulse interval of the pulse signal can be adjusted.

In the above invention, it is preferable that the inverting circuit has a storage element whose voltage terminal to which an electrode is connected is switched based on a clock signal. According to this configuration, electricity can be stored and discharged efficiently. Further, in the above-mentioned invention, in the case where only a first region formed of a part of the plurality of scanning lines is set in a display state, and a second region formed of other scanning lines is set to a non-display state. When the scanning line belonging to the second area is selected, it is desirable to stop the polarity inversion by the inversion circuit or reduce the inversion frequency. According to this configuration, when the scanning line when no display is performed is selected, the polarity inversion by the inversion circuit is prohibited or the frequency of the inversion is reduced, so that the power is wasted accordingly. Will be prevented. Now, in order to achieve the above object, the present invention is a drive circuit of an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines,
With reference to an intermediate value of the signal voltage supplied to the data line, a power supply circuit that generates a positive polarity and a negative polarity selection voltage respectively, and a positive polarity and a negative polarity selection voltage generated by the power supply circuit, A scanning line driving circuit for applying a predetermined order to each of the scanning lines, wherein the power supply circuit selects either the positive polarity or the negative polarity selection voltage from the first and second input potentials. A voltage generation circuit that generates a voltage, a power storage element that stores power based on the selected voltage generated by the voltage generation circuit, and a voltage that is stored in the power storage element, the polarity of which is inverted with reference to a predetermined value, and the positive electrode And an inverting circuit that outputs the negative selection voltage as the other, and the voltage generation circuit includes a switching element, and when the switching element is turned on,
An inductor that stores electric power between the first and second input potentials and releases the stored electric power when the switching element is turned off is included. The positive polarity is based on the electric power emitted from the inductor. Alternatively, one of the negative selection voltages is generated. According to this configuration, the number of parts such as the power storage element is reduced for the same reason as in the first aspect of the invention, so that the mounting can be simplified and the cost can be reduced. Further, in order to achieve the above object, the present invention provides a drive circuit of an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, A power supply circuit for respectively generating positive and negative selection voltages with reference to an intermediate value of signal voltages supplied to the lines, and the positive and negative selection voltages generated by the power supply circuit for the scanning line. A scanning line drive circuit for applying a predetermined order to each of the above, and the power supply circuit generates either the positive polarity or the negative polarity selection voltage from the first and second input potentials. Voltage generating circuit, a power storage element that stores power based on the selected voltage generated by the voltage generation circuit, and the voltage stored in the power storage element, the polarity is inverted with reference to a predetermined value, the positive polarity or Negative polarity The voltage generation circuit includes a transformer for inputting a pulse signal to the primary side, and the positive or negative polarity is output based on the secondary side output of the transformer. It is characterized in that either one of the selection voltages is generated.
According to this configuration, for the same reason as in the second aspect,
Since the number of parts such as the power storage element is reduced, it is possible to simplify the mounting and reduce the cost.

On the other hand, in order to achieve the above object, the present invention provides a driving method of an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines. , While switching the switching element on and off,
When the switching element is turned on, electric power is stored in the inductor between the first and second input potentials, while the switching element is turned off,
The electric power stored in the inductor is discharged, one of the positive and negative selection voltages is generated with reference to the intermediate value of the signal voltage supplied to the data line, and the electricity is stored based on the selection voltage. The first process and the first
And a second step of reversing the polarity of the voltage stored in the step of (1) with a predetermined value as a reference and outputting the polarity as the other of the positive polarity or the negative polarity selection voltage. The selection voltage generated in the second process is applied to each of the scanning lines in a predetermined order. With this method, the first
For the same reason as in the invention, the number of parts such as the power storage element is reduced, so that the mounting can be simplified and the cost can be reduced. Further, in order to achieve the above object, the present invention is a driving method of an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, a pulse signal Input to the primary side of the transformer, and based on the secondary side output of the transformer, one of the positive and negative selection voltages is generated based on the intermediate value of the signal voltage supplied to the data line. Then
The first step of charging based on the selected voltage and the voltage charged in the first step are reversed in polarity based on a predetermined value, and either the positive polarity or the negative polarity selected voltage is applied to the other. And a second step of outputting the selection voltage generated in the first step and the second step, and the selection voltage generated in the first step and the second step is applied to each of the scanning lines in a predetermined order. Also by this method, the number of parts such as the storage element is reduced for the same reason as in the second aspect of the invention, so that the mounting can be simplified and the cost can be reduced. In addition, in order to achieve the above object, the present invention is an electro-optical device in which a pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines,
With reference to an intermediate value of the signal voltage supplied to the data line, a power supply circuit that generates a positive polarity and a negative polarity selection voltage respectively, and a positive polarity and a negative polarity selection voltage generated by the power supply circuit, A scanning line driving circuit for applying a predetermined order to each of the scanning lines, wherein the power supply circuit selects either the positive polarity or the negative polarity selection voltage from the first and second input potentials. A voltage generation circuit that generates a voltage, a power storage element that stores power based on the selected voltage generated by the voltage generation circuit, and a voltage that is stored in the power storage element, the polarity of which is inverted with reference to a predetermined value, and the positive electrode And an inverting circuit that outputs the negative selection voltage as the other, and the voltage generation circuit includes a switching element, and when the switching element is turned on,
An inductor that stores electric power between the first and second input potentials and releases the stored electric power when the switching element is turned off is included. The positive polarity is based on the electric power emitted from the inductor. Alternatively, one of the negative selection voltages is generated. Also with this configuration, the number of parts such as the power storage element is reduced for the same reason as in the first aspect of the invention, so that the mounting can be simplified and the cost can be reduced.

In order to achieve the above object, the present invention is an electro-optical device in which a pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and A power supply circuit that generates positive and negative selection voltages based on an intermediate value of the supplied signal voltage, and a positive and negative selection voltage generated by the power supply circuit for each of the scanning lines. A scanning line driving circuit for applying in a predetermined order to the power supply circuit,
A voltage generation circuit that generates either the positive polarity or the negative polarity selection voltage from the first and second input potentials; a storage element that stores electricity at the selection voltage generated by the voltage generation circuit; The voltage stored in the storage element is
A polarity inversion with a predetermined value as a reference, and an inverting circuit that outputs as either the positive polarity or the negative polarity selection voltage, the voltage generating circuit includes a transformer that inputs a pulse signal to the primary side, One of the positive polarity and the negative polarity selection voltage is generated based on the secondary side output of the transformer. Also with this configuration, the number of components such as the power storage element is reduced, so that the mounting can be simplified and the cost can be reduced.

Further, the electro-optical device of the present invention is an electro-optical device in which a pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, and a signal supplied to the data lines. A power supply circuit that generates positive and negative selection voltages based on an intermediate value of the voltage is provided, and the power supply circuit uses an inductor or a transformer that is driven according to a pulse signal, A voltage generation circuit that generates either the positive polarity or the negative polarity selection voltage from the input potential of 2; a storage element that stores power at the selection voltage generated by the voltage generation circuit; An inversion circuit that inverts the polarity of the selected voltage based on a predetermined value and outputs it as the other one of the positive polarity and the negative polarity selection voltage, and scans a part of the plurality of scanning lines. In the case where only the first area consisting of the scanning lines is in the display state and the second area consisting of the other scanning lines is not displayed, when the scanning line belonging to the second area is selected, the inversion circuit It is characterized in that the polarity reversal due to is stopped or the reversal frequency is reduced. Also with this configuration, the number of parts such as the power storage element is reduced for the same reason as above, so that the mounting can be simplified and the cost can be reduced. Further, according to this configuration, when the scanning line when no display is performed is selected, the polarity inversion by the inversion circuit is prohibited or the frequency of the inversion is reduced, so that the power is wasted accordingly. Will be prevented.

Further, in order to achieve the above object, an electronic apparatus according to the present invention is characterized in that the electro-optical device is used for a display section. Therefore, according to this electronic device, the number of externally attached parts is reduced, so that the mounting is simplified and the cost is reduced.

In the present invention, the above-described inductor and piezoelectric transformer are connected to a substrate of a liquid crystal panel, a flexible substrate having terminals on one end side connected to the substrate of the liquid crystal panel, or a terminal on the other side of the flexible substrate. The printed circuit board is placed on the printed circuit board. Conventionally, a large number of capacitors for a power supply circuit were mounted on this substrate, but the present invention can significantly reduce the number of components mounted on the substrate and downsize the device.

In the voltage generation circuit according to the present invention, the first potential and the second potential are supplied from the first potential and the second potential supplied from the first input line and the second input line. A third potential and a fourth potential which are symmetrical with respect to the intermediate potential between the potentials and whose potential difference from the intermediate potential is larger than the difference between the first potential and the second potential are generated. A voltage generating circuit, wherein the inductor receives the first potential and the second potential from the first input line and the second input line to generate electrical energy stored in the inductor. By connecting a first means for storing in a capacitor to generate as the third potential and a second capacitor between a first supply line and the first input line, the first supply Line and the third potential and the first input line output Second means for accumulating a voltage between the applied first potential and the second capacitor; and supplying the second capacitor with the second input line and the fourth potential. And a second supply line for connecting the second input line to the second input line, the second potential applied to the second input line separates the voltage stored in the second capacitor from the potential. And a third means for generating the fourth potential.

Further, the voltage generating circuit according to the present invention is configured such that the first potential and the second potential given from the first input line and the second input line are mutually referenced with the first potential as a reference. A voltage generation circuit that is symmetric and that generates a third potential and a fourth potential whose potential difference from the intermediate potential is greater than the difference between the first potential and the second potential; When the inductor receives the first potential and the second potential from the second input line and the second input line, the electrical energy accumulated in the inductor is stored in the first capacitor and the third potential is stored. And a second capacitor connected between the first supply line and one input line of the first input line or the third input line for receiving the fifth potential. To output the first output signal to the first supply line. Means for accumulating a voltage between the potential of the first input line and the potential input to the one input line in the second capacitor, and the second capacitor for storing the second capacitor in the first input line or the third input line. By connecting between one of the input lines and the second supply line, the voltage component stored in the second capacitor from the first potential or the fifth potential. And a third means for generating the fourth electric potential which is a remote electric potential.

The voltage generating circuit according to the present invention is the same as the voltage generating circuit described above, except that the operational amplifier or DC-DC is used.
It is characterized by including means for generating the fifth potential from the first potential and the second potential by using a converter.

Further, the voltage generation circuit according to the present invention is such that the ground potential and the second potential applied from the first input line and the second input line are between the ground potential and the second potential. A voltage generation circuit that is symmetrical to each other with respect to the potential and that generates a third potential and a fourth potential whose potential difference from the intermediate potential is larger than the difference between the ground potential and the second potential. Receiving the ground potential and the second potential from the first input line and the second input line in the inductor, the electrical energy accumulated in the inductor is stored in the first capacitor and stored in the third capacitor. And a second capacitor connected between the first supply line and the first input line to output the third potential output to the first supply line. And given to the first input line Means for storing a voltage between the ground potential and the second capacitor, and a second supply line for supplying the second capacitor with the second input line and the fourth potential. By connecting the second input line, the fourth potential, which is the potential separated from the voltage stored in the second capacitor from the second potential applied to the second input line, is generated. And means for doing so.

Further, the voltage generating circuit according to the present invention is symmetrical with respect to the ground potential and the second potential given from the first input line and the second input line, with the ground potential as a reference. A voltage generation circuit for generating a third potential and a fourth potential having a potential difference from the intermediate potential that is larger than a difference between the ground potential and the second potential, the first input line and the first potential A second means for receiving the ground potential and the second potential from the second input line in the inductor, storing the electric energy accumulated in the inductor in the first capacitor, and outputting it as the third potential; To the first supply line by connecting the capacitor between the first supply line and one of the first input line or one of the third input lines for receiving the fifth potential. The third potential being output and the Means for accumulating a voltage between the potential input to the other input line and the second capacitor, and inputting the second capacitor to one of the first input line and the third input line By connecting between a line and the second supply line, the fourth potential which is the potential separated from the ground potential or the fifth potential by the voltage stored in the second capacitor And means for generating an electric potential.

The power supply circuit of the electro-optical device according to the present invention is an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines. It is characterized by having the described voltage generation circuit.

The drive circuit of the electro-optical device according to the present invention is an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines. The above-mentioned voltage generation circuit is included, and the first potential and the second potential are supplied to the data line.

Further, in the drive circuit of the electro-optical device according to the present invention, in the drive circuit of the electro-optical device, the third potential and the fourth potential constitute a plurality of electro-optical devices. It is characterized in that it is used for driving a scan line.

The drive circuit of the electro-optical device according to the present invention is the drive circuit of the electro-optical device described above, wherein a region including a part of the plurality of scanning lines is set to a display state, and When the area including the scanning line is set to the non-display state, the switching operation of the second means and the third means is stopped during the period in which the scanning line in the non-display area is selected. Alternatively, it is characterized in that it has means for lowering the frequency of the signal for controlling the switching operation.

An electro-optical device according to the present invention is characterized by including the power supply circuit according to the present invention. An electro-optical device according to the present invention is characterized by including a drive circuit for the electro-optical device according to the present invention.

An electronic apparatus according to the present invention is characterized by including the electro-optical device according to the present invention.

[0026]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below with reference to the drawings.

First Embodiment First, before describing a power supply circuit according to an embodiment of the present invention, an electro-optical device to which this power supply circuit is applied will be described. FIG. 1 is a block diagram showing the electrical configuration of this electro-optical device.

As shown in this drawing, a plurality of data lines (segment electrodes) 212 are formed on the panel 100 so as to extend in the column (Y) direction, while a plurality of scanning lines (common electrodes) are formed. ) 312 is formed extending in the row (X) direction, and pixels 116 are formed corresponding to the respective intersections of the data lines 212 and the scanning lines 312. Furthermore, each pixel 116 includes an electro-optical material (liquid crystal layer) 118 and a thin film diode (Th
in Film Diode: hereinafter, simply referred to as TFD) 220. For convenience of description, the scanning line 31
The total number of 2 is 240, and the total number of data lines 212 is 32.
Although it is described as a matrix type display device having 240 rows × 320 columns, it is not limited to this.

Next, the structure of the panel 100 will be briefly described. FIG. 2 is a partially cutaway perspective view showing the structure. As shown in this figure, the panel 100 includes an element substrate 200 and a counter substrate 300 arranged to face the element substrate 200. Of these, on the facing surface of the element substrate 200,
Pixel electrodes 234 made of a transparent conductor such as ITO (Indium Tin Oxide) or a reflective metal such as an Al alloy or an Ag alloy are arranged in a matrix in the X direction and the Y direction. The 240 pixel electrodes 234 arranged in a row are arranged in one of the data lines 212 extending in the Y direction.
Each of them is connected to a book via a TFD 220.
Here, when viewed from the substrate side, the TFD 220 is made of tantalum simple substance, tantalum alloy, or the like.
Is composed of a branched first conductor 222, an insulator 224 obtained by anodizing the first conductor 222, and a second conductor 226 such as chromium. A body / conductor sandwich structure is adopted. Therefore, the TFD 220 has a diode switching characteristic in which the current-voltage characteristic is non-linear in both positive and negative directions.

On the other hand, on the facing surface of the facing substrate 300, the scanning lines 312 are formed so as to extend in the X direction and face the pixel electrodes 234. The element substrate 200 and the counter substrate 300 configured as described above maintain a constant gap by a sealant and a spacer (both not shown), and in this closed space, for example, TN (Twisted Nematic) type, bistable type such as ferroelectric type, polymer dispersed type, vertical alignment type without twist, horizontal alignment type, etc. are enclosed, whereby the liquid crystal layer 118 in FIG. 1 is formed. The Rukoto. That is, the liquid crystal layer 118 includes the data line 212 and the scan line 312.
At a point of intersection with, the scanning line 312, which is an electrode, the pixel electrode 234, and the liquid crystal 105 sandwiched between the two electrodes.

Now, returning to the description of FIG. 1, the scanning line driving circuit 350 includes the power supply circuit 400 for each scanning line 312.
The voltage generated by is selected in a predetermined order and the scanning signals Y1 to Y240 are supplied. The data line driving circuit 250 also supplies the power supply circuit for each data line 212 in accordance with the display content of the pixel intersecting the selected scanning line 312 and the polarity of the selection voltage applied to the scanning line 312. Select the voltage generated by 400 to select the data signal X
1 to X320 are supplied.

Here, j (j
Is an integer that satisfies 1 ≦ j ≦ 240) -th scanning line 312
FIG. 3 shows an example of waveforms of the scanning signal Yj applied to the first data line 212 and the data signal Xi applied to the i-th (i is an integer satisfying 1 ≦ i ≦ 320) data line 212 counted from the left in FIG. Show.

In this figure, the voltages VSP and VSN are selection voltages, and the voltages VHP and VHN are non-selection voltages. In addition, the non-selection voltages VHP and VHN
Are also used as the high potential side voltage and the low potential side voltage of the data signal, respectively. Then, the selection voltages VSP and VSN
Is the intermediate voltage V of the high potential side and low potential side voltages of the data signal.
It is symmetrical with respect to C. In this way, with reference to the intermediate voltage VC of the data signal, the selection voltages VSP, VS
Giving symmetry to N is a premise for AC driving the liquid crystal layer 118. In the TFD 220, there is an asymmetry of the current-voltage characteristic with respect to the polarity of the applied voltage, and in order to compensate for it, the intermediate voltage VC of the data signal
On the other hand, the selection voltages VSP and VSN may be asymmetrical. However, with regard to the polarity, hereinafter, with reference to the intermediate voltage VC, the voltage on the high potential side is the positive polarity and the voltage on the low potential side is the positive potential. Is referred to as a negative polarity.

Now, as shown in FIG. 3, the scanning signal Yj is, first, in the second half period (1 / 2H) obtained by dividing one horizontal scanning period (1H) in which the scanning line 312 is selected into two. It becomes the selection voltage VSP, then secondly becomes the non-selection voltage VHP, and thirdly, one vertical scanning period (1F) has elapsed since the selection voltage VSP was applied, and then the scanning line 3 concerned.
When 12 is selected again, in the latter half period (1 / 2H) of the horizontal scanning period, this time becomes the selection voltage VSN, and then the fourth becomes the non-selection voltage VHN. is there. Note that such a scanning signal has a relationship in which all the scanning lines 312 are sequentially shifted and selected one by one in the one horizontal scanning period (1H) in one vertical scanning period (1F). Become.

The data signal Xi is as follows, corresponding to the scanning signal Yj. That is, when the display content of the pixel 116 corresponding to the intersection position of the i-th data line 212 and the j-th scanning line 312 is ON display (black display in normally white mode or white display in normally black mode) If the selection voltage applied to the scanning line 312 is positive in the latter half of the horizontal scanning period in which the j-th scanning line 312 is selected, the data signal Xi is ), The voltage becomes the high-potential side voltage VHP in the first half period of the horizontal scanning period (1H), and in the latter half period thereof, the low-potential side voltage V having the opposite polarity to the applied selection voltage.
HN, while displaying the same, and j
If the selection voltage applied to the scanning line 312 has a negative polarity in the second half of the horizontal scanning period in which the second scanning line 312 is selected, the data signal Xi is the horizontal scanning signal as shown in FIG. In the first half of the period (1H), the voltage VHN is on the low potential side, and in the latter half of the period,
The voltage VHP on the high potential side having the opposite polarity to the applied selection voltage
Becomes

Further, the display content of the pixel corresponding to the intersection position of the i-th data line 212 and the j-th scanning line 312 is OFF display (white display in normally white mode or black display in normally black mode). In some cases, and when the selection voltage applied to the scanning line 312 has a positive polarity in the latter half period of the horizontal scanning period in which the j-th scanning line 312 is selected, the data signal Xi
As shown in FIG. 3C, becomes the low-potential-side voltage VHN in the first half period of the horizontal scanning period (1H), and in the latter half period thereof, a high polarity having the same polarity as the applied selection voltage. On the other hand, when the same display is performed while the voltage becomes VHP on the potential side, and the selection voltage applied to the scanning line 312 is negative during the latter half of the horizontal scanning period when the j-th scanning line 312 is selected. Data signal X
i is the horizontal scanning period (1
In the first half period of (H), it becomes the voltage VHP on the high potential side,
In the subsequent half period, the voltage VHN on the low potential side has the same polarity as the applied selection voltage.

Incidentally, when the intermediate display between the two is performed by the pulse width modulation, the waveform becomes as shown in FIG. Further, in the figure, the broken line region depends on the display contents of the pixels that intersect the scanning lines 312 other than the i-th scanning line 312 and the polarity of the scanning signal applied in the latter half of the selection period, This means that the voltage of the data signal Xi is determined.

As described above, the selection voltage is applied to the scanning signal Yj not in one horizontal scanning period but in the half horizontal scanning period (1 / 2H), and the data is divided into these two periods. When the signal Xi is applied, the data signal Xi changes to the high potential side voltage VH in one horizontal scanning period (1H).
The period during which the voltage becomes P and the low potential side voltage VHN becomes half each.
Therefore, in the non-selection period, a constant voltage is applied to the TFD 220 irrespective of the display content, and as a result, the off-leak amount in the TFD 220 in the non-selection period becomes constant, so that the occurrence of so-called crosstalk is prevented. The Rukoto.

1 and 2, the scanning lines and the data lines may be replaced with each other. In that case, reference numeral 312 in FIG. 2 is the data line and reference numeral 212 is the scanning line, and as a result, FIG. Liquid crystal layer 118 and TF in
The connection relationship of D220 will be switched, but this does not cause any problem in driving.

In the present invention, since the drive waveform itself does not matter, further reference will be avoided. However, it is necessary to clearly state that the scanning line drive circuit 350 is: While the scanning signals Y1 to Y240 are supplied to the respective scanning lines 312 by using the voltage generated by the power supply circuit 400, the data line driving circuit 250 uses the voltage generated by the power supply circuit 400 in the same manner. It is at the point of supplying the data signals X1 to X320 to the line 212, respectively. When considered as an electro-optical device,
It is also necessary to provide a configuration for controlling the scanning line drive circuit 350 and the data line drive circuit 250 by supplying a control signal, a clock signal, etc., but such a configuration is not directly related to the present invention, and therefore, in FIG. Is omitted.

<Power Supply Circuit> Next, a power supply circuit according to the first embodiment of the present invention, which is applied to the above-described electro-optical device, will be described. FIG. 4 is a block diagram showing a schematic configuration of the power supply circuit 400. This power supply circuit 400 uses a single power supply 410 for Vcc-GND.
Generate the selection voltages VSP and VSN from the voltage Vcc and the ground potential GND as they are and the unselection voltage V
It is supplied as HP and VHN.

As described above, the non-selection voltage VH
P and VHN are also used as the high-potential side voltage and the low-potential side voltage of the data signal, respectively. Therefore, the intermediate voltage VC which is the reference of the polarity is the voltage Vcc (VHP) and the ground potential G.
Since it has an intermediate value with ND (VHN), it becomes Vcc / 2, but in the present embodiment, this voltage is not actually generated, but means a virtual voltage.

Now, referring to FIG. 4, the voltage generating circuit 420
Is the voltage Vcc (first input potential) and the ground potential GND.
Using the potential difference from the (second input potential), the positive selection voltage VSP is generated and output via the supply line p1. Next, the inverting circuit 430 is provided with switches SW1 and SW2 interlocking with each other, and is configured as follows. That is, the selection terminal a of the switch SW1 is connected to the supply line p1 of the positive selection voltage VSP, the selection terminal b is connected to the supply line of the voltage Vcc, and the selected terminal c is connected to one of the capacitors Cp. Connected to the terminal. Further, the selection terminal a of the switch SW2 is grounded to the potential GND, the selection terminal b is connected to the supply line n1, and the selected terminal c is connected to the other terminal of the capacitor Cp. Such a switch is composed of switching elements such as single or plural transistors.

Further, the oscillation circuit 440 is the voltage generation circuit 4
20 for a clock signal CK1 (or C
K2) and signals / A and B for controlling the switching of the switches SW1 and SW2 to the inverting circuit 430. In the following description, "/" attached to a signal means an inverted signal.

In addition, a capacitor Cb2 is inserted between the ground potential GND and the supply line n1.

In the power supply circuit 400 having such a configuration, the voltage generation circuit 420 first generates and outputs the positive selection voltage VSP. At this time, in the inverting circuit 430, the switches SW1,
The terminals a and b of SW2 are alternately switched.
Here, when the terminals a of the switches SW1 and SW2 are respectively selected, the capacitor Cp is connected with the selection voltage VSP on the high potential side and the ground potential GND on the low potential side, as shown in FIG. Will be charged.

Next, when the terminals b of the switches SW1 and SW2 are respectively selected, the high potential side of the capacitor Cp becomes the voltage Vcc, so that the potential of the low potential side becomes the terminal a as shown in FIG. From the ground potential GND at the time of selecting, the fluctuation amount on the high potential side (VSP-Vc
Only c) can be lowered. Therefore, the capacitor Cp
The potential of the supply line n1 connected to the low potential side becomes a voltage obtained by inverting the positive selection voltage VSP with reference to the intermediate voltage VC, that is, the negative selection voltage VSN.

Then, again, the terminals a of the switches SW1 and SW2 are selected respectively, and the capacitor Cp is connected and charged with the selection voltage VSP on the high potential side and the ground potential GND on the low potential side. Such an operation will be repeatedly executed.

Even during the period when the terminals a of the switches SW1 and SW2 are selected, the potential of the supply line n1 is set to the negative selection voltage V by the capacitor Cb2.
It will be held in SN.

Next, details of each part in the power supply circuit 400 will be described.

<Voltage Generation Circuit> First, the voltage generation circuit 42.
0 will be described. The power supply circuit 4 according to the embodiment
Although various types of voltage generation circuits 420 applicable to H.00 can be considered, here, two modes that are assumed to be appropriate when applied to an electro-optical device will be described.

<Voltage Generating Circuit: Part 1> Then, first, the first mode of the voltage generating circuit 420 will be described. Figure 6
FIG. 4 is a circuit diagram showing a configuration of a voltage generation circuit according to the first aspect. The voltage generation circuit 420 shown in this figure is
It is a switching regulator that boosts the voltage Vcc by using an inductor (coil) L.

In FIG. 6, the latch circuit 422 latches the signal Vcp supplied to the input terminal D at the rising edge of the clock signal CK1 supplied from the oscillation circuit 440, and outputs the signal Vrcp from the output terminal Q. is there. The logical product (AND) circuit 424 outputs a pulse signal Vg which is a logical product of the signal Vrcp and the clock signal CK1. Therefore, the AND circuit 424 outputs the clock signal CK1 according to the signal Vrcp from the latch circuit 422. Here, the clock signal CK1 is, for example, as shown in FIG. 7, a pulse signal having a pulse width of about 0.5 μs and a frequency of about several hundred kHz.

Next, the pulse signal Vg output from the AND circuit 424 is supplied to the gate of the N-channel type transistor 426 which is one mode of the switch in the present invention. Here, the source of the transistor 426 is the potential GN.
While it is grounded to D, its drain has a voltage Vc at one end.
It is connected to the other end of the inductor L connected to the supply line of c. Further, the other end of the inductor L is connected to the diode D
A capacitor C whose one end is grounded to the potential GND through
It is connected to the other end OUT of b1 and the voltage appearing at the other end OUT is output as the positive selection voltage VSP.

Now, the other end OUT of the capacitor Cb1 is
It is grounded to the potential GND through the resistors R1 and R2.
Here, for convenience of explanation, if the voltage at the connection point of the resistors R1 and R2, that is, the voltage obtained by dividing the selection voltage VSP by the resistors R1 and R2 is VSP ′, this voltage VS
P ′ is supplied to the negative input terminal of the comparator 428. On the other hand, the reference voltage Vref is supplied to the positive input terminal of the comparator 428. Therefore, in the output signal Vcp of the comparator 428, the voltage VSP ′ is the reference voltage Vcp.
When it becomes lower than ref, it becomes H level, and when the voltage VSP ′ becomes higher than the reference voltage Vref, it becomes L level. And
This output signal Vcp is fed back to the input terminal D of the latch circuit 422. The reference voltage Vref is not fixed as will be described later, but is a voltage that is variable according to the environment such as temperature and settings.

Next, the operation of the voltage generation circuit 420 will be described. First, when the transistor 426, which is a switching element, is turned on, an on-current ion flows from the voltage Vcc toward the ground in the inductor L, so that energy is accumulated. On the other hand, when the transistor 426 is turned off, an off current ioff flows, so that the energy stored in the on period of the transistor 426 is added to the capacitor Cb1 via the forward direction of the diode D1 and in series with the voltage Vcc. It will be moved. Further, when all the energy stored in the inductor L moves to the capacitor Cb1, the diode D1 becomes reverse biased, so that the selection voltage VSP appearing at the other end OUT of the capacitor Cb1 does not flow backward to the voltage Vcc side. Therefore, the selection voltage VSP increases every time the transistor 426 is turned on and off.

However, in reality, the charging voltage of the capacitor Cb1 is attenuated as it is discharged to the load composed of the resistance and the capacitance of the scanning lines of the liquid crystal display device. Here, the selection voltage VSP is lowered, and the voltage VSP ′ obtained by dividing the selection voltage VSP by the resistors R1 and R2 is used as a reference voltage Vre as shown in FIG.
When it is lower than f, the output signal Vcp of the comparator 428 transits to H level. Along with this, the signal Vrcp from the latch circuit 422 transitions to the H level at the rising edge of the clock signal CK1 immediately after the transition of the signal Vcp to the H level, so that the AND circuit 424 opens. Therefore, the clock signal CK1 changes to the AND circuit 424.
Is output as a pulse signal Vg. Therefore, when the voltage VSP ′ falls below the reference voltage Vref, the transistor 426 is turned on / off at least once, so that the selection voltage VSP rises. That is, when the voltage VSP ′ is lower than the reference voltage Vref, the control for increasing the selection voltage VSP is artificially performed.

On the other hand, when the selection voltage VSP rises and the voltage VSP 'exceeds the reference voltage Vref, the output signal Vcp of the comparator 428 transits to the L level. Accordingly, the signal Vrcp changes to the L level at the rising edge of the clock signal CK1 immediately after the signal Vcp changes to the L level, so that the AND circuit 424 is closed. Therefore, since the clock signal CK1 is not supplied to the gate of the transistor 426, the selection voltage VSP
Is gradually reduced by the discharge of the capacitor Cb1. That is, the voltage VSP ′ is the reference voltage Vref.
If it is higher than that, the control in the direction of lowering the selection voltage VSP is spontaneously performed.

Therefore, as a whole, the voltage VSP '
Will be stabilized at a point where control in both directions is balanced, that is, near the reference voltage Vref. Here, since the voltage VSP ′ is a voltage obtained by dividing the selection voltage VSP by the resistors R1 and R2, VSP ′ = VSP · R2 /
Since (R1 + R2) is established and stabilized at the reference voltage Vref, the positive polarity selection voltage VSP generated by the power supply circuit 420 is eventually Vref (R1 + R2).
2) / R2 will stabilize.

In order to stabilize the VSP, it is necessary to increase the resistance value of the resistors R1 and R2, which is realized by using a polycrystalline silicon wiring layer formed in the semiconductor IC as the resistor. be able to. Further, in FIG. 7, the vertical scale of the voltage VSP ′ is enlarged in comparison with other signals for the sake of explanation. Conversely speaking, since the comparator 428 operates by using the voltage Vcc as a power source,
The input voltage VSP 'and reference voltage Vref
Also, in practice, it is set to be GND or more and Vcc or less.

<Voltage Generating Circuit: Part 2> Next, the second mode of the voltage generating circuit 420 will be described. FIG. 8 is a circuit diagram showing the configuration of the voltage generation circuit according to the second aspect. The voltage generation circuit 420 shown in this figure is a type that boosts the voltage Vcc using a piezoelectric transformer 427. Therefore, the transistor 426 and the inductor L in FIG. 6 are replaced by the piezoelectric transformer 427, and the part of the secondary side output that is equal to or higher than the potential GND is half-wave rectified by the diodes D3 and D4 to obtain the capacitor Cb1. It is configured to be charged to. Also,
In connection with the use of the piezoelectric transformer 427, the clock signal CK1 in the first mode is not used, and the clock signal CK2 has a duty ratio of about 50% as shown in FIG. Therefore, a pulse signal having a frequency of about 100 kHz is used instead. The other parts are the same as those in the first mode shown in FIG. 6, and the description thereof will be omitted.

The piezoelectric transformer 427 sandwiches the dielectric between the primary side electrode and the secondary side electrode, and the primary side expands and compresses the dielectric according to the applied pulse signal Vg. While mechanical vibration occurs, dielectric vibration occurs on the secondary side due to the vibration,
As a result, the boosted voltage is taken out as the secondary output. The common electrode of the piezoelectric transformer 427 is connected to the ground GND.

Here, the reason why the duty ratio of the clock signal CK2 is set to about 50% is that a waveform having symmetry is effective in terms of conversion efficiency because of the boosting using the piezoelectric transformer 427. In addition, the clock signal CK
It is the piezoelectric transformer 4 that sets the frequency of 2 to about 100 kHz.
This is because the natural frequency of the dielectric in 27 is about 100 kHz. That is, when the frequency of the clock signal CK2 is set near the natural frequency of the dielectric in the piezoelectric transformer 427, there is an advantage that the conversion efficiency of the voltage is improved.

Now, the operation of the voltage generating circuit 420 according to the second mode is almost the same as that of the first mode shown in FIG. 6, as described below. That is, the selection voltage VS
P decreases, and the divided voltage VSP 'is changed to the reference voltage Vre.
Below f, as shown in FIG.
The output signal Vcp of No. 28 shifts to the H level, and this is taken in by the latch circuit 422 at the rising edge of the clock signal CK2. As a result, the AND circuit 424 is opened and the clock signal CK2 is supplied to the piezoelectric transformer 427 as the pulse signal Vg. . Therefore, the clock signal C
After K2 is boosted by the piezoelectric transformer 427, it is rectified by the diodes D3 and D4 and charged in the capacitor Cb1, so that the control for increasing the selection voltage VSP is performed.

On the other hand, when the selection voltage VSP rises and the divided voltage VSP 'exceeds the reference voltage Vref, the output signal Vcp of the comparator 428 is output, as shown in FIG.
Shifts to the L level, and this is taken in by the latch circuit 422 at the rising edge of the clock signal CK2. As a result, the AND circuit 424 is closed, so that the clock signal CK2 is not supplied to the piezoelectric transformer 427. Therefore, the charging voltage of the capacitor Cb1 is attenuated as the load is discharged, so that control is performed in the direction of decreasing the selection voltage VSP.

Therefore, in the voltage generating circuit 420 according to the second mode, the positive side selection voltage VSP is Vref (R1 + R2) / R2, as in the first mode shown in FIG.
Will be stabilized at. Note that the voltage V
The vertical scale of SP ′ is enlarged in comparison with other signals for the same reason as in the first mode.

Further, in the second mode, instead of the piezoelectric transformer 427, it is possible to use an ordinary transformer using a winding coil. However, since the size of an ordinary transformer tends to be large when viewed as a component, the piezoelectric transformer 42 described above is required.
The configuration using 7 is more advantageous in terms of downsizing the circuit scale.

In FIG. 8, the piezoelectric transformer 427
The common electrode and the cathode of the diode D3 are grounded to the potential GND, but the voltage Vcc
It may be configured to be connected to the supply line. Although one end of the capacitor Cb1 is grounded to the potential GND in FIG. 6 or FIG. 8, it may be connected to the supply line of the voltage Vcc. With this configuration, the withstand voltage required for the capacitor Cb1 is smaller.

<Reference voltage Vref in the voltage generation circuit
By the way, the characteristics of the electro-optical material generally change with temperature. In addition, a mechanism for adjusting display characteristics and the like is usually provided in the electro-optical device in order to respond to user's preference and application. On the other hand, the selection voltage VSP (and the polarity-inverted selection voltage VSN) is also a voltage that defines the display characteristics of the electro-optical device. Therefore, it is necessary to compose and adjust the selection voltage VSP according to the environment and settings.

In such a configuration, firstly, in the voltage generating circuit 420 shown in FIG. 6 or 8, the selection voltage is generated with the fixed reference voltage Vref as a reference.
Secondly, a configuration is conceivable in which the generated selection voltage is lowered and adjusted by resistance division or a transistor to indirectly obtain a desired selection voltage. However, with this configuration,
A drop amount from the generated selection voltage to the adjusted voltage is a loss, which is not desirable in an electro-optical device that requires low power consumption.

Therefore, it is desirable to have a configuration in which the reference voltage Vref is appropriately changed according to changes in the environment and settings to directly generate a desired selection voltage. Generally, in a reference voltage generation circuit, a resistance having a temperature characteristic that a resistance value changes according to a temperature change is connected in series and / or in parallel to a reference voltage generation source circuit, and the reference voltage is changed to a temperature. It is preferable to change it accordingly. The change in the temperature-reference voltage characteristic may be set so that the temperature-transmittance characteristic change curve in the liquid crystal display device is compensated by the change in the voltage supplied as the reference voltage.

Further, as an example of such a configuration, in addition to this, for example, as shown in FIG. 10A, the temperature detected by the temperature sensor 4202 is converted into a voltage by the temperature-voltage table 4204. Then, a configuration is conceivable in which this is used as the reference voltage Vref. Further, as shown in FIG.
The voltage set in step 1, that is, the voltage output corresponding to the contrast is used as the reference voltage Vref, and further, as shown in FIG. A configuration in which each output voltage is weighted according to the coefficient k and this voltage is used as the reference voltage Vref is conceivable.

<Inverting Circuit> Next, the inverting circuit 430 will be described. FIG. 11A is a circuit diagram showing a specific configuration example of the inverting circuit 430 of the power supply circuit 400. As shown in this figure, the switch SW1 of the inverting circuit 430 has a P-channel type transistor Tp for inputting a signal / A to its gate between its terminal a and terminal b.
1 and an N-channel type transistor Tn1 for inputting a signal B to its gate are connected in series, and the connection point is configured as a terminal c. Similarly, switch SW2
Is a P-channel type transistor Tp2 for inputting a signal / A to its gate and an N-channel type transistor Tn for inputting a signal B to its gate between its terminals a and b.
2 are connected in series, and the connection point is configured as a terminal c. The terminals c of the switches SW1 and SW2 using the transistors as switching elements
The capacitor Cp is connected between them.

Therefore, in such a configuration, the signal /
When both A and B become L level, the transistor Tp
1, Tp2 is turned on and the transistors Tn1 and Tn2 are turned off. Therefore, when the terminals a are selected in the switches SW1 and SW2, respectively, when the signals / A and B are both at the H level, the transistors Tp1 and Tp2 are turned off, Since the transistors Tn1 and Tn2 are turned on, the switch S
The terminal b is selected in each of W1 and SW2.

In FIG. 11A, the switches SW1 and SW2 are each composed of a transistor, but for example, as shown in FIG. The configuration may be replaced with. However, in this configuration, the diode D
There is a drawback that the charging voltage of the capacitor Cp is reduced by the amount of the voltage drop generated in the forward direction at 11 and D12. The switch SW1 is connected to the diode D11,
Of course, the configuration may be replaced with D12.

Further, each transistor in FIG.
Although it is a single-channel transistor, it may have a transmission gate structure using P-channel and N-channel complementary transistors (both transistors are on / off controlled together).

<Oscillation Circuit> Next, the transistors Tp1,
The oscillation circuit 44 that generates the clock signal CK1 (CK2) supplied to the voltage generation circuit 420 together with the signals / A and B supplied to the gates of Tp2, Tn1 and Tn2.
The configuration of 0 will be described. FIG. 12 shows the oscillation circuit 4
It is a block diagram which shows the structure of 40. In this figure,
The source oscillation circuit 442 oscillates / generates a clock signal CK2 having a duty ratio of about 50%. Here, as a specific configuration of the source oscillation circuit 442, for example, FIG.
As shown in, the normal output of the three-stage series inverter is
CR that oscillates by feedback to the input end via a capacitor
An oscillator circuit or a crystal oscillator circuit in which a crystal oscillator is inserted in the feedback path from the output end to the input end of the inverter as shown in FIG.

When controlling the oscillation of the oscillation circuit 442 shown in (a) or (b) of the figure, the first-stage inverter shown in (a) or the inverter shown in (b) is used. The configuration may be replaced with a NAND circuit as shown in FIG. In this configuration, NAN
The same feedback signal as that of the input terminal of the inverter before the replacement is supplied to one input terminal of the D circuit, and the other input terminal has an H level when turning on the oscillation and an L level when turning off the oscillation. A control signal ON, which becomes a level, is supplied. In addition, this control signal ON is actually the panel 10
This signal is supplied by a control circuit (not shown) that controls 0, and is a signal that becomes L level when the panel 100 does not display for a long time. In this case, in the power supply circuit 400, the supply of the clock signal is stopped, so that the power consumption can be reduced accordingly.

Now, returning to the description of FIG. 12, regarding the voltage generation circuit (see FIG. 8) according to the above-described second mode,
Although the clock signal CK2 from the source oscillation circuit 442 is supplied as it is, when the voltage generation circuit according to the first aspect described above is used, the clock signal CK2 having a duty ratio of about 50% is waveform-shaped by the shaping circuit 443. Has been
This is supplied as the clock signal CK1.

In practice, when the voltage generation circuit according to the first aspect is used, the oscillation circuit shown in FIG. 13B causes the clock signal with a frequency of about 1 MHz (therefore, the pulse width is 0). .. .5 .mu.s) and appropriately thinning it out by the shaping circuit 443 to generate a clock signal CK1 having a frequency of about several hundred kHz, or an oscillator circuit having a frequency of several hundred kHz.
A clock signal of about z is generated and passed through a differentiating circuit to generate a clock signal CK1 having a pulse width of 0.5 μs and a frequency of 100 kHz. In the latter case, there is an advantage that the power consumption can be kept low because the frequency of the oscillation circuit is lowered. Further, when the voltage generation circuit according to the second aspect is used, the oscillator circuit shown in FIG. 13A generates a clock signal having a frequency of about 100 kHz and supplies it as it is as the clock signal CK2. Becomes Therefore, the shaping circuit 443 is unnecessary in the second mode.

Next, referring to FIG. 12, the frequency dividing circuit 444 is used.
Divides the clock signal CK2 to obtain a frequency of 10 kHz
The clock generating circuit 446 outputs a clock signal CK of a certain degree, and the clock forming circuit 446 generates signals / A and B having low logic amplitude from the clock signal CK. Here, the clock forming circuit 446 uses the clock signal CK to output signals / A and B having low logic amplitudes as shown in FIG. 14, for example.
To generate. That is, the clock forming circuit 446 firstly generates the signal A which is the inverted signal of the clock signal CK and which has the delayed rising edge and the signal / B which has the delayed falling edge. Then, these signals A and / B are respectively inverted to generate signals / A and B.

Since the power supply 410 is used up to the clock forming circuit 446, its output amplitude is the ground potential G.
Limited from ND to voltage Vcc. On the other hand, in the inverting circuit 430, the transistors Tp1, Tp2, Tn1 and Tn2 forming the switches SW1 and SW2 switch between voltages much higher than that. For this reason,
A signal / A of low logic amplitude by the clock forming circuit 446,
B is converted into a signal of high logic amplitude by the level shifter 448. Then, the amplitude-converted signal / A
As the gate signals of the transistors Tp1 and Tp2,
Similarly, the amplitude-converted signal B is transferred to the transistor Tn1,
The gate signal of Tn2 is supplied to each inverting circuit 430.

Here, as shown in FIG.
The period in which A is at the L level and the period in which the signal B is at the H level are set so as not to overlap with each other.
The transistors Tp1 and Tp2 and the transistors Tn1 and
Tn2 is turned on exclusively with respect to each other. Therefore, leakage of the capacitor Cp due to simultaneous turning on of the four transistors is prevented, and the switch S
In W1 and SW2, the terminals a and b are alternately selected.

Thus, the power supply circuit 4 according to the first embodiment
In 00, when the first mode (see FIG. 6) is adopted as the voltage generation circuit 420, only the inductor L and the capacitor Cb1 need be externally attached,
Further, if the second mode (see FIG. 8) is adopted, only the piezoelectric transformer 427 and the capacitor Cb1 are required. Besides, what is needed is a capacitor Cp used for polarity reversal,
Capacitor C for holding the negative selection voltage VSN
Only b2. Therefore, according to the power supply circuit 400 according to the present embodiment, a component that must be externally attached as compared with the conventional configuration in which the single power supply voltage Vcc is boosted by the charge pump circuit to generate the selection voltage. Since the number is greatly reduced, it is possible to simplify the mounting and reduce the cost.

Further, the power supply circuit 40 according to the first embodiment.
At 0, first, the positive selection voltage VSP is generated by the voltage generation circuit 420, and the switch SW
1, the terminal a is selected in SW2, and the capacitor C
Second, the terminal b is selected by being charged to p, and the polarity of the selection voltage VSP is inverted with respect to the intermediate voltage VC, and the negative selection voltage VSN is generated. Therefore, it becomes relatively easy to symmetrically generate the positive selection voltage VSP and the negative selection voltage VSN with respect to the intermediate voltage VC, and also the heat loss due to the charge / discharge current of the electro-optical material. Since this is prevented, the power consumption can be further reduced.

<Modification of First Embodiment> The above-described inverting circuit 430 has a structure in which the selection terminal b of the switch SW1 is connected to the supply line of the voltage Vcc, and the selection terminal a of the switch SW2 is grounded to the potential GND. However, it is not limited to this. For example, as shown in FIG. 15, the switch S
The selection terminal b of W1 may be grounded to the potential GND, and the selection terminal a of the switch SW2 may be connected to the supply line of the voltage Vcc. In this configuration, the switch S
When the terminals a of W1 and SW2 are respectively selected, the capacitor Cp is connected and charged with the selection voltage VSP set to the high potential side and the voltage Vcc set to the low potential side, as shown in FIG. Next, the switches SW1 and SW
When the two terminals b are selected, as shown in FIG. 16, the high potential side of the capacitor Cp becomes the ground potential GND. Therefore, the potential of the signal line n1 on the low potential side is the same as when the terminal a is selected. As a result of being reduced from the voltage Vcc by a fluctuation amount (VSP-GND) on the high potential side, as in the first embodiment, the positive selection voltage VSP.
Becomes a negative selection voltage VSN that is inverted with reference to the intermediate voltage VC. Note that the oscillator circuit 440 is omitted in FIG. 15 for simplification. In this respect, the same applies to FIGS. 17, 19 and 23 below.

Further, the voltage generation circuit 420 is configured to generate the positive selection voltage VSP, but it may be configured to generate the negative selection voltage VSN as shown in FIG. In this configuration, the switches SW1 and SW2
When the terminals b of are respectively selected, the capacitor Cp becomes
As shown in FIG. 18, the voltage Vcc is set to a high potential and the negative selection voltage VSN is set to a low potential to be connected and charged. Next, when the terminals a of the switches SW1 and SW2 are selected, as shown in FIG. 18, the low potential side of the capacitor Cp becomes the ground potential GND, so that the potential of the high potential side signal line p1 becomes As a result of being pulled up from the voltage Vcc at the time of selecting the terminal b by the fluctuation amount (GND-VSN) on the low potential side, the negative selection voltage VSN is changed to the positive selection voltage VSP obtained by inverting the intermediate voltage VC as a reference. Become.

Further, in the structure in which the voltage generating circuit 420 generates the negative selection voltage VSN, as shown in FIG. 19, the selection terminal b of the switch SW1 is grounded to the potential GND and the selection terminal a of the switch SW2 is grounded. May be connected to the supply line of the voltage Vcc. In this configuration, when the terminals b of the switches SW1 and SW2 are selected, the capacitor Cp connects the ground potential GND to a high potential and the negative selection voltage VSN to a low potential as shown in FIG. Will be charged. Next, when the terminals a of the switches SW1 and SW2 are selected, as shown in FIG. 20, the low potential side of the capacitor Cp becomes the voltage Vcc, so that the potential of the high potential side signal line p1 is From the ground potential GND when b is selected, the fluctuation component (Vcc
As a result of being increased by −VSN), similarly, the selection voltage VSN of the negative polarity becomes the selection voltage VSP of the positive polarity which is inverted with the intermediate voltage VC as a reference.

Here, in FIG. 17 and FIG. 19, as the voltage generation circuit 420 for generating the negative selection voltage VSN, for example, in the case of the first mode, FIG.
As shown in FIG. That is, in the voltage generation circuit 420 shown in FIG. 21, in comparison with the configuration shown in FIG. 6, first, the voltage Vcc changes to the ground potential GND due to the polarity inversion.
The ground potential GND is replaced with the voltage Vcc, secondly, the forward direction of the diode D1 is reversed, thirdly, the signals supplied to the positive input terminal and the negative input terminal of the comparator 428 are reversed, and fourthly, First, the transistor 426 is a P-channel type, and fifth, the AND circuit 424 is replaced with a NAND circuit. In this configuration, the energy stored in the inductor L during the on period of the transistor 426 is taken out with the opposite polarity during the off period of the transistor 426 and is stored (strictly speaking, discharged) in the capacitor Cb1. Become. In addition,
It is similar to FIG. 6 in that ON / OFF of the transistor 426 is feedback-controlled in accordance with the comparison result of the voltage VSN ′ obtained by dividing the output selection voltage VSN and the reference voltage Vref. Therefore, when the negative selection voltage VSN is high (absolute value is small), the inverted signal of the clock signal CK1 is supplied to the transistor 426, so that the selection voltage VS is increased.
While the control of decreasing N (increasing the absolute value) is artificially performed, when the negative selection voltage VSN is low (when the absolute value is large), the inverted signal of the clock signal CK1 is not supplied to the transistor 426. The control for increasing the selection voltage VSN (decreasing the absolute value) is performed spontaneously.

On the other hand, as the voltage generation circuit 420 for generating the negative selection voltage VSN, the voltage generation circuit according to the second mode is as shown in FIG. That is, FIG.
In the voltage generation circuit 420 shown in FIG. 2, the voltage Vcc is replaced with the ground potential GND and the ground potential GND is replaced with the voltage Vcc in accordance with the polarity inversion. , The diodes D3 and D4 have opposite forward directions, and thirdly, the signals supplied to the positive input terminal and the negative input terminal of the comparator 428 are opposite,
Fourth, the AND circuit 424 is replaced with a NAND circuit. In this configuration, the negative selection voltage VSN
Is high, the inverted signal of the clock signal CK2 is supplied to the primary side of the piezoelectric transformer 427, so that the control for lowering the selection voltage VSN is artificially performed, while when the negative selection voltage VSN is low, the clock signal CK2 is reduced. Since the inversion signal is not supplied to the primary side of the piezoelectric transformer 427, the control for increasing the selection voltage VSN is spontaneously performed.

In FIG. 21, the piezoelectric transformer 42
The common electrode in 7 and the anode of the diode D3 are
Although it is connected to the supply line of the voltage Vcc,
It may be configured to be grounded to the potential GND. 21 or 22, one end of the capacitor Cb1 has a voltage V
Although it is connected to the cc supply line, it may be configured to be grounded to the potential GND. This configuration is better for capacitor C
The withstand voltage required for b1 is small.

By the way, there are cases where the voltage Vcc from the power supply 410 (see FIG. 4) cannot be used as the voltage applied to the data line due to various circumstances such as the characteristics of the electro-optical material. In such a case, as shown in FIG. 23, the voltage Vcx different from the voltage Vcc is supplied as the high potential side voltage (non-selection voltage) VHP of the data signal, while the ground potential GND is changed to the low potential of the data signal. The voltage may be supplied as the side voltage (non-selection voltage) VHN, and the terminal b of the switch SW1 may be connected to the supply line of the voltage Vcx. In this configuration, the switches SW1 and S
When each terminal a of W2 is selected, the capacitor Cp
Is the selection voltage VS, as shown in FIG.
P is set to a high potential and ground potential GND is set to a low potential to be connected and charged. Next, when the terminals b of the switches SW1 and SW2 are respectively selected, as shown in FIG. 24, the high potential in the capacitor Cp changes to the voltage Vcx.
Therefore, the potential of the signal line n1, which is a low potential, is lowered from the ground potential GND when the terminal a is selected, by the amount of change in the high potential (VSP-Vcx), and as a result, similar to the first embodiment. Intermediate voltage V of the voltage applied to
Based on C '(= Vcx / 2), the positive selection voltage VS
The negative selection voltage VSN is obtained by inverting P.

In such a structure, the voltage Vc
x is generated from Vcc-GND by an operational amplifier (not shown), a DC-DC converter, or the like.
Although not shown, the same applies to a configuration in which the terminal b of the switch SW1 is grounded to the potential GND and the terminal a of the switch SW2 is connected to the supply line of the voltage Vcx.

Furthermore, such a configuration using the voltage Vcx instead of the voltage Vcc can be applied to other embodiments, and can be implemented by replacing the voltage Vcc in FIGS. 15, 17, and 19 with the voltage Vcx. is there.

As described above, when the applied voltage is used to compensate for the fact that the current-voltage characteristics of the TFD 220 are asymmetrical between the positive and negative electrodes, (Vcc-GND) is used as the data signal while the power source is used. In the circuit 400, the voltage Vcc different from the voltage Vcc is used to generate the positive selection voltage VSP and the negative selection voltage VSN, which may be asymmetric with respect to the intermediate voltage VC of the data signal. This makes it possible to compensate for the non-linearity in the TFD 220.

<Second Embodiment> In the power supply circuit according to the first embodiment described above, since it is applied to the panel 100 using the TFD 220, the intermediate voltage VC of the data signal is not actually generated. ing. On the contrary,
In a so-called passive matrix type electro-optical device that does not use a switching element such as the TFD 220, the non-selection voltage is almost always the intermediate voltage VC of the data signal.

Therefore, as a second embodiment, a power supply circuit applied to a passive matrix type electro-optical device will be described. Here again, before describing the power supply circuit, the overall configuration of the electro-optical device including this power supply circuit will be briefly described. FIG. 25 is a block diagram showing the electrical configuration of this electro-optical device. The electro-optical device shown in this figure differs from that shown in FIG. 1 in that
First, the panel 100 does not include a switching element such as the TFD 220, and the scan electrode (scan line) 31
3 is formed to extend in the row direction, while the data electrode (data line) 213 is formed to extend in the column direction. Secondly, the power supply circuit 400 is configured to select voltages VSP and VS.
N, the voltage VHP and VHN used for the data signal, and the point that the intermediate voltage VC is actually generated. Third, the display control signal PD causes the data line driving circuit 250, the scanning line driving circuit 350, and the power supply circuit 400 It has been supplied to.

First, according to the first difference, the panel 10 is
The structure of 0 is very simple as shown in FIG. That is, the data electrode 213 is formed on one substrate 200 that constitutes the panel 100, while the scanning electrode 313 is formed on the other substrate 300, and an electro-optic material such as TN type or STN ( Super Twisted Nematic) type, BTN (Bi-
A liquid crystal 105 of a bistable type such as a stable twisted nematic type or a ferroelectric type or a polymer dispersed type is sandwiched. Therefore, the pixel 116 has the data electrode 21.
At the intersection of the scanning electrode 313 and the scanning electrode 313, both electrodes and the liquid crystal sandwiched therebetween are formed.

Next, the second difference is related to the drive waveform in this electro-optical device shown in FIG. That is, in FIG. 27, the voltages VSP and V
SN is common to FIG. 3 in that it is a selection voltage, but it is different from FIG. 3 in that the non-selection voltage is only the intermediate voltage VC. Due to this difference, the intermediate voltage V in FIG.
That is, C is supplied to the scanning line drive circuit 350 as a non-selection voltage.

As shown in FIG. 27, the selection signal of the scanning signal Yj is the positive selection voltage VSP for the horizontal scanning period (1H) in which the scanning electrode 313 is selected.
Alternatively, the negative selection voltage VSN is applied. Therefore, the data signal Xi also becomes as follows corresponding to the scanning signal Yj. That is, i is counted from the left in FIG.
In the same figure as the th data electrode 213, j from the top
When the display content of the pixel 116 located at the intersection with the th scan electrode 313 is on-display, and during the horizontal scanning period (1H) in which the jth scan electrode 313 is selected, When the applied selection voltage has a positive polarity, as shown in FIG. 27A, the data signal Xi becomes the low-potential-side voltage VHN having the opposite polarity to the selection voltage, while displaying the same. In this case, and during the horizontal scanning period (1H) in which the j-th scanning electrode 313 is selected,
When the selection voltage applied to the scan electrode 313 has a negative polarity, the data signal Xi becomes a high-potential-side voltage VHP having a polarity opposite to that of the selection voltage, as shown in FIG.

When the display content of the pixel 116 located at the intersection of the i-th data electrode 213 and the j-th scan electrode 313 is OFF display, and the j-th scan electrode 313 is selected. When the selection voltage applied to the scan electrode 313 has a positive polarity during the horizontal scanning period (1H), the data signal Xi has a high polarity with the same polarity as the selection voltage, as shown in FIG. The voltage VHP on the potential side is applied, while the same display is performed, and during the horizontal scanning period (1H) in which the j-th scanning electrode 313 is selected,
When the selection voltage applied to the scan electrode 313 has a negative polarity, the data signal Xi becomes a low-potential-side voltage VHN having the same polarity as the selection voltage, as shown in FIG.

Next, the third difference will be described.
When the display control signal PD is a signal supplied from a control circuit (not shown), only a region included in a certain scan electrode 313 is in a display state, and a region included in another scan electrode 313 is a non-display region. In the case of (partial display), the signal is H level only during the period when the scan electrode 313 included in the display region is selected, and is L level during the other periods. For example, in the partial display as shown in FIG. 28, specifically, in the panel 100, the region scanned by the 1st to 120th scanning electrodes from the top is the display region, while the 121st to 240th scanning is performed. Assuming a partial display in which the region scanned by the electrode is the non-display region, the display control signal PD is at the H level in the first 120H period of one vertical scanning period (1H), as shown in FIG. And 12 of this latter half
It becomes L level during the period of 0H.

At this time, the scan electrodes 313 belonging to the display area
29, the scanning signals Y1 to Y120 are applied to one horizontal scanning period (1
H) is the selection signal VSP or VSN, but the scanning signal Y12 applied to the scanning electrodes 313 belonging to the non-display area
1 to Y240 are fixed to the non-selection voltage VC. On the other hand, in the period in which the display control signal PD is at the H level, the data signal Xi is, as described above, the pixel 1 located at the intersection of the polarity of the selection voltage and the scanning electrode 313.
Although it is determined according to the display content of 16, the scanning signal Y12 is set during the period when the display control signal PD is at the L level.
It is latched at the voltage level when the voltage of 0 becomes the selection voltage. That is, the voltage of the data signal Xi in the period in which the display control signal PD is at the L level is the voltage of the pixel 116 located at the intersection of the i-th data electrode 213 and the 240th scan electrode 313 located at the boundary of the display area. It is latched to either the voltage VHP or VHN depending on the display content and the polarity of the selection voltage applied at that time.
Here, since the polarity of the selection voltage in the scanning signal Yj is inverted every vertical scanning period (1F), the data signal Xi in the period in which the display control signal PD is at L level is also 1.
It is inverted every vertical scanning period (1F). Therefore, the scanning signals Y1 to Y fixed to the non-selection voltage VC
120 and the voltage applied by the data signal Xi during the period when the display control signal PD is at the L level, that is, the effective value of the voltage applied to the pixel 116 belonging to the non-display area is zero, so that the off display is performed. Will be seen.

<Power Supply Circuit> Next, a power supply circuit according to the second embodiment of the present invention will be described. FIG. 30 is a block diagram showing a schematic configuration of the power supply circuit 400. This power supply circuit 400 has a Vc supplied from a single power supply 410.
Although it is common with the power supply circuit according to the first embodiment (see FIG. 4) in that the selection voltages VSP and VSN are generated from the c-GND, the intermediate voltage V generated by the step-down circuit 450 is used.
C (= Vcc / 2) is supplied as a non-selection voltage, and the voltage Vcc and the ground potential GND are supplied to the high potential side voltage VHP and the low potential side voltage VHN of the data signal, respectively.
In terms of not sharing with non-selection voltage,
This is different from the power supply circuit according to the first embodiment.

Further, the power supply circuit 400 according to the present embodiment.
In that case, the oscillation circuit 440 is also slightly different.
That is, as shown in FIG. 31, the display control signal PD is supplied to the frequency dividing circuit 444 that divides the clock signal CK2 by the source oscillation circuit 442 and outputs the clock signal CK. Here, the frequency dividing circuit 44 in the present embodiment.
4 outputs the clock signal CK only when the display control signal PD is at the H level, and stops outputting the clock signal CK when the display control signal PD is at the L level. When the output of the clock signal CK is stopped, the clock forming circuit 446 does not generate the signals / A and B, so that the switching operation of the switches SW1 and SW2 in the inverting circuit 430 is also stopped.

As described above, when the display control signal PD is at the L level, the voltage applied to the scan electrode 313 is fixed to the non-selection voltage VC, and therefore the positive selection voltage VSP and the negative selection voltage VSN are selected. Therefore, in this case, it is meaningless to switch the switches SW1 and SW2 from one selection voltage to generate the other selection voltage. On the other hand, in the power supply circuit according to the present embodiment, when the display control signal PD is at the L level, the switching operation of the switches SW1 and SW2 in the inverting circuit 430 is stopped, so that the power consumption can be reduced accordingly. Will be planned.

Although the output of the clock signal CK is stopped in the frequency dividing circuit 444 when the display control signal PD is at the L level, the frequency dividing ratio is increased to lower the frequency of the clock signal CK. Even in this case, similarly, it becomes possible to suppress the power consumption.

Now, in such a second embodiment,
The other points are similar to those of the first embodiment. That is, as a first point, the voltage generation circuit 42 of the second embodiment.
0 may use the first mode (see FIG. 6) or the second mode (see FIG. 8). As a second point, which potential should be used for the polarity reversal in the inverting circuit 430 can be considered in the same manner as in the first embodiment. Therefore, in addition to the configuration shown in FIG. The terminal b may be connected to the potential GND and the terminal a of the switch SW2 may be connected to the supply line of the voltage Vcc. Thirdly, since the voltage generation circuit 420 may generate a negative selection voltage instead of a positive polarity, the voltage generation circuit 420 of the second embodiment may have the configuration shown in FIG. Alternatively, the configuration shown in FIG. 22 may be used. As a fourth point, not the voltage Vcc but the voltage Vc
Since x may be used as the non-selection voltage VHP, FIG.
In the configuration shown in FIG. 5, the step-down circuit 450 is inserted between VHP and VHN to provide the power supply circuit 4 according to the second embodiment.
It may be configured as 00. Furthermore, the power supply circuit 4 according to the second embodiment is obtained by appropriately combining the above first to fourth points.
Of course, it may be configured as 00.

<Modification of Second Embodiment> In the power supply circuit 400 shown in FIG. 30, unlike the first embodiment,
The intermediate voltage VC is actually generated. Therefore, the inversion circuit 430 may be configured to perform the inversion with reference to the intermediate voltage VC. Specifically, as shown in FIG. 32, in the inverting circuit 430, the selection terminal b of the switch SW1 and the selection terminal a of the switch SW2 are connected to the supply line of the intermediate voltage VC. In this configuration, first, when the terminals a of the switches SW1 and SW2 are selected, the capacitor Cp changes the selection voltage VSP.
Is set to the high potential side and the intermediate voltage VC is set to the low potential side for connection and charging. Next, when the terminals b of the switches SW1 and SW2 are respectively selected, the high potential side of the capacitor Cp becomes the intermediate voltage VC, so the potential of the low potential side becomes
From the intermediate voltage VC when the terminal a is selected, the amount of fluctuation on the high potential side (VSP-VC) is reduced. Therefore, the supply line n1 connected to the low potential side of the capacitor Cp
Is a voltage obtained by inverting the positive selection voltage VSP with reference to the intermediate voltage VC, that is, the negative selection voltage VSN.

Even in the configuration in which the polarity is inverted with reference to the intermediate voltage VC, the configuration excluding the second point regarding the reference of the inverting circuit can be adopted. That is, the first aspect of the voltage generation circuit 420
And the third point where the voltage generation circuit 420 generates a negative selection voltage that is not positive and the fourth point where the voltage Vcx is used as the non-selection voltage VHP instead of the voltage Vcc. Of course, the power supply circuit 400 according to the modification of the second embodiment may be configured.

<Third Embodiment> The first and second embodiments described above.
The power supply circuit according to the embodiment is applied to an electro-optical device in which one scanning line (electrode) is sequentially selected, but in general, in such an electro-optical device, The selection voltage applied to the selection scan line tends to be high.

Therefore, as a third embodiment, a plurality of scan electrodes are collectively selected at the same time, and the plurality of scan electrodes are selected a plurality of times within one vertical scanning period. An electro-optical device and a power supply circuit which are driven by the multi-line selection method and whose selection voltage is lowered will be described.

FIG. 33 is a block diagram showing the electrical construction of this electro-optical device. In the electro-optical device shown in this figure, the switching electrodes such as the TFD 220 are not formed in the panel 100, the scan electrodes 313 are formed extending in the row direction, and the data electrodes 213 are formed in the column direction. 25 is common to the electro-optical device shown in FIG. 25 in that the power supply circuit 400 is provided.
Are applied to the scanning line driving circuit 350 by the voltages VH, VC, V
While supplying a total of 3 voltages of L, the data line drive circuit 250
In terms of voltage ± V2, ± V1, and VC, a total of 5 voltages are supplied.

This difference will be mainly described, which is related to the drive waveforms in this electro-optical device shown in FIG. That is, as shown in FIG. 34, the scanning signals Y1 to the scanning electrodes 313 have the selection voltages VH and VL.
Although three voltages of the non-selection voltage VC and the non-selection voltage VC can be taken, the data signals X1 to X1 to the respective data electrodes 213 have voltages ± V2 and ± V.
This is because 5 voltages of 1 and VC can be obtained.

Now, in this multi-selection system, as shown in FIG. 34, in each field (1f) obtained by dividing one frame (1F) into four equal parts,
The scanning electrodes 313 are sequentially selected every four lines at the same time, and a selection voltage satisfying normality and orthogonality is applied in each selection period. Here, “normality” means that the effective values of the voltages applied to all the scan electrodes 313 are equal to each other in frame cycle units, and
“Orthogonality” means that the voltage applied to a certain scan electrode 313 and the voltage applied to another arbitrary scan electrode 313 are 1
This means that the sum of products for the frame is zero.

Next, the data signal Xi to the i-th data electrode 213 is determined as follows, for example. That is, first, if the selected voltage to the selected scan electrode 313 is positive polarity (VH), it is set to “1”, and negative polarity (VL).
If it is "-1", the selected scan electrode 31
Pixel 1 located at the intersection of the 3rd and i-th data electrode 213
If the display of 16 is off, it is set to "-1", and if it is on, it is set to "1". Secondly, the four scanning electrodes 3 selected simultaneously are selected.
The four mismatched pixels 116 are compared with each other to obtain the number of mismatches. Thirdly, if the number of mismatches is “4”, the voltage is V2, and if the number of mismatches is “3”, the voltage is V1.
If it is "2", the voltage is VC, and if it is "1", the voltage is V1.
If it is “0”, the voltage is −V2, and the data signal X
The voltage of i is defined.

The data signal Xi in FIG. 34 is
In the i-th data electrode 213, the scan electrodes Y1 to Y
The display of the eight pixels 116 that intersect with 8 is a waveform when, for example, on, on, on, on, on, off, on, on.

Although the selection voltage is applied in a temporally dispersed manner in one frame here, the selection voltage may be applied in a temporally aggregated manner in one frame. Further, the number of scanning electrodes selected at the same time is not limited to “4”, and for example, “2”, “3”,
It may be set to “7” or the like, and in this case, the number of voltages used for the data signal also increases or decreases according to the number of scanning electrodes selected at the same time.

<Power Supply Circuit> Next, a power supply circuit according to the third embodiment of the present invention will be described. FIG. 35 is a block diagram showing a schematic configuration of the power supply circuit 400.

In this power supply circuit, the voltage Vcc and the ground potential GND supplied from the single power supply 410 are supplied as the voltages V2 and VC used for the data signal, respectively. Therefore, in the present embodiment, the intermediate voltage VC of the data signal is V as in the first and second embodiments described above.
It should be noted that the reference of the polarity is different because it is the ground potential GND instead of cc / 2.

On the other hand, the voltage generation circuit 460 uses Vcc-G.
Voltage -V2 (= -Vcc) with polarity reversed from ND
Is generated. The specific configuration is shown in FIG.
The voltage −V2 may be generated in the same manner as the voltage generation circuit 420 of FIG. 1 or FIG. By connecting them,-(V2-VC) =-V2 may be generated in the negative direction with reference to the previous intermediate voltage VC, or an operational amplifier or the like may be used. Further, step-down circuit 470 receives voltage Vcc and ground potential GN.
A voltage V1 (= Vcc / 2) is generated by dividing the voltage between D and the step-down circuit 480.
/ 2) is generated.

The voltage generation circuit 420 is configured as described above to generate the positive selection voltage VH from Vcc-GND generated by the power supply 410. This specific configuration may be similar to that of the voltage generation circuit 420 shown in FIG. 6 or FIG. 8, the polarity may be inverted by using a capacitor, or an operational amplifier may be used. However, the selection voltage VH may be lower than the selection voltage VSP. In addition, in the inverting circuit 430, the selection terminal a of the switch SW2 is connected to the supply line of the voltage −V2, but the selection voltage VH having the positive polarity is inverted in polarity with respect to the intermediate voltage VC to select the negative polarity. There is no change in the point of generating the voltage VL.

Therefore, in the power supply circuit 400, the positive selection voltage VH is first generated by the voltage generation circuit 420 with reference to the intermediate voltage VC of the data signal.
Next, the polarity of the selection voltage VH is inverted by the inversion circuit 430 to generate the negative selection voltage VL, and
In the multi-selection method, five values of the voltage of the required data signal are generated.

Incidentally, in the third embodiment (and its modification described later), the other points are the same as the first embodiment.
This is similar to the embodiment and the second embodiment. That is, the first
Regarding the point, the voltage generation circuit 420 of the third embodiment has a first
(See FIG. 6) or the second aspect (see FIG. 8) may be used. The second point is that the inverting circuit 4
The potential to be used for polarity reversal in 30 can be considered in the same manner as in the first and second embodiments. Therefore, in addition to the configuration shown in FIG. The supply line for V2 may be connected to the supply line for the voltage Vcc at the terminal a of the switch SW2. Thirdly, the voltage generation circuit 4
21 may generate a selection voltage having a negative polarity instead of the positive polarity.
22 may be used, or the configuration shown in FIG. 22 may be used. Fourthly, the voltage Vcx different from the voltage Vcc is set as the voltage V2, and the intermediate voltage V
It may be inverted to the negative polarity side with respect to C and used as the voltage −V2. Furthermore, it is needless to say that the power supply circuit 400 according to the third embodiment may be configured by appropriately combining the above first to fourth points.

<Modification of Third Embodiment> In the power supply circuit 400 shown in FIG. 35, the intermediate voltage VC is actually generated as in the second embodiment. Therefore, the inversion circuit 430 may be configured to perform the inversion with reference to the intermediate voltage VC. Specifically, as shown in FIG. 36, in the inverting circuit 430, the selection terminal b of the switch SW1 and the selection terminal a of the switch SW2 are connected to the supply line of the intermediate voltage VC. With this configuration,
First, when the terminals a of the switches SW1 and SW2 are selected, the capacitor Cp is connected and charged with the selection voltage VH on the high potential side and the intermediate voltage VC on the low potential side. Next, when the terminals b of the switches SW1 and SW2 are respectively selected, the high potential side of the capacitor Cp becomes the intermediate voltage VC, so that the potential of the low potential side becomes the terminal a.
The intermediate voltage VC at the time of selecting is reduced by the fluctuation amount (VH-VC) on the high potential side. Therefore, the potential of the supply line n1 connected to the low potential side of the capacitor Cp becomes a voltage obtained by inverting the positive selection voltage VH with the intermediate voltage VC as a reference, that is, the negative selection voltage VL.

Even in the configuration in which the polarity is inverted with reference to the intermediate voltage VC as described above, a configuration excluding the second point regarding the reference of the inverting circuit can be adopted. That is, the first aspect of the voltage generation circuit 420
And a third point where the voltage generation circuit 420 generates a negative selection voltage that is not positive polarity and a fourth point that uses the voltage Vcx as the voltage V2 instead of the voltage Vcc, as appropriate. Power supply circuit 400 according to modified example of third embodiment
Of course, it may be configured as.

Further, although partial display is not mentioned in the electro-optical device shown in FIGS. 35 and 36, the display control signal PD is supplied to the data line driving circuit 250, the scanning line driving circuit 350 and the power supply circuit 400. Then, it goes without saying that the same processing as in the second embodiment may be performed.

Further, in the first, second and third embodiments, the display device using the liquid crystal as the electro-optical material has been described as an example, but electroluminescence,
It can be applied to all devices using the electro-optical effect, such as fluorescent display tubes and plasma displays. That is, the present invention can be applied to all electro-optical devices having a configuration similar to that described above.

<Electronic Device> Next, a case where the above-described electro-optical device is applied to a portable electronic device will be described. In this case, the electronic device is roughly configured as shown in FIG. That is, CPU (Central Processing Uni
t) 1002 controls each part of the electric device via the bus. Further, the VRAM 1004 is the panel 10
It has a one-to-one storage area corresponding to 0 pixels, and the display data randomly written by the CPU 1002 is sequentially read out according to the scanning direction. Further, the control circuit 100
6 generates various timing signals required for driving the panel 100 and supplies them to the drive circuit 150. The drive circuit 150 is a general term for the data line drive circuit 250 and the scan line drive circuit 350 described above. In addition, the power supply circuit 400 uses the power supply 41 as described above.
From 0, the drive circuit 150 generates a voltage used for a scanning signal and a data signal. The power source 410 is also used as a power source for this electronic device. According to such an electronic device, the number of external components in the power supply circuit 400 is reduced, so that the mounting can be simplified and the cost can be reduced.

<Mobile Phone> Next, an example in which the above-described display device is applied to a mobile phone will be described. FIG. 38 is a perspective view showing the configuration of this mobile phone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302, an earpiece 1304, a mouthpiece 1306, and a panel 100.
It is equipped with. The panel 100 enables the above-described partial display. For example, when an incoming call or an outgoing call is made, a full-screen display in which the entire area is used as a display area is performed. ,
Partial display is performed in which only an area for displaying necessary information such as characters is a display area and other areas are non-display areas. This allows the panel 100 to be in standby mode.
Since the electric power consumed by is reduced, it is possible to extend the standby time.

The electronic device to which the electro-optical device according to the present embodiment is applied is a device with strong demand for low power consumption, such as the above-mentioned mobile phone, pager, clock, PDA (personal information terminal). ) Etc. are suitable. However, in addition to this, it is also applied to LCD TVs, viewfinder type, monitor direct view type video tape recorders, car navigation devices, calculators, word processors, workstations, video phones, POS terminals, devices equipped with touch panels, etc. It is possible.

[0132]

As described above, according to the present invention, as compared with the conventional configuration in which the selection voltage of both electrodes is generated by the charge pump circuit or the switching regulator, it is difficult to configure the components, particularly the semiconductor substrate. As a result, the number of components such as a power storage element and an inductor mounted as external components is reduced, so that the mounting can be simplified and the cost can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram showing an overall configuration of an electro-optical device including a power supply circuit according to a first embodiment of the present invention.

FIG. 2 is a partially cutaway perspective view showing a configuration of a panel portion in the electro-optical device.

FIG. 3 is a waveform diagram showing an example of a drive waveform in the electro-optical device.

FIG. 4 is a block diagram showing a configuration of a power supply circuit in the electro-optical device.

FIG. 5 is a diagram for explaining a polarity reversing operation in the power supply circuit.

FIG. 6 is a circuit diagram showing a configuration of a voltage generation circuit according to a first aspect of the power supply circuit.

FIG. 7 is a timing chart for explaining the operation of the voltage generation circuit.

FIG. 8 is a circuit diagram showing a configuration of a voltage generation circuit according to a second aspect of the power supply circuit.

FIG. 9 is a timing chart for explaining the operation of the voltage generation circuit.

10A to 10C are block diagrams each showing an example of a configuration for generating a reference voltage for a voltage generation circuit.

11A and 11B are circuit diagrams each showing an example of a specific configuration of an inverting circuit in the same power supply circuit.

FIG. 12 is a circuit diagram showing a configuration of an oscillation circuit in the power supply circuit.

13A and 13B are block diagrams each showing an example of the configuration of a source oscillation circuit in the same oscillation circuit, and FIG. 13C is a replaceable NAND in the inverter of the source oscillation circuit. It is a figure which shows a circuit.

FIG. 14 is a timing chart for explaining a signal generated by the oscillation circuit.

FIG. 15 is a block diagram showing a first modification of the power supply circuit.

FIG. 16 is a diagram showing a polarity reversing operation in the modification.

FIG. 17 is a block diagram showing a second modification of the power supply circuit.

FIG. 18 is a diagram showing a polarity reversing operation in the modification.

FIG. 19 is a block diagram showing a third modified example of the power supply circuit.

FIG. 20 is a diagram showing a polarity reversing operation in the same modified example.

FIG. 21 is a circuit diagram showing a configuration of a voltage generation circuit applicable in the modification.

FIG. 22 is a circuit diagram showing a configuration of a voltage generation circuit applicable in the modification.

FIG. 23 is a block diagram showing a fourth modified example of the power supply circuit.

FIG. 24 is a diagram showing a polarity reversing operation in the same modified example.

FIG. 25 is a block diagram showing an overall configuration of an electro-optical device including a power supply circuit according to a second embodiment of the invention.

FIG. 26 is a partially cutaway perspective view showing a configuration of a panel portion of the electro-optical device.

FIG. 27 is a waveform chart showing an example of a drive waveform in the electro-optical device.

FIG. 28 is a plan view of the panel for explaining the partial display in the electro-optical device.

FIG. 29 is a waveform diagram for explaining a signal waveform during partial display in the same electro-optical device.

FIG. 30 is a block diagram showing a configuration of a power supply circuit in the electro-optical device.

FIG. 31 is a block diagram showing a configuration of an oscillator circuit in the power supply circuit.

FIG. 32 is a block diagram showing a modified example of the power supply circuit.

FIG. 33 is a block diagram showing an overall configuration of an electro-optical device including a power supply circuit according to a third embodiment of the invention.

FIG. 34 is a waveform chart showing an example of a drive waveform in the electro-optical device.

FIG. 35 is a block diagram showing a configuration of a power supply circuit in the electro-optical device.

FIG. 36 is a block diagram showing a modified example of the power supply circuit.

FIG. 37 is a block diagram showing a schematic configuration of an electronic device to which the electro-optical device according to the embodiment is applied.

FIG. 38 is a perspective view showing a configuration of a mobile phone which is an example of an electronic apparatus to which the electro-optical device is applied.

[Explanation of symbols]

100 ... panel 116 ... Pixel 118 ... Liquid crystal layer 200 ... substrate 212, 213 ... Data line (data electrode) 220 ... TFD 234 ... Pixel electrode 250 ... Data line drive circuit 300 ... substrate 312, 313 ... Scan lines (scan electrodes) 350 ... Scan line drive circuit 400 ... Power supply circuit 410 ... power supply 420, 460 ... Voltage generation circuit 426 ... transistor 427 ... Piezoelectric transformer 430 ... Inversion circuit 440 ... Oscillation circuit 450, 470, 480 ... Step-down circuit 1300 ... Mobile phone L: inductor Cp, Cb1, Cb2 ... Capacitor

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ Identification code FI theme code (reference) G09G 3/20 622 G09G 3/20 622Q 623 623U // G02F 1/133 520 G02F 1/133 520 (72) Inventor Katsunori Yamazaki 3-3-5 Yamato, Suwa City, Nagano Seiko Epson Co., Ltd. F-term (reference) 2H093 NA16 NC03 NC06 NC26 NC27 NC34 ND39 5C006 AA15 AC02 AC11 AC13 AC26 AF42 AF68 AF72 BB12 BB17 BC03 BC12 BF14 BF23 BF23 BF23 BF26 BF27 BF34 BF36 BF37 BF38 BF43 BF46 BF49 FA16 FA19 FA25 FA36 FA42 FA43 FA48 FA52 5C080 AA10 BB06 DD05 DD10 DD20 DD22 DD26 EE29 FF03 FF11 FF12 JJ02 JJ03 JJ04 JJ06 KK07

Claims (28)

[Claims] 1. A power supply circuit that supplies a potential used as a selection voltage to the scanning line to an electro-optical device that intersects the plurality of scanning lines and the plurality of data lines, Based on the intermediate value of the signal voltage applied to the voltage generator, a voltage generation circuit that generates one of the positive polarity and negative polarity selection voltages, and the power storage based on the one selection voltage generated by the voltage generation circuit. An electric storage element for performing, and a voltage stored in the electric storage element, a polarity inversion with reference to a predetermined value, and an inverting circuit for outputting as the other of the positive or negative selection voltage, the voltage The generation circuit accumulates power between the switching element and the first and second input potentials when the switching element is turned on, and accumulates power when the switching element is turned off. An inductor that discharges the generated power, and based on the power discharged from the inductor, selects one of the positive polarity and the negative polarity selection voltage based on the intermediate value of the signal voltage applied to the data line. A power supply circuit of an electro-optical device characterized by generating. 2. The voltage generation circuit further includes a circuit for controlling ON / OFF of the switching element according to a comparison result of a voltage based on electric power emitted from the inductor and a target voltage. The power supply circuit for the electro-optical device according to claim 1. 3. The switching element is on / off controlled according to a pulse signal.
Alternatively, the power supply circuit of the electro-optical device according to claim 2. 4. A power supply circuit that supplies a potential used as a selection voltage to the scanning line to an electro-optical device that intersects the plurality of scanning lines and the plurality of data lines, Based on the intermediate value of the signal voltage applied to the voltage generator, a voltage generation circuit that generates one of the positive polarity and negative polarity selection voltages, and the power storage based on the one selection voltage generated by the voltage generation circuit. An electric storage element for performing, and a voltage stored in the electric storage element, a polarity inversion with reference to a predetermined value, and an inverting circuit for outputting as the other of the positive or negative selection voltage, the voltage The generation circuit includes a transformer for inputting a pulse signal to the primary side, and generates either the positive polarity or the negative polarity selection voltage based on the secondary side output of the transformer. Power supply circuit of the electro-optical device that. 5. The transformer is a piezoelectric transformer that generates mechanical vibrations by a voltage applied to a primary side thereof, and converts the mechanical vibrations into a voltage and outputs the voltage from a secondary side. A power supply circuit for the electro-optical device according to claim 4. 6. The voltage generation circuit further includes a circuit for controlling the supply of the pulse signal to the primary side of the transformer according to a comparison result of a voltage based on a secondary side output of the transformer and a target voltage. The power supply circuit of the electro-optical device according to claim 4, further comprising: 7. The electro-optical device according to claim 1, wherein the inverting circuit has a storage element in which a voltage terminal to which an electrode is connected is switched based on a clock signal. The power circuit of the device. 8. Among the plurality of scanning lines, when only a first region composed of a part of the scanning lines is in a display state, and a second region composed of other scanning lines is not displayed, When a scan line belonging to the second area is selected,
8. The power supply circuit for an electro-optical device according to claim 1, wherein the polarity reversal by the reversing circuit is stopped or the reversal frequency is reduced. 9. A drive circuit of an electro-optical device for driving a pixel, which is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, wherein an intermediate of signal voltages supplied to the data lines. With reference to the value, a power supply circuit that generates a positive polarity and a negative polarity selection voltage, respectively, and a positive polarity and a negative polarity selection voltage generated by the power supply circuit in a predetermined order for each of the scanning lines. A scanning line driving circuit for applying the voltage; and the power supply circuit, the voltage generation circuit for generating one of the positive polarity or the negative polarity selection voltage from the first and second input potentials, and the voltage generation circuit. A power storage element that stores power based on a selection voltage generated by a circuit, and the voltage stored in the power storage element is polarity-inverted with a predetermined value as a reference, and either the positive polarity or the negative polarity selection voltage is the other. When The voltage generation circuit includes a switching element, and when the switching element is turned on, electric power is stored between the first and second input potentials while the switching element is turned off. Driving an electro-optical device, the inductor generating an accumulated electric power, and generating either one of the positive polarity or the negative polarity selection voltage based on the electric power emitted from the inductor. circuit. 10. A drive circuit of an electro-optical device for driving a pixel, which is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, wherein an intermediate of signal voltages supplied to the data lines. With reference to the value, a power supply circuit that generates a positive polarity and a negative polarity selection voltage, respectively, and a positive polarity and a negative polarity selection voltage generated by the power supply circuit in a predetermined order for each of the scanning lines. A scanning line driving circuit for applying the voltage; and the power supply circuit, the voltage generation circuit for generating one of the positive polarity or the negative polarity selection voltage from the first and second input potentials, and the voltage generation circuit. A power storage element that stores power based on a selection voltage generated by a circuit, and the voltage stored in the power storage element is polarity-inverted with a predetermined value as a reference, and either the positive polarity or the negative polarity selection voltage is the other. The voltage generation circuit includes a transformer for inputting a pulse signal to the primary side, and either the positive polarity or the negative polarity selection voltage is selected based on the secondary side output of the transformer. A drive circuit for an electro-optical device, characterized in that it generates one. 11. A driving method of an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, wherein a switching element is turned on and off and the switching element is turned on and off. When turned on, electric power is stored in the inductor between the first and second input potentials, while when the switching element is turned off, the electric power stored in the inductor is discharged and supplied to the data line. A first step of generating one of a positive polarity and a negative polarity selection voltage with an intermediate value of the signal voltage as a reference and storing the voltage based on the selection voltage; and a voltage stored in the first step. A second step of reversing the polarity with respect to a predetermined value as a reference, and outputting the polarity as the other of the positive polarity and the negative selection voltage. A method of driving an electro-optical device, wherein the selection voltage generated in the step and the second step is applied to each of the scanning lines in a predetermined order. 12. A driving method of an electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, wherein a pulse signal is input to a primary side of a transformer. ,
Based on the secondary side output of the transformer, one of the positive and negative selection voltages is generated with reference to the intermediate value of the signal voltage supplied to the data line, and the electricity is stored based on the selection voltage. A first step of performing, and a second step of inverting the polarity of the voltage stored in the first step with a predetermined value as a reference and outputting the voltage as the other of the positive polarity or the negative polarity selection voltage. A method of driving an electro-optical device, comprising: applying the selection voltage generated in the first process and the second process in a predetermined order to each of the scanning lines. 13. An electro-optical device in which a pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, wherein an intermediate value of a signal voltage supplied to the data lines is used as a reference. Power supply circuits that generate positive and negative selection voltages, respectively, and scan line drive that applies the positive and negative selection voltages generated by the power supply circuit to each of the scan lines in a predetermined order. And a voltage generation circuit that generates one of the positive polarity and the negative polarity selection voltage from the first and second input potentials, and the power generation circuit that is generated by the voltage generation circuit. An electricity storage element that stores electricity based on a selected voltage, and an inversion that inverts the polarity of the voltage stored in the electricity storage element based on a predetermined value and outputs the other of the positive polarity and the negative polarity selected voltage. A voltage generating circuit, the voltage generating circuit stores a power between the first and second input potentials when the switching element and the switching element are turned on, and the stored power when the switching element is turned off. An electro-optical device including: an inductor that discharges the positive voltage; and that generates one of the positive polarity and the negative polarity selection voltage based on the power discharged from the inductor. 14. An electro-optical device in which a pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, wherein an intermediate value of a signal voltage supplied to the data lines is used as a reference. Power supply circuits that generate positive and negative selection voltages, respectively, and scan line drive that applies the positive and negative selection voltages generated by the power supply circuit to each of the scan lines in a predetermined order. And a voltage generation circuit that generates one of the positive polarity and the negative polarity selection voltage from the first and second input potentials, and the power generation circuit that is generated by the voltage generation circuit. An electricity storage element that stores electricity at a selected voltage, and an inversion circuit that inverts the polarity of the voltage stored in the electricity storage element with a predetermined value as a reference and outputs the other of the selected voltage of the positive polarity or the negative polarity as the other. The voltage generation circuit includes a transformer for inputting a pulse signal to a primary side, and generates either the positive polarity or the negative polarity selection voltage based on a secondary side output of the transformer. And electro-optical device. 15. An electro-optical device in which a pixel is provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, wherein an intermediate value of a signal voltage supplied to the data lines is used as a reference. The power supply circuit includes a power supply circuit that generates a selection voltage of positive polarity and a selection voltage of negative polarity, and the power supply circuit uses an inductor or a transformer driven in response to a pulse signal, and outputs the positive polarity from the first and second input potentials. Alternatively, a voltage generation circuit that generates one of the negative selection voltages, a storage element that stores power at the selection voltage generated by the voltage generation circuit, and a voltage stored in the storage element are set to a predetermined value. An inversion circuit that inverts the polarity as a reference and outputs the other of the positive polarity or the negative polarity selection voltage as the other, and only a first region formed of a part of the plurality of scanning lines. Is displayed, while the second area including the other scanning lines is not displayed, when a scanning line belonging to the second area is selected,
An electro-optical device characterized in that the polarity reversal by the reversing circuit is stopped or the reversal frequency thereof is reduced. 16. An electronic apparatus using the electro-optical device according to claim 13 for a display unit. 17. A mutual relation between the first potential and the second potential given from the first input line and the second input line with reference to an intermediate potential between the first potential and the second potential. A voltage generation circuit that is symmetric and that generates a third potential and a fourth potential whose potential difference from the intermediate potential is larger than the difference between the first potential and the second potential; When the inductor receives the first potential and the second potential from the second input line and the second input line, the electrical energy accumulated in the inductor is stored in the first capacitor and the third potential is stored. And a second capacitor connected between the first supply line and the first input line to output the third capacitor output to the first supply line. The electric potential and the first electric potential applied to the first input line, Second means for storing a voltage between them in the second capacitor, and the second capacitor between the second input line and a second supply line for supplying the fourth potential. By connecting the second input line to the second input line
And a third means for generating the fourth potential, which is the potential separated from the voltage stored in the second capacitor, from the potential. 18. The first potential and the second potential given from the first input line and the second input line are symmetrical to each other with respect to the first potential and the intermediate potential. A voltage generation circuit that generates a third potential and a fourth potential, the potential difference of which is greater than the difference between the first potential and the second potential, the first input line and the second input line First means for storing the electric energy accumulated in the inductor by receiving the first potential and the second potential from the inductor in the first capacitor and outputting the energy as the third potential, The first supply line by connecting a second capacitor between the first supply line and one of the first input line or one of the third input lines for receiving the fifth potential. Input to the one input line and the third potential being output to Second means for storing electric voltage between potential to said second capacitor being, said second capacitor first input line or the third
By connecting between one of the input lines and the second supply line, the voltage component stored in the second capacitor from the first potential or the fifth potential. A third means for generating the fourth potential which is a remote potential, and a voltage generating circuit comprising: 19. The voltage generator according to claim 18, further comprising means for generating the fifth potential from the first potential and the second potential by using an operational amplifier or a DC-DC converter. circuit. 20. From the ground potential and the second potential given from the first input line and the second input line, they are symmetrical to each other with reference to an intermediate potential between the ground potential and the second potential. A voltage generation circuit that generates a third potential and a fourth potential having a potential difference from the intermediate potential that is larger than a difference between the ground potential and the second potential, wherein the first input line and the A means for receiving the ground potential and the second potential from the second input line in the inductor and storing the electric energy accumulated in the inductor in the first capacitor to generate the third potential. Is connected between the first supply line and the first input line to provide the third potential output to the first supply line and the first input line. The voltage between the ground potential and And a second capacitor connected between the second input line and a second supply line for supplying the fourth potential. The second given to the input line
And a means for generating the fourth potential which is the potential separated from the voltage stored in the second capacitor from the potential. 21. From the ground potential and the second potential given from the first input line and the second input line, they are mutually symmetrical with respect to the ground potential, and a potential difference from the intermediate potential is the ground potential. A voltage generation circuit that generates a third potential and a fourth potential that are greater than a difference between a potential and the second potential, wherein the first input line and the second input line are connected to the ground potential and the second potential. Means for storing electric energy accumulated in the inductor in the first capacitor by receiving the second potential to the third capacitor and outputting the third potential as the third potential; By connecting between the first input line or one input line of the third input line for receiving the fifth potential, the third potential output to the first supply line and the third potential Potential input to the one input line A means for energy storage in the second capacitor a voltage between the said second capacitor first input line or the third
By connecting between one of the input lines and the second supply line, the voltage stored in the second capacitor is separated from the ground potential or the fifth potential. Means for generating the fourth potential, which is a potential, and a voltage generation circuit comprising: 22. An electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, comprising the voltage generating circuit according to claim 17. A power supply circuit for an electro-optical device characterized by the above. 23. An electro-optical device for driving a pixel provided corresponding to each intersection of a plurality of scanning lines and a plurality of data lines, comprising the voltage generation circuit according to any one of claims 17 to 21. However, the drive circuit of the electro-optical device, wherein the first potential and the second potential are supplied to the data line. 24. The electro-optical device according to claim 23, wherein the third potential and the fourth potential are used to drive a plurality of scanning lines which constitute the electro-optical device. Drive circuit. 25. When a region including a part of the plurality of scan lines is in a display state and a region including other scan lines is in a non-display state, the region is in the non-display state 7. A means for stopping the switching operation of the second means and the third means or for reducing the frequency of a signal for controlling the switching operation during the period when the scanning line is selected. 23 or 2
4. The drive circuit for the electro-optical device according to item 4. 26. An electro-optical device comprising the power supply circuit according to claim 22. 27. An electro-optical device comprising the drive circuit for the electro-optical device according to claim 23. 28. An electronic device comprising the electro-optical device according to claim 26.