JP2001092402A - Power source circuit, electrooptical device and electronic equipment - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a power source circuit realizing an electrooptical device in which the display unevenness caused by ripples which are generated in a driving voltage does not appear. SOLUTION: In this power source circuit, when the number of pieces of a reference signal which are generared in a vertical scanning period (frame) is an even number, a timing when a driving voltage is generated is shifted by a time equivalent to one cycle of a latch signal (the reference signal) before and after the vertical scanning period is changed over. As a result, ripples which are superposed for every vertical scanning period are cancelled. For example, when this power source circuit is used for a liquid crystal display device, the display unnevenness can be suppressed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply circuit, an electro-optical device, and an electronic apparatus.

[0002]

2. Description of the Related Art In general, a liquid crystal display device as an electro-optical device has features such as small size and thinness, low power consumption, and a flat display. Therefore, a wristwatch, a portable game machine, a notebook personal computer, It is widely applied to display portions of electronic devices such as televisions and car navigations.

This liquid crystal display device is generally constituted by a liquid crystal display panel, a power supply circuit, a data line drive circuit and a scanning line drive circuit.

[0004] Among them, the liquid crystal display panel has a liquid crystal sandwiched between two substrates (hereinafter, referred to as first and second substrates). Here, a plurality of data lines are formed on the first substrate, and a plurality of scanning lines are formed on the second substrate in a direction crossing the data lines. Further, a plurality of pixel electrodes are arranged in a matrix on the first substrate. These pixel electrodes are arranged at respective intersections of the data lines and the scanning lines, and are connected to the data lines. A plurality of counter electrodes are arranged in a matrix on the second substrate so as to face each pixel electrode. These counter electrodes are each connected to a scanning line.

The scanning line driving circuit is a circuit for selecting a scanning line for each horizontal scanning period within one vertical scanning period and applying a selection voltage to the selected scanning line. The data line driving circuit is a circuit that applies a data voltage to a plurality of data lines within one horizontal scanning period.

A power supply circuit is a circuit for generating a power supply voltage of the liquid crystal display device and various reference voltages. These reference voltages include those supplied to the data line driving circuit and the scanning line driving circuit. This power supply circuit includes a plurality of charge pump circuits. These charge pump circuits are provided with a latch signal LP generated every horizontal scanning period.
Alternatively, the latch signal LP is driven by a frequency-divided signal.

The scanning line driving circuit and the data line driving circuit select necessary voltages from various reference voltages supplied from the power supply circuit, and output the above-described selection voltage for the scanning lines and the data voltage for the data lines. You do it.

In such a configuration, the selection voltage is supplied from the scanning line driving circuit to one or a plurality of scanning lines in each horizontal scanning period within one vertical scanning period, and during that time, the data line driving circuit supplies each data line with the selection voltage. Is supplied with a data signal. As a result, an electric field corresponding to the voltage difference between the data signal and the selection voltage is generated between each pixel electrode and each counter electrode connected to the relevant data line and scanning line. Then, the transmittance of the liquid crystal between the two electrodes changes according to the electric field between each pixel electrode and each counter electrode, and ON / OFF of each pixel is determined. An image is displayed by performing such an operation for each horizontal scanning period.

[0009]

In the above-described conventional electro-optical device, the charge pump is driven by the latch signal LP synchronized with the horizontal scanning period. There is a problem that a ripple having a cycle twice as long as the signal LP is generated and display unevenness due to the ripple may occur.

Here, this problem will be described in detail with reference to an example shown in FIG.

FIG. 22 shows waveforms of a latch signal LP, a frame switching signal FR, and a driving voltage -V2 which is one of driving voltages generated in a certain liquid crystal display device.

In FIG. 22, a frame switching signal FR
Is a signal which becomes H level in an odd frame and L level in an even frame, for example. Drive voltage-V2
Is one of the drive voltages obtained by driving the charge pump circuit by the latch signal LP, and a ripple having a cycle twice as long as the latch signal LP is superimposed as shown in the figure.

In this example, a so-called MLS driving method is employed as a driving method of the scanning lines and the data lines, and four pixels are driven for one frame (vertical scanning period).
The processing is performed in two fields 1f to 4f. More specifically, in one field, a plurality of scanning lines are driven for each horizontal scanning period in the field, and driving of all the scanning lines is completed in one field.
On the other hand, in each horizontal scanning period, each data line on the liquid crystal panel is driven.

In the example shown in FIG. 22, an even number of latch signals LP are generated during one frame. Therefore, after a series of ripple waveforms are generated in the field 1f, a ripple waveform having the same phase as the ripple waveform is repeatedly generated in the subsequent fields 2f to 4f. The same is true even if the frame is switched.

As described above, when the in-phase ripple waveform is superimposed on the drive voltage in each vertical scanning period, the pixel driven by the drive voltage corresponding to the peak portion of the ripple in a certain vertical scanning period is used for the subsequent vertical scanning period. Even during the period, the driving is always performed by the driving voltage corresponding to the peak portion of the ripple. Similarly, in a certain vertical scanning period,
The pixel driven by the driving voltage corresponding to the ripple valley portion is always driven by the driving voltage corresponding to the ripple valley portion even in each subsequent vertical scanning period. As a result, shading appears on the display screen.

The present invention has been made in view of the above-described circumstances, and has an electro-optical device in which display unevenness does not appear due to a ripple generated in a driving voltage, a power supply circuit applied to the electro-optical device, and an electric power device. It is an object to provide an electronic device using an optical device.

[0017]

In order to solve the above-mentioned problem, the present invention supplies a driving voltage to an electro-optical device which drives a pixel for one screen every vertical scanning period to display an image. A power supply circuit that performs switching operation for generating a drive voltage every time a reference signal synchronized with each horizontal scanning period in the vertical scanning period is generated twice; Correction means for shifting the timing of the operation of generating the drive voltage by the switching power supply means by one period of the reference signal every N vertical scanning periods (N is an integer of 1 or more) when the number of reference signals is an even number; It is characterized by having.

According to another aspect of the present invention, there is provided a power supply circuit for supplying a driving voltage to an electro-optical device for displaying an image by driving pixels for one screen every vertical scanning period. A switching power supply unit that receives a reference signal synchronized in each of the repeated horizontal scanning periods and repeats an operation of generating a drive voltage every time the reference signal is generated twice, and an N vertical scanning period (where N is one or more). Correction means for shifting the timing of the operation of generating the driving voltage by the switching power supply means by one cycle of the reference signal for each integer).

With such a configuration, the voltage fluctuation period due to the driving voltage can be inverted every vertical scanning period, and as a result, the influence of ripple can be canceled every vertical scanning period.

On the other hand, according to the present invention, a two-phase clock signal is supplied to a power supply circuit for supplying a driving voltage to an electro-optical device that drives a pixel for one screen to display an image every vertical scanning period. Accordingly, the first switching operation and the second switching operation are sequentially performed, and a switching power supply unit that generates a driving voltage and supplies the driving voltage to the electro-optical device, and is generated for each of a plurality of horizontal scanning periods in the vertical scanning period. Means for generating the two-phase clock signal in accordance with a reference signal and supplying the clock signal to the switching power supply means, wherein when the number of reference signals generated in the vertical scanning period is an even number, the N vertical scanning period (N Is an integer of 1 or more)
Clock signal generating means including means for inverting the order of each phase of the two-phase clock signal every time.

Further, according to the present invention, a two-phase clock signal is supplied to a power supply circuit for supplying a driving voltage to an electro-optical device for driving a pixel for one screen to display an image every vertical scanning period. Switching power supply means for sequentially performing the first switching operation and the second switching operation to generate a driving voltage and supplying the driving voltage to the electro-optical device; and for each horizontal scanning period repeated an even number of times during the vertical scanning period. Receiving the reference signal synchronized with the clock signal, generating the two-phase clock signal and supplying the generated signal to the switching power supply means, wherein the two-phase clock signal is generated every N vertical scanning periods (N is an integer of 1 or more). And a clock signal generating means including means for reversing the order of each phase.

With such a configuration, the clock signal generating means outputs two signals every time the vertical scanning period is switched.
A signal in which the order of each phase of the phase clock signal is reversed is output to the switching power supply means. Then, the drive voltage generated from the switching power supply means reverses the voltage fluctuation cycle every vertical scanning period. As a result, it is possible to cancel the influence of the ripple every vertical scanning period.

Also, the present invention relates to a method for controlling N
= 1 is preferred.

Further, in the present invention, it is preferable that the switching power supply means has a charge pump for performing a step-up / step-down operation by the clock signal.

On the other hand, the electro-optical device according to the present invention has a plurality of data lines and a plurality of scanning lines intersecting the data lines, and drives each of the plurality of scanning lines for each vertical scanning period. An electro-optical device that drives each pixel interposed at an intersection of each data line and each scanning line by driving the plurality of data lines in each of a plurality of horizontal scanning periods within the period. A power supply circuit for generating a drive voltage for driving a scanning line and a data line by performing a switching operation in accordance with a reference signal synchronized with the reference signal, wherein the number of the reference signals generated in the horizontal scanning period is an odd number. It is characterized by having.

Further, the electro-optical device according to the present invention has a plurality of data lines and a plurality of scanning lines intersecting the data lines, and divides a frame which is a vertical scanning period into a plurality of scanning lines for each field. And driving the plurality of data lines in each of a plurality of horizontal scanning periods in each vertical scanning period, thereby driving each pixel interposed at the intersection of each data line and each scanning line. An optical device, comprising: a power supply circuit that generates a driving voltage for driving a scanning line and a data line by performing a switching operation in accordance with a reference signal synchronized with the horizontal scanning period, wherein the reference voltage generated in the field is provided. The number of signals is an odd number, and the electro-optical device according to the present invention has a plurality of data lines and a plurality of scanning lines intersecting with the data lines. By driving the plurality of scanning lines for each scanning period and driving the plurality of data lines in each of a plurality of horizontal scanning periods in each vertical scanning period, an intersection between each data line and each scanning line is provided. An electro-optical device that drives each pixel interposed therebetween, comprising a power supply circuit that generates a driving voltage for driving a scanning line and a data line by performing a switching operation in accordance with a reference signal synchronized with the horizontal scanning period. A switching power supply unit that sequentially performs a first switching operation and a second switching operation by receiving a two-phase clock signal, generates a driving voltage, and supplies the driving voltage to the electro-optical device; The two-phase clock signal is generated in accordance with a reference signal generated for each of a plurality of horizontal scanning periods in a vertical scanning period to generate the switching power supply. The number of reference signals generated in the vertical scanning period is an even number, and the number of reference signals generated in each of the two-phase clock signals is increased every N vertical scanning periods (N is an integer of 1 or more). Clock signal generating means including means for reversing the order.

With this configuration, the voltage fluctuation period due to the drive voltage is inverted every vertical scanning period, and the influence of ripple is canceled every vertical scanning period. Then, it is possible to reduce the display unevenness caused by the ripple.

Further, the present invention relates to the method of N
= 1 is preferred.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment according to the present invention will be described below with reference to the accompanying drawings of FIGS.

<< 1 >> First Embodiment <1.1> Liquid Crystal Display Device <1-1.1> Configuration of Liquid Crystal Display Device FIG. 1 shows an embodiment of an electro-optical device according to the present invention. FIG. 2 is a block diagram showing a configuration of the display device 100.

The liquid crystal display device 100 is generally constituted by a liquid crystal display panel 101, a liquid crystal drive circuit 102 to which image data representing a display object is input, and a liquid crystal drive power supply circuit 10. Here, the image data is data for one screen that indicates ON / OFF of each pixel of the liquid crystal display panel 101.

Here, as shown in FIG. 2, the liquid crystal display panel 101 is provided between a substrate having a plurality of scanning lines X1, X2... Xm and a substrate having a plurality of data lines Y1, Y2. A liquid crystal layer is interposed.

<1-1-2> Configuration and Operation of Liquid Crystal Driving Circuit In the liquid crystal driving circuit 102 according to the present embodiment, the scanning line driving circuit 103 and the data line driving circuit 104 operate the liquid crystal display panel 101 based on the so-called MLS driving method. Drive is performed. Here, a driving method of the liquid crystal display panel 101 in the present embodiment will be described with reference to FIG.

First, in this embodiment, one frame F (1F and 2F in FIG. 3) is divided into four fields 1f to 4f.
, And driving of each pixel is performed in each field. Here, each field is divided into a plurality of horizontal scanning periods. Further, all the scanning lines are divided into a plurality of groups each including four scanning lines.

The scanning line driving circuit 103 selects one group for each horizontal scanning period, and preliminarily determines a latch signal LP generated for each horizontal scanning period for each scanning line constituting the selected group. A selection voltage according to the specified pattern is applied. Then, the scanning line driving circuit 103
All the groups are sequentially selected by using one field.
FIG. 3 illustrates a selection voltage applied to each scanning line, taking a group including four scanning lines X1 to X4 as an example.

Focusing on each group, the pattern of the selection voltage applied to each scanning line differs for each field. In the example shown in FIG. 3, the pattern of the polarity of the selection voltage applied to the scanning lines X1 to X4 is the first field 1f.
+-++,-++++ in the next field 2f, +++-in the next field 3f, and +++-+ in the last field 4f. When the frame is switched, the selection voltage pattern is switched to another one.

The data line drive circuit 104 includes a power supply circuit 1
0 to 5 types of driving voltages V2, V1, Vc, -V1,-
V2 is supplied. Here, between each drive voltage, V2
>V1>Vc>-V1> -V2. Also,
There is a relationship of V2 = 2 × V1 between the voltages V1 and V2. In each horizontal scanning period, the data line driving circuit 104 selects necessary driving voltages from these driving voltages for each data line, and outputs a data signal.

Focusing on each pixel, the data line driving circuit 1
Reference numeral 04 outputs a data signal corresponding to each pixel divided into four fields. FIG. 3 illustrates the waveform of the data signal for the data line Y1, which is the leftmost one of all the data lines.

Here, the data line Y1 and the four scanning lines X1
A method of generating a data signal for the data line Y1 will be described below, taking as an example a case where all four pixels at the intersections with X4 are turned on.

First, when ON / OFF states of four pixels are patterned by setting ON to + and OFF to-, the result is +++++.

Next, when the selection voltage for the scanning lines X1 to X4 is patterned by setting the positive selection voltage to + and the negative selection voltage to-, the selection voltage pattern in the field 1f becomes +-++.

Here, comparing the on / off state pattern of the pixel +++ and the selection voltage pattern +-++, there is one mismatch between them. Therefore, in the field f1, the data line drive circuit 104 selects -V1 from the above five types of drive voltages as the data signal for the data line Y1.

Next, looking at each field other than the field 1f, the pattern of the selection voltage in the field f2 is-++++, the pattern of the selection voltage in the field f3 is +++-, and the pattern of the selection voltage in the field f4 is +++-+. Has become. In these cases, there is one non-coincidence between the ON / OFF state pattern of the pixel +++ and the selection voltage pattern. Therefore, in the fields 2f to 4f, the data line drive circuit 104 selects -V1 from the above five types of drive voltages as the data signal for the data line Y1.

In the example described above, since there is only one mismatch between the pattern of the ON / OFF state of the pixel and the pattern of the selection voltage, the data line driving circuit 10
4, the drive voltage -V1 is selected. However, when the number of mismatched portions is different, a drive voltage other than -V1 is selected. That is, the data line drive circuit 104 outputs the drive voltage −V2 when the number of mismatched portions is 0, the drive voltage Vc when the number of mismatched portions is 2, and the drive voltage −C3 when the number of mismatched portions is 3. V1, the number of mismatched parts is 4
Is satisfied, the driving voltage V2 is selected and applied to the data line as a data signal.

In this manner, the data line driving circuit 104 generates a time-series driving voltage pattern corresponding to the combination of the on / off pattern of each pixel specified by the image data and the pattern of the selection voltage for the scanning electrode. The data is supplied to the data line, and the image is displayed.

In the MLS drive described above, for example, A GENERALIZED ADDRESSING TECHNIQUE FO
R RMS RESPONDING MATRIX LCDS.1988 INTERNATIONAL DI
SPLAYRESEARCH CONFERENCE P80-85, JP-A-5-461
No. 27, for example.

<1.2> Liquid Crystal Driving Power Supply Circuit Next, the liquid crystal driving power supply circuit 10 used in the four-line simultaneous selection driving method will be described with reference to FIGS.

<1-2-1> Overall Configuration of Liquid Crystal Driving Power Supply Circuit FIG. 4 is a block diagram showing the configuration of the liquid crystal driving power supply circuit 10. As shown in FIG. As shown in FIG. 4, the power supply circuit 10 for driving a liquid crystal is supplied with a ground potential GND and a power supply voltage Vcc from a single power supply (not shown). The power supply circuit 10 for driving a liquid crystal performs a boosting process or a step-down process on the power supply voltage Vcc so that the ground potential GND is used as a reference.
Nine types of voltages VH, V2, V1, Vc, -V1, -V2, Vdd
Generates y, VL and Vee. However, the voltage Vc includes
The ground potential GND is used as it is. Also, the voltage V2
, The power supply voltage Vcc is used as it is.

The clock forming circuit 11 receives the latch signal LP
To generate two-phase clock signals A and B from a power supply voltage Vcc. The details of the clock forming circuit 11 will be described later.

The 1/2 voltage step-down circuit 16 is a circuit for generating a positive voltage V1 which is 1/2 times the power supply voltage Vcc from the power supply voltage Vcc.

The negative direction double boosting circuit 15 is provided with a power supply voltage Vcc.
Is a circuit that generates a negative voltage twice as large as the above and outputs the same with reference to the power supply voltage Vcc. Here, with reference to the ground potential GND, the negative-direction double boosting circuit 15 is provided with a power supply voltage Vcc
It outputs a negative voltage -V2 of the same magnitude as

The 1/2 booster circuit 17 is a circuit for generating a negative voltage -V1 which is 1/2 times the output voltage -V2 of the negative double booster circuit 15.

The negative-direction six-fold booster circuit 12 has a power supply voltage Vcc
Is generated and output with reference to the power supply voltage Vcc. Here, with reference to the ground potential GND, the negative-direction six-fold booster circuit 12 outputs a negative voltage Vee that is six times the power supply voltage Vcc.

The contrast adjusting circuit 13 generates and outputs a selection voltage VL that provides an optimum contrast from the output voltage Vee of the negative-direction six-fold boosting circuit 12. This selection voltage VL
Is the negative selection voltage supplied to the scanning line X.

The constant power supply 18 has a voltage Vc higher than the selection voltage VL.
A voltage higher by c is generated, and this is
4 is supplied as a logic voltage Vddy.

The booster circuit and the step-down circuit in the above-described configuration are constituted by charge pumps driven by clock signals A and B.

<1-2.2> Clock forming circuit <1-2.2-1> Configuration of clock forming circuit Here, clock forming circuit 11 constituting power supply circuit 10
Will be described with reference to FIG. A pulse-like latch signal LP generated every horizontal scanning period is input to the clock forming circuit 11 as a reference signal.

The D-type flip-flop DF is / Q
The output terminal is connected to the write data input terminal D, whereby the toggle operation is performed at the rising edge of the latch signal LP.

The frame switching signal FR and the determination signal SEL are input to the AND gate AND. Here, the frame switching signal FR is, for example, a signal that becomes H level in an odd frame and L level in an even frame. The determination signal SEL goes high when the number of latch signals LP in the frame is even, and goes low when the number of latch signals LP is odd.

Exclusive OR Gate EX-OR
Is the determination result signal S output from the AND gate AND
And a signal R output from the flip-flop DF.

The NOR gates Nor1 and Nor2 are for forming two-phase clock signals A and B having different timings, and are provided with inverters Inv1, Inv2 and Inv.
3 and Inv4 form signals / A, / B, Doff and / R having phases opposite to those of A, B, / Doff and R, respectively.

<1-2.2-2 Operation of Clock Forming Circuit> Next, the operation of the clock forming circuit 11 will be described with reference to FIG.

The clock forming circuit 11 outputs two-phase clock signals A and B generated according to a periodically generated pulse-like latch signal LP. The two-phase clock signals A and B are supplied to a charge pump circuit (for example, FIG.
The switching operation is performed by the middle double boosting circuit 15).

The charge pump circuit repeatedly charges the pumping capacitor with the power supply voltage Vcc and charges the backup capacitor with the pumping capacitor. Further, in the charge pump circuit, as shown by the pulse width TP shown in FIG.
), The two-phase clock signals A and B are both at “L”. For this reason, in the charge pump circuit, all of the switching means are turned off, and escape of electric charge at the transition timing is prevented.

However, if the off-time due to the switching operation at the transition timing is too long, the time required to charge the pumping capacitor and the backup capacitor is shortened, so that a necessary voltage cannot be obtained. For this reason, the pulse width TP of the latch signal LP is usually 100 ns to 30 ns.
A pulse clock having a period of about 0 nS and a period of about several tens of μS to about 100 μS is convenient as a basic clock of this circuit. Since the charging and discharging of the liquid crystal display panel 101 occur in one horizontal scanning period, the driving voltage of the liquid crystal display panel 101 can be charged using the latch signal LP.

Next, the display off control signal / Doff will be described. Here, while the control signal / Doff is at "L", the clock signals A and B are also at "L", and the operation of the charge pump circuit is stopped. That is, the power supply circuit 1
0 has a function of stopping supplying a clock signal to the charge pump circuit. By adding this function, the power supply circuit 10 can make the power consumption during the display-off control almost zero.

Furthermore, in the clock forming circuit 11 according to the present embodiment, when the number of pulses of the latch signal LP in the frame F is an even number, when the frame switching signal FR is switched, the determination result output from the AND gate AND The signal S also switches from "L" to "H". Then, the clock forming circuit 11 shifts the clock signal A by one period of the latch signal LP, as indicated by a section a. Similarly, the clock signal B is shifted by one period of the latch signal LP.

Thus, the phases of the two-phase clock signals A and B in the frame before switching and the phases of the two-phase clock signals A and B in the frame after switching can be shifted by a half cycle.

In the charge pump circuit, the on / off operation by the switching means is performed by the frame switching signal F.
Since the shift is performed by a half cycle before and after the switching of R, the ripple superimposed on the output drive voltage (for example, -V2)
It can be shifted before and after the frame switching signal FR is switched. As a result, the ripple superimposed on the drive voltage can be canceled for each frame.

That is, the pixel driven by the driving voltage corresponding to the peak portion of the ripple in the frame before the switching is driven by the driving voltage corresponding to the valley portion of the ripple in the frame after the switching. Thus, by offsetting the ripple due to the drive voltage for each frame, it is possible to suppress the unevenness of shading appearing on the display screen.

<1-2-3> Charge Pump Circuit Double booster circuit 14 and negative direction six-fold booster circuit 12 shown in FIG.
The basic configuration of such a charge pump circuit will be described with reference to FIG.

In FIG. 7, SWa and SWb are interlocking switches, and one of the switches is tilted to the A side while the other is tilted to the A side. Although SWa and SWb are represented by mechanical switches in FIG. 7, actually, the switches SWa and SWb
Is composed of a MOS transistor for controlling conduction and interruption to the A side, a MOS transistor for controlling conduction and interruption to the B side, and a pair of transistors in general.

Each of the transistors receives two-phase clock signals A and B from the clock forming circuit 11.
When the clock signal A is "H", the switches SWa, S
Wb falls to the A side, and when the clock signal B is "H", the switches SWa and SWb fall to the B side.

Here, while the switches SWa and SWb receive the clock signal A and switch to the A side, the pumping capacitor Cp is charged with the voltage of Vb-Va. Next, when the switches SWa and SWb receive the clock signal B and switch to the B side, the charge charged in the pumping capacitor Cp is transferred to the backup capacitor Cb. By repeating this switching operation, the voltage applied to the backup capacitor Cb, that is, V
The voltage between e-Vd approaches a value substantially equal to the voltage between Vb-Va. At this time, if Vd is a fixed voltage, a voltage higher than Vd by Vb-Va is generated in Ve. Conversely, if Ve is a certain voltage,
A voltage lower than Ve by Vb-Va is generated at Vd. As described above, the charge pump circuit outputs a boosted / stepped-down drive voltage.

As described above, the charge pump circuit
Depending on where a, Vb, Vd, and Ve are connected, it is determined whether this circuit functions as a booster circuit or a step-down circuit.

Further, since the switches SWa and SWb are operated by the clock signals A and B, the driving voltage output from the charge pump circuit includes the clock signals A and B.
B switching timing (twice the cycle of latch signal LP)
Ripples are superimposed.

<1.3> Effect of First Embodiment The liquid crystal display device 1 according to the present embodiment configured as described above.
In the case of 00, when the number of pulses of the latch signal LP existing in one frame is an even number by the clock forming circuit 11, when the frame switching signal FR is switched as shown in the time chart of FIG. Two-phase clock signals A and B shifted by one period of LP are output to the charge pump circuit. As a result, as shown in FIG. 8, the waveform of the driving voltage −V2 generated in a certain frame 1F and the waveform of the driving voltage −V2 generated in the next frame 2F are shifted by a half cycle phase,
The voltage fluctuation period can be reversed before and after switching.
Then, the drive voltage can be averaged between the frames, and the influence of the ripple due to the drive voltage can be canceled.

As a result, it is possible to cancel out the influence of the ripple due to the double cycle of the latch signal LP, which is generated every time the screen is rewritten. That is, for example, when the screen is rewritten at 60 Hz, the influence of the ripple on one screen can be canceled by the influence of the ripple on the next screen, and the influence of the ripple generated from the power supply circuit 10 can be totally canceled. Then, it is possible to reduce the display unevenness caused by the voltage fluctuation due to the power supply circuit.

In the above embodiment, the case where the liquid crystal is driven by an AC voltage by the frame inversion method has been described. A case has been described in which the phase in which the voltage fluctuates is shifted by a half cycle every frame period, but the phase in which the voltage fluctuates is shifted by a half cycle every frame.
The phase can be shifted by a half cycle for each field. In this case, instead of the frame switching signal FR input to the AND gate AND of the clock forming circuit 11, a field switching signal may be input.
With such a configuration, the driving voltage −V2 output from the power supply circuit can be shifted in phase by a half cycle for each of the fields f1, f2, f3, and f4, as shown in FIG. As a result, it is possible to reduce display unevenness due to ripples, which has occurred due to voltage fluctuations caused by the power supply circuit.

<< 2 >> Second Embodiment Next, the specific configuration of the charge pump circuit described in the first embodiment will be described with reference to FIGS.
This will be described with reference to FIG.

<2.1> Double Boost FIG. 10 is a diagram in which Vd is connected to Vb in FIG.
It is a conceptual diagram of a double boosting charge pump circuit. Here, for the above-mentioned reason, SWe and SWb continuously repeat the switching operation, so that Ve−Vd = V
Since e−Vb = Vb−Va, Ve−Va = (Ve
-Vb) + (Vb-Va) = 2 * (Vb-Va). That is, when Va is set to the reference level (0 V) of the potential, Ve = 2 × Vb, and Ve is a voltage that is twice Vb.

<2.2> Negative direction double boosting FIG. 11 is a diagram in which Ve is connected to Va in FIG.
It is a conceptual diagram of a charge pump circuit for double boosting in the negative direction.
Since SWa and SWb successively repeat the switching operation, Ve−Vd = Va−Vd = Vb−Va, so that Vb−Vd = (Vb−Va) + (Va−Vd)
= 2 × (Vb−Va). That is, when Vb is set to the reference level (0 V) of the potential, Vd = 2 × Va.
d is a voltage obtained by boosting Va twice in the negative direction.

<2.3> Step-down by 1/2 FIG. 12 is a diagram showing a case where the input voltage Vb-Va is changed to Vb in FIG.
FIG. 14 is a conceptual diagram of a charge pump circuit for 倍 step-down, which has been changed to −Vd. Ve is the output voltage, V
The current consumed by the load connected to e is supplied from the backup capacitor Cb. First, when SWa and SWb are conducting with the B side, the pumping capacitor Cp and the backup capacitor Cb are connected in parallel, so that the voltages applied to Cp and Cb are equal. Next, SW
When a and SWb are switched to A side, C connected in series becomes
p and Cb fall between the input voltages Vb and Va, and C
The voltage applied to p and Cb is half of the input voltage.

Next, when SWa and SWb are switched to the B side again, Cp and Cb are connected in parallel, so that the charge stored in Cp is supplied to Cb, and the voltage applied to Cp and Cp
The voltage applied to b becomes equal. Therefore, if the charge that can be stored in Cp and Cb is sufficiently larger than the charge that is removed by the load current of Ve, SWa and SWb
Continuously repeats the switching operation,
At e, an output voltage close to half the input voltage is generated.

<2.4> Negative Direction Sixfold Boost FIG. 13 is a conceptual diagram showing an example of a negative direction sixfold boosting charge pump circuit. FIGS. 14 (a) and 14 (b)
SWa1 to SWa3 and SWb1 to SWb3 are A
It is a connection relation diagram at the time of switching to the side and the B side. S
Wa1 to SWa3, SWb1 to SWb3 are interlocking switches, Cp1 to Cp3 are pumping capacitors, Cb
1 and Cb23 are backup capacitors.

By the same operation as the above-described double boosting circuit in the negative direction, -V3B generates a voltage -2 × (Vcc-GND) which is twice the voltage of GND with respect to Vcc in the negative direction. When all switches are switched to the A side, FIG.
As shown in (a), since Cp2 and Cp3 are connected in parallel, Cp2 and Cp3 are each approximately 2 × (Vcc−G
ND).

Next, when all the switches are switched to the B side, as shown in FIG.
3 is connected in parallel to Cb23. Cp2 and Cp3 are
As described above, the battery is charged at 2 × (Vcc−GND). Therefore, 4 × (Vcc−GN) is applied between −V3B and VEE.
The voltage of D) is generated, and Cb23 is charged with this voltage.

For the above reasons, when all the switches repeat the switching operation continuously, VEE is
a voltage obtained by boosting GND six times in the negative direction based on cc, that is, Vcc
−6 × (Vcc−GND) occurs. For example, Vcc = 3V
In the case of -3V for -V3B and -15V for VEE
Voltage is generated.

FIG. 15 is a conceptual diagram showing another example of the charge pump circuit for boosting the negative direction six times. FIGS. 16 (a) and 16 (b) show SWa1 to SWa3 and SWa, respectively.
It is a connection relation diagram when b1 and SWb2 are switching to A side and B side. Cp1 to Cp3 are pumping capacitors, and Cb1 and Cb2 are backup capacitors.

As in FIG. 13, -V3B is a voltage obtained by boosting GND twice in the negative direction with respect to Vcc -2 ×
(Vcc-GND) occurs.

Here, when all the switches are switched to the A side, as shown in FIG.
The battery is charged with a voltage of (Vcc-GND). As shown in FIG. 15, the circuit including Cp2, Cb2, SWb23, and SWa2 is a negative direction double boosting circuit, like the circuit including Cp1, Cb1, SWb1, and SWa1. Therefore, Cb2 is also charged with a voltage of 2 × (Vcc−GND), and a voltage of −4 × (Vcc−GND) is generated in VEM. As a result, Cp3 becomes 4 × (Vcc−GN
It is charged with the voltage of D).

Next, when all the switches are switched to the B side, as shown in FIG. 16 (b), C is set between -V3B and VEE.
The connection relationship is such that p3 is inserted. The voltage of -V3B is-
2 × (Vcc−GND), and Cp3 is 4 × (Vcc−G
ND). Therefore, Vcc is Vcc
Is a voltage obtained by boosting GND six times in the negative direction based on
A voltage of -6 × (Vcc-GND) is generated.

The circuit of FIG. 13 is different from the circuit of FIG.
VEM which is a stable voltage between V3B and VEE
Is unnecessary, so that there is an advantage that the number of capacitors required is one less than that of the circuit of FIG. On the other hand, in the circuit of FIG. 15, since the switches connected to the positive electrodes of Cp2 and Cp3 are shared, there is an advantage that the number of switches required is one less (two as the number of transistors) than the circuit of FIG. There is. Further, by forming the intermediate voltage VEM, the drain withstand voltage of the transistor may be lower than that of the circuit of FIG. 13, and there is an advantage that the size of the transistor can be reduced.

<2.5> 3/2 boosting FIGS. 17A and 17B are conceptual diagrams of a 3/2 boosting charge pump circuit. CpH and CpL are pumping capacitors, and Cb is a backup capacitor. As shown in FIGS. 17 (a) and 17 (b), in this circuit, a state where CpH, CpL and Cb are connected in series and a state where Cb, CpH and CpL are connected in parallel are described. Repeated alternately. Assuming that the voltages applied to CpH and CpL are VcpH and VcpL, respectively, in FIG. 17B, since CpH and CpL are in a parallel state, VcpH = VcpL. Also,
As shown in FIG. 17 (b), CpH and CpL are Vcc-GN
When the D series connection is established, CpH and CpL have Vcc of 1
/ 2 voltage is charged. Thereafter, when the connection state shown in FIG. 17 (b) is reached, the electric charge stored in Vcc is supplied to Cb and CpL to Cb. By repeating this operation many times, all the voltages applied to Cb, CpH, and CpL approach 1/2 of Vcc, and as a result, a voltage obtained by boosting Vcc to 3/2 times is generated in the output voltage. I do.

<2.6> Negative 3 / 2-fold boosting FIGS. 18A and 18B are conceptual diagrams of a negative-direction 3 / 2-fold boosting charge pump circuit. Since the operation principle is the same as that of the above-mentioned 3/2 boosting, CpH, CpL, CpL
b is connected in series and Cb, CpH, Cp
By alternately repeating the state in which L is connected in parallel, the boosted voltage −3 /
2 × Vcc can be obtained.

The driver IC of the liquid crystal display device requires a logic voltage and a voltage on the negative side of the logic voltage. Therefore, by applying this circuit to such a liquid crystal display device, Power consumption can be reduced.

<2.7> 2/3 Step-Down The voltages applied to the CpL are all the same because they are connected in parallel in FIG. 19B, and are connected in series as shown in FIG. , Cb, CpH, and CpL are charged with approximately 1/3 of Vcc, respectively. By repeating this operation many times, Cb, CpH, CpL
Are approaching about 1/3 of Vcc,
As a result, a voltage lower than Vcc by (１ ／) × Vcc, that is, a voltage obtained by stepping down Vcc by 2/3 times is generated.

<2.8> Negative 2 / 3-fold step-down FIG. 20A and FIG. 20B are conceptual diagrams of a negative-direction 2 / 3-fold step-down charge pump circuit. The operating principle is 2 /
Since this is the same as the triple step-down, detailed description is omitted. 2
CpH, CpL and Cb
20 (a) connected in series with Cb,
By alternately repeating the state of FIG. 20B in which CpH and CpL are connected in parallel, a step-down voltage of − ×× Vcc is obtained in the reverse direction as in the case of 2/3 step-down. Can be.

<< 3 >> Modified Example of Embodiment <3.1> First Modified Example In the above-described embodiment, the phase is shifted for each frame. However, the present invention is not limited to this. The phase may be shifted every plural frames such as frames.

<3.2> Second Modification In the above embodiment, the reference signal input to the clock forming circuit 11 of the liquid crystal driving power supply circuit 10 is the latch signal LP used for the scanning signal. Is not limited to this,
For example, a shift clock or the like used for a data signal may be used.

<3.3> Third Modification In the above embodiment, as shown in FIGS. 5 and 6, the power supply circuit having a function of stopping the operation of the charge pump circuit by the control signal / Doff has been described. However, the stop control by the control signal / Doff may be omitted.

<3.4> Fourth Modification In the above-described embodiment, a liquid crystal display device is exemplified as an electro-optical device. However, the present invention is not limited to this, and various electro-optical effects such as an electro-luminescence element can be used. The present invention can be applied to an electro-optical device that performs display by using.

<3.5> Fifth Modification In the above-described embodiment, the case where the liquid crystal display panel 101 is driven by MLS driving has been described as an example. Of course, it may be possible.

<3.6> Sixth Modification Examples of the liquid crystal display device include an active matrix method using a TFD (non-linear two-terminal element) and a TFT (Thin Film Transistor), a TFD and a TFT, and the like. Various types, such as a passive matrix type that does not use a switching element, can be adopted.

<3.7> Seventh Modification In the above embodiment, the power supply circuit is described as including the charge pump circuit. However, the scope of application of the present invention is not limited to this. The present invention is also applicable to other switching power supplies that generate a drive voltage by performing a switching operation according to a latch signal LP.

<3.8> Eighth Modification In the above embodiment, the power supply circuit may be sold alone with the power supply circuit mounted on the electro-optical device, or may be sold alone.

<3.9> Ninth Modified Example Further, regardless of the number of scanning lines, the number of latch signals LP generated within one vertical scanning period may be set to be always an odd number.

Alternatively, the number of latch signals LP generated within one field period may be set to be always an odd number.

<3.10> Tenth Modification The power supply circuit described above may be used not only in a display device but also in a projector. Further, a personal computer, a pager, a liquid crystal television, a viewfinder type, and a monitor direct view It can also be applied to electronic devices such as video tape recorders, car navigation devices, electronic organizers, calculators, word processors, workstations, mobile phones, videophones, POS terminals, and devices with touch panels.

Further, a display device using the above-described power supply circuit can be used as a projector, a personal computer,
By using it in electronic devices such as pagers, liquid crystal televisions, video tape recorders of viewfinder type and monitor direct-view type, car navigation devices, electronic organizers, calculators, word processors, workstations, mobile phones, videophones, POS terminals, etc. The power consumption of equipment can be significantly reduced.

Here, an example in which the above-described electronic device is applied to a mobile phone will be described.

FIG. 21 is a perspective view showing the structure of the portable telephone. In the figure, a mobile phone 1300 includes a plurality of operation buttons 1302, an earpiece 1304, a mouthpiece 13
06, a liquid crystal display device (electro-optical device) 100 is provided. This liquid crystal display device 100 is also provided with a front light on its front face, if necessary. Also,
Even in this configuration, since the liquid crystal display device 100 is used as a reflection direct-view type, a configuration in which the pixel electrode 118 has unevenness is desirable.

[0113]

As described above, in the power supply circuit according to the present invention, the operation timing for generating the drive voltage every time the reference signal is generated twice is changed every time the vertical scanning period (or the horizontal scanning period) is switched. Since the reference signal is shifted by one period, the ripple superimposed on the drive signal can be canceled each time the vertical scanning period (or horizontal scanning period) is switched. Thereby, when this power supply circuit is used in, for example, a liquid crystal display device, display unevenness can be suppressed.

[Brief description of the drawings]

FIG. 1 is an overall configuration diagram illustrating a liquid crystal display device according to an embodiment of the present invention.

FIG. 2 is an explanatory diagram showing an electrode pattern of a liquid crystal display panel.

FIG. 3 is a waveform diagram showing scanning signals and data signals supplied to the liquid crystal display panel.

FIG. 4 is a block diagram showing a liquid crystal power supply circuit.

FIG. 5 is a block diagram showing a clock forming circuit.

FIG. 6 is a time chart illustrating a relationship between an input signal and an output signal to a clock forming circuit.

FIG. 7 is a circuit diagram showing a basic configuration of a charge pump circuit.

FIG. 8 is an explanatory diagram showing a state in which the phase of a drive signal is shifted for each frame.

FIG. 9 is an explanatory diagram showing a state where the phase of a drive signal is shifted for each field.

FIG. 10 is a circuit diagram showing a charge pump circuit of double boosting.

FIG. 11 is a circuit diagram showing a charge pump circuit of double boosting in the negative direction.

FIG. 12 is a circuit diagram showing a charge pump circuit of 倍 -fold step-down.

FIG. 13 is a circuit diagram showing a charge pump circuit that boosts in the negative direction six times.

FIG. 14 is a circuit diagram showing the operation of a charge pump circuit that boosts in the negative direction six times.

FIG. 15 is a circuit diagram showing another charge pump circuit that boosts in the negative direction by six times.

FIG. 16 is a circuit diagram showing the operation of another charge pump circuit for boosting the negative direction six times.

FIG. 17 is a circuit diagram showing a charge pump circuit of 3/2 times boosting.

FIG. 18 is a circuit diagram showing a charge pump circuit that boosts in the negative direction by 3/2 times.

FIG. 19 is a circuit diagram showing a 2/3 step-down charge pump circuit.

FIG. 20 is a circuit diagram showing a charge pump circuit for stepping down in the negative direction by 2/3.

FIG. 21 is a perspective view illustrating a configuration of a mobile phone as an example of an electronic apparatus to which the liquid crystal display device is applied.

FIG. 22 is an explanatory diagram showing a ripple generated in a drive signal according to the related art.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Liquid crystal drive power supply circuit 11 ... Clock formation circuit 12 ... Negative direction 6 times booster circuit 14 ... Double booster circuit 15 ... Negative double booster circuit 16, 17 ... 1 / 2 step-down circuit 18: negative direction double booster circuit 100: liquid crystal display device 101: liquid crystal display panel 102: liquid crystal drive circuit 103: scanning line drive circuit 104: data line drive Circuit Cp: Charge capacitor Cb: Backup capacitor SWa, SWb: Switch

Continued on the front page F term (reference) 2H093 NA07 NA18 NA47 NC04 NC05 NC21 NC49 NC62 ND09 ND15 ND33 ND60 NF05 NF13 5C006 AA11 AF51 AF52 AF71 AF78 BB12 BF06 BF26 BF27 BF42 BF46 FA22 5C080 AA10 BB05 JJ05 FF03 JJ05 FF03

Claims (11)

[Claims] 1. A power supply circuit for supplying a driving voltage to an electro-optical device that performs image display by driving pixels for one screen every vertical scanning period, wherein the power supply circuit synchronizes with each horizontal scanning period in the vertical scanning period. A switching power supply unit that repeats an operation of generating a drive voltage every time the reference signal is generated twice, and an N vertical scanning period (where N is N) when the number of reference signals generated in the vertical scanning period is even And a correction means for shifting the timing of the operation of generating the driving voltage by the switching power supply means by one cycle of the reference signal every one (1 or more integer). 2. A power supply circuit for supplying a driving voltage to an electro-optical device which performs image display by driving pixels for one screen every vertical scanning period, wherein each horizontal line is repeated an even number of times during the vertical scanning period. A switching power supply unit that receives a reference signal synchronized in each scanning period and repeats an operation of generating a driving voltage every time the reference signal is generated twice, and in every N vertical scanning periods (N is an integer of 1 or more). A power supply circuit comprising: a correction unit that shifts a timing of a driving voltage generation operation by the switching power supply unit by one cycle of the reference signal. 3. A two-phase clock signal is supplied to a power supply circuit that supplies a driving voltage to an electro-optical device that performs image display by driving pixels for one screen every vertical scanning period. Switching power supply means for sequentially performing the switching operation and the second switching operation, generating a driving voltage and supplying the driving voltage to the electro-optical device, and a reference signal generated for each of a plurality of horizontal scanning periods in the vertical scanning period, Means for generating the two-phase clock signal and supplying it to the switching power supply means, wherein when the number of reference signals generated in the vertical scanning period is an even number, N vertical scanning periods (where N is one or more) 2)
And a clock signal generating means including means for inverting the order of each phase of the phase clock signal. 4. A two-phase clock signal is supplied to a power supply circuit for supplying a driving voltage to an electro-optical device for driving a pixel for one screen to display an image every vertical scanning period. Switching power supply means for sequentially performing the switching operation and the second switching operation to generate a driving voltage and supplying the driving voltage to the electro-optical device; Receiving the signal, generating the two-phase clock signal, and supplying the generated signal to the switching power supply means, wherein each of the two-phase clock signals is generated every N vertical scanning periods (N is an integer of 1 or more). Clock signal generating means including means for reversing the order. 5. The power supply circuit according to claim 1, wherein N = 1 in said N vertical scanning periods. 6. The power supply circuit according to claim 1, wherein said switching power supply means includes a charge pump for performing a step-up / step-down operation by said clock signal. 7. A plurality of data lines and a plurality of scanning lines intersecting with the plurality of data lines, the plurality of scanning lines being driven every vertical scanning period, and a plurality of horizontal scanning periods in each vertical scanning period An electro-optical device that drives each pixel interposed at the intersection of each data line and each scanning line by driving the plurality of data lines in each of the plurality of data lines, wherein a switching operation is performed according to a reference signal synchronized with the horizontal scanning period. And a power supply circuit for generating a drive voltage for driving a scanning line and a data line, wherein the number of the reference signals generated in the vertical scanning period is an odd number. apparatus. 8. A frame having a plurality of data lines and a plurality of scanning lines intersecting the plurality of data lines, dividing a frame to be a vertical scanning period to drive the plurality of scanning lines for each field, and An electro-optical device that drives each pixel interposed at an intersection of each data line and each scanning line by driving the plurality of data lines in each of a plurality of horizontal scanning periods within the period; A power supply circuit that generates a drive voltage for driving a scanning line and a data line by performing a switching operation in accordance with a reference signal synchronized with the reference signal, wherein the number of the reference signals generated in the field is an odd number An electro-optical device comprising: 9. A plurality of data lines and a plurality of scanning lines intersecting the data lines, the plurality of data lines being driven in each of the vertical scanning periods, and a plurality of horizontal scanning periods in each of the vertical scanning periods An electro-optical device that drives each pixel at the intersection of each data line and each scanning line by driving the plurality of data lines in each of the plurality of data lines. And a power supply circuit for generating a drive voltage for driving the scanning line and the data line. The power supply circuit receives a two-phase clock signal to perform the first switching operation and the second switching operation. A switching power supply unit for sequentially performing a switching operation to generate a driving voltage and supplying the driving voltage to the electro-optical device; Means for generating the two-phase clock signal in accordance with the reference signal to be supplied to the switching power supply means, wherein the number of reference signals generated in the vertical scanning period is an even number in the N vertical scanning period ( N is an integer of 1 or more).
And a clock signal generating means including means for inverting the order of each phase of the phase clock signal. 10. The electro-optical device according to claim 9, wherein N = 1 in the first N vertical scanning periods. 11. An electronic apparatus using the electro-optical device according to claim 7, 8, 9, or 10 for a display unit.