JP4514784B2 - Display device - Google Patents

Description

  The present invention relates to a display device that performs gradation display using an analog voltage generated by a digital / analog conversion device that converts digital data into an analog voltage.

  A digital / analog converter for converting digital data into an analog signal is generally used. Such a digital / analog conversion device is, for example, for executing gradation display in a display device in which each pixel includes a voltage-driven light-emitting element such as a liquid crystal display element or a self-luminous current-driven light-emitting element. It is used to generate an analog voltage (hereinafter also referred to as “gradation voltage”).

In such a display device, gradation display can be performed by setting the gradation voltage to an intermediate level between the maximum luminance (white) and the minimum luminance (black) in each pixel. That is, the gradation voltage is set in 2 ⁿ steps according to n-bit (n: natural number) digital data and transmitted to each pixel.

  As a general digital / analog conversion device, a type constituted by a plurality of resistance elements connected in a ladder shape is known (for example, Non-Patent Document 1). However, such a ladder-type digital / analog conversion device has a problem in that current consumption increases because direct current flows constantly.

  For this reason, for example, Patent Document 1 discloses a digital / analog conversion device that changes an output voltage stepwise by charge / discharge by a capacitive element using a charge pump circuit.

The digital / analog conversion device using the charge pump circuit disclosed in Patent Document 1 can reduce power consumption because no steady DC current is generated therein.
JP 2002-111499 A (FIGS. 7 and 8, pages 9 to 11) Yoshio Shirato, “All About Illustrated Analog IC”, 1st edition, Tokyo Denki University Press, November 1986, p. 258-260

  However, in the digital / analog conversion device using the charge pump circuit disclosed in Patent Document 1, the amount of change in the output voltage varies depending on the level of the output voltage Vout, as shown in FIG. . Specifically, as the output voltage Vout increases, the amount of voltage change per pulse input gradually saturates.

  For this reason, when it is desired to set the output voltage Vout at equal intervals, it is expected that the number of input clocks to the charge pump circuit will need to be controlled according to the level of the output voltage Vout. Is concerned. This problem is expected to become prominent when the digital / analog conversion is used to generate gradation voltages in the display device.

  The present invention has been made to solve such problems, and an object of the present invention is to provide an output according to the number of input pulses in a low power consumption digital / analog converter by operation of a charge pump circuit. It is to provide a configuration for setting the analog voltage to be set at equal intervals and a display device provided with such a digital / analog conversion device.

  The display device according to the present invention is a display device that performs gradation display based on display data composed of weighted n bits (n: an integer of 2 or more), each corresponding to a supplied voltage. A plurality of pixel circuits configured to perform display, a selection line for selecting the plurality of pixel circuits, a data line connected to the plurality of pixel circuits, and a gradation that is an analog voltage corresponding to display data A gradation voltage generating circuit for supplying a voltage to the data line, the gradation voltage generating circuit including a first transition edge that changes from an initial level to a predetermined level and a second that returns from the predetermined level to the initial level. A pulse number control circuit for supplying the number of pulses including a transition edge to the first node in the number corresponding to the display data, and an output node connected to the data line every time one pulse is applied to the first node. And a charge pump circuit for varying the voltage stepwise.

  A display device according to another configuration of the present invention is a display device that performs gradation display based on display data composed of weighted n bits (n: an integer of 2 or more), each supplied A plurality of pixel circuits configured to perform display in accordance with a voltage, a data line connected to the plurality of pixel circuits, and a gradation voltage which is an analog voltage corresponding to display data is supplied to the data line A gradation voltage generation circuit, and the gradation voltage generation circuit continuously receives a pulse including a first transition edge that changes from an initial level to a predetermined level and a second transition edge that returns from the predetermined level to the initial level. In response to the specific bit of the n bits, the pulse control unit that outputs one of the pulse and the inverted pulse obtained by inverting the pulse, and the pulse and the inverted pulse output from the pulse control. In response, the pulse number control circuit for transmitting the number of pulses or inversion pulses corresponding to the display data to the first node, and the connection to the data line in response to each of the pulses transmitted to the first node And a second output connected to the data line in response to each of the inversion pulse transmitted to the first node. And a second charge pump circuit for stepwise dropping the voltage of the node.

  The display device according to the present invention can generate an analog voltage for gradation display that is set stepwise according to weighted display data of a plurality of bits by using a charge pump circuit with low power consumption. .

  Further, in the display device, the ascending charge pump circuit and the descending charge pump circuit are selectively operated to generate an analog voltage for gradation display. Compared with a configuration using only one of the circuits, the generation of the gradation voltage can be speeded up.

Hereinafter, embodiments of the present invention will be described in detail with reference to the drawings. In the following description, the same reference numerals indicate the same or corresponding parts.

[Embodiment 1]
FIG. 1 is a circuit diagram showing a configuration of digital / analog converting apparatus 10 according to the first embodiment of the present invention.

  Referring to FIG. 1, digital / analog converting apparatus 10 according to the first embodiment includes a pulse number control circuit 20, a charge pump circuit 30, and precharge switches 51 to 53 functioning as a precharge circuit. The digital / analog converter 10 generates an analog voltage VNo corresponding to the input digital data to the output node No to which the output capacitor 5 is connected.

  Hereinafter, in the embodiment of the present invention, when the input digital data is 4 bits, that is, the data bit D0 is the least significant digit (LSB) and the data bit D3 is the most significant digit (MSB). A case where input digital data is constituted by data bits D0 to D3 will be described representatively.

  Note that the number of bits of input digital data is not limited to such a case, and as will be apparent from the following description, the digital / analog converter according to the present invention corresponds to digital data of an arbitrary number of bits. It is possible to configure.

  The pulse number control circuit 20 includes switches 22 to 25 that constitute a switch circuit, and a switch control circuit 27. The switches 22 to 25 are connected in parallel between the node 21 to which the pulse CP is continuously supplied and the node N1.

  The switch control circuit 27 generates control signals D0C to D3C that respectively control the ON periods of the switches 22 to 25 according to the data bits D0 to D3.

  The switch 22 is turned on when the control signal D0C is at a logic high level (hereinafter simply referred to as “H level”), and is turned off when the control signal D0C is at a logic low level (hereinafter also simply referred to as “L level”). To do. Similarly, the switches 23 to 25 are turned on or off in response to the control signals D1C to D3C, respectively. Each of switches 22 to 25 transmits pulse CP from node 21 to node N1 when turned on.

  The charge pump circuit 30 includes a pump capacitor 32 connected between the nodes N1 and N2, a switch element 34 connected between the node N2 and the output node No, a power supply node NR and a node to which a predetermined voltage VR is supplied. And a bias circuit 40 provided between N2.

  The switch element 34 is formed of, for example, a p-type transistor, an n-type transistor, or a combination of both connected in parallel, and is turned on / off in response to the control signal φ1. Bias circuit 40 has an n-type transistor 41 connected between power supply node NR and node N2. The gate of n-type transistor 41 is connected to output node No.

  Precharge switches 51, 52 and 53 are connected between nodes N1 and N2, output node No and power supply node NL to which a predetermined low voltage VDL is supplied. Each of precharge switches 51-53 is turned on / off in response to precharge signal φp. Here, the low voltage VDL corresponds to, for example, the lowest level of the control range of the output voltage VNo generated according to the input digital data. The predetermined voltage VR is at least higher than the low voltage VDL.

  The output node No has an output capacitor 5 connected to a predetermined voltage Vss (typically ground voltage). In the following, the capacity value of the pump capacity 32 is Cp and the capacity value of the output capacity 5 is Co.

First, the operation of the pulse number control circuit 20 will be described.
FIG. 2 is a circuit diagram showing a configuration of switch control circuit 27 shown in FIG.

  Referring to FIG. 2, switch control circuit 27 includes logic gates 28a to 28d that generate control signals D0C to D3C, respectively. Logic gate 28a generates an AND logic operation result of control signal C0 and data bit D0 as control signal D0C, and logic gate 28b generates an AND logic operation result of control signal C1 and data bit D1 as control signal D1C. Similarly, logic gate 28c generates an AND logic operation result of control signal C2 and data bit D2 as control signal D2C, and logic gate 28d generates an AND logic operation result of control signal C3 and data bit D3 as control signal D3C. Generate.

FIG. 3 is an operation waveform diagram for explaining the operation of the pulse number control circuit 20.
Referring to FIG. 3, node CP shown in FIG. 1 has a pulse CP including a transition edge (rising edge) from L level to H level and a transition edge (falling edge) from H level to L level. Is supplied continuously. As an example, one cycle T includes (2 ⁿ −1) (15 in FIG. 3) pulses CP corresponding to the number of bits n of the digital signal.

  In each cycle T, the control signal C0 corresponding to the data bit D0 of the least significant digit is set to the H level during the time ta to tb including one pulse CP, and is set to the L level in other periods. . Similarly, the control signal C1 is set to the H level from time tb to tc so as to include two pulses CP in the H level period, and is set to the L level during other periods, and the control signal C2 is set to the H level. It is set to the H level from time tc to td so as to include four pulses CP in the period. Further, the control signal C3 corresponding to the most significant data bit D3 is set to the H level from time td to te so as to include eight pulses CP in the H level period.

  In this way, at the timing when each pulse CP is transmitted to the node 21 during one cycle T, one of the control signals C0 to C3 is set to the H level, and the rest is set to the L level. The H level period of the control signals C0 to C3 is set to a power ratio of 2 according to bit weighting, that is, 1: 2: 4: 8.

  Therefore, in the pulse number control circuit 20 shown in FIG. 1, the data bits D0 to D3 are “0” between the times ta and tb, between tb and tc, between tc and td, and between td and te. When the corresponding data bits D0 to D3 are “1” while the pulse CP is not transmitted to the node N1, the number of pulses CP corresponding to the H level period of the control signals C0 to C3 is set to the node N1, respectively. N1 is transmitted.

  As a result, in one cycle T, the number of pulses CP transmitted from the node 21 to the node N1 by the pulse number control circuit 20 is set to “D0 + 2 · D1 + 4 · D2 + 8 · D3”.

Next, the operation of the digital / analog converter 10 will be described with reference to FIG.
Referring to FIG. 4, before the output operation of output voltage VNo, precharge signal φp is set to the H level for a predetermined period (between times t0 and t1), and each of nodes N1, N2 and output node No has a low voltage. Precharged to VDL. As a result, the voltage VN1 at the node N1, the voltage VN2 at the node N2, and the output voltage VNo at the output node No are set to VN1 = VN2 = VNo = VDL. Hereinafter, the voltage of each node or the like is shown as a voltage with respect to the low voltage VDL (that is, VDL = 0 (V)).

  Due to the transmission of the first pulse CP, the voltage VN1 at the node N1 rises from the low voltage VDL to V1 between times t3 and t5. On the other hand, the switching element 34 is turned on at the timing (time t3) when the rising edge of the pulse CP is transmitted to the node N1, and is turned off at the timing (time t5) when the falling edge is transmitted. In the period t4, the control signal φ1 is set to the H level. The switch element 34 is turned on during the H level period of the control signal φ1, and is turned off during the L level period.

  At time t <b> 3, the increase V <b> 1 of the voltage VN <b> 1 is transmitted to the node N <b> 2 and the output node No connected by the switch element 34 by capacitive coupling via the pump capacitor 32. As a result, the voltages VN2 and VNo are increased by V2. Here, the voltage increase V2 is expressed by equation (1).

V2 = V1 · Cp / (Cp + Co) (1)
At time t4, the control signal φ1 is set to L level, the switch element 34 is turned off, and the falling edge of the pulse CP is transmitted to the node N1 at time t5, whereby the voltage VN1 decreases by V1. In response to this, the voltage VN2 drops by V1 due to capacitive coupling, but the output voltage VNo is maintained at V2 because the switch element 34 is turned off.

  In response to the decrease in the voltage VN2, the n-type transistor 41 constituting the bias circuit 40 becomes conductive. Here, by setting the predetermined voltage VR so that the n-type transistor 41 operates in the saturation region, the n-type transistor 41 operates in the source follower mode. Thereby, since the gate voltage of the n-type transistor 41 (that is, the output voltage VNo) is V2, the voltage VN2 of the node N2 is returned to “V2−VTN” by the bias circuit 40. Here, VTN is the threshold voltage of the n-type transistor 41. Thus, the bias circuit 40 changes the voltage VN2 of the node N2 with the same polarity in accordance with the change of the voltage VNo of the output node No.

  From time t7 to t9, the next pulse CP is transmitted to the node N1. Control signal φ1 is set to the H level again between times t6 and t8 including the rising edge (time t7) and not including the falling edge (time t9).

  Before the time t6, the voltage VN2 of the node N2 = V2−VTN and the output voltage VNo = V2, and therefore, from the output node No having a high potential to the node in response to the turn-on of the switch element 34 at the time t6. An AC current flows on the N2 side. As a result, while the voltage VN2 increases by VA, the output voltage VNo decreases by VB and VN2 = VNo. The voltage change amounts VA and VB are determined by the capacitance values Cp and Co.

  FIG. 5 is a circuit diagram showing the internal state of the charge pump circuit around time t6 in FIG. 4, specifically, the state of node N2 and output node No.

  Referring to FIG. 5, when switch element 34 is turned on in response to control signal φ1 at time t6, node N2 and output node No become the same voltage VX. Before and after the switch element 34 is turned on, charge exchange with other parts does not occur, so the charge conservation law is established, and the voltage VX is expressed by the following equation (2).

Cp · (V2−VTN) + Co · V2 = (Cp + Co) · VX (2)
From the equation (2), the voltage VX is given by the following equation (3).

VX = (Cp.V2 + Co.V2-Cp.VTN) / (Cp + Co)
= V2-Cp.VTN / (Cp + Co) (3)
Accordingly, the voltage drop amount VB of the output node No shown in FIG. 4 is expressed by the following equation (4).

VB = Cp · VTN / (Cp + Co) (4)
By executing the same charge pump in response to the transmission of the next pulse CP at time t7 to t9, the output voltage VNo = 2 · V2-VB at the end of the second charge pump operation. Further, when the third pulse CP is transmitted to the node N1 at times t11 to t13, the output voltage VNo = 3 · V2-2 · VB.

  Thus, the output voltage VNo is set to the following equation (5) in response to the number m (m: natural number) of the pulses CP transmitted to the node N1 by the pulse number control circuit 20.

VNo = m.V2- (m-1) .VB (5)
Therefore, the voltage change amount ΔV of the output node No per pulse CP is ΔV = V2−VB, which is a constant value independent of the level of the output voltage VNo.

  As described above, the digital / analog conversion device 10 according to the first embodiment can obtain the output voltage VNo proportional to the number of transmission pulses to the charge pump circuit 30 set according to the digital data. Thereby, an analog voltage set at equal intervals and in steps can be obtained by a digital / analog conversion device with low power consumption and a simple circuit configuration.

[Modification of Embodiment 1]
FIG. 6 is a circuit diagram showing a configuration of digital / analog converter 11 according to the modification of the first embodiment.

  Referring to FIG. 6, digital / analog conversion device 11 according to the modification of the first embodiment includes a pulse number control circuit 20 as compared with digital / analog conversion device 10 according to the first embodiment shown in FIG. Instead, the difference is that a pulse number control circuit 20 # is provided. Since the configuration of the other parts is similar to that of digital / analog converting apparatus 10 according to the first embodiment, detailed description will not be repeated.

  Compared with pulse number control circuit 20 shown in FIG. 1, pulse number control circuit 20 # includes a switch control circuit 27 # instead of switch control circuit 27, and a switch between node 21 and node N1. The difference is that switches 22 # to 25 # are further connected in series with 22 to 25, respectively.

  Switch control circuit 27 # transmits control signals C0-C3 shown in FIG. 3 to switches 22-25, respectively, and switches 22-25 are turned on / off in response to control signals C0-C3, respectively.

  Switches 22 # -25 # are turned on / off in response to the levels of data bits D0-D3. Specifically, each of switches 22 # to 25 # is turned on when corresponding data bits D0 to D3 are "1", and turned off when "0".

  Therefore, according to the configuration of pulse number control circuit 20 # shown in FIG. 6, similarly to pulse number control circuit 20, a number of pulses CP corresponding to data bits D0 to D3 are transmitted from node 21 to node N1, Input to the charge pump circuit 30 is possible.

  As a result, similarly to the configuration according to the first embodiment, analog voltages set at equal intervals and in steps can be obtained by the digital / analog conversion device with low power consumption and a simple circuit configuration.

[Embodiment 2]
Output voltage VNo of the digital / analog conversion device according to the first embodiment and its modification includes terms of capacitance values Cp, Co and threshold voltage VTN as shown in the above equation (4). Usually, the temperature dependence of the capacitance values Cp and Co is small and is canceled in the term of Cp / (Cp + Co) in the equation (4). On the other hand, since the threshold voltage VTN has a relatively large temperature dependence, if the operating temperature of the digital / analog converter rises, the output voltage VNo will fluctuate accordingly. In the second embodiment, a configuration for solving such problems will be described.

  FIG. 7 is a circuit diagram showing a configuration of digital / analog conversion device 12 according to the second embodiment of the present invention.

  Referring to FIG. 7, digital / analog conversion device 12 according to the second embodiment includes charge pump circuit 130 instead of charge pump circuit 30 as compared with digital / analog conversion device 10 shown in FIG. 1. It is different. The charge pump circuit 130 is different from the charge pump circuit 30 in that it includes a bias circuit 140 instead of the bias circuit 40.

  The bias circuit 140 further includes a current limiting element 42 and a p-type transistor 43 in addition to the n-type transistor 41. Current limiting element 42 and p-type transistor 43 are connected in series between power supply nodes that receive supply of different voltages. In FIG. 7, the current limiting element 42 and the p-type transistor 43 are connected between the power supply node NR and the ground node. However, if a predetermined operation described below is possible, a power supply to which another voltage is supplied. You can also connect between nodes.

  The gate of p-type transistor 43 is connected to output node No, and node N 3 corresponding to the connection node of current limiting element 42 and p-type transistor 43 is connected to the gate of n-type transistor 41.

  Since the configuration of other parts of digital / analog converter 12 is the same as that of digital / analog converter 10 shown in FIG. 1, detailed description will not be repeated.

  The current limiting element 42 is typically composed of a resistance element, and by setting the resistance value of the resistance element sufficiently higher than the conduction resistance value of the p-type transistor 43, the node N3 is hardly increased. The voltage VN3 can be set to the following equation (6).

V3 = VNo + | VTP | (6)
Here, | VTP | is the absolute value of the threshold voltage of the p-type transistor 43. As a result, a voltage higher than the output voltage VNo by | VTP | is input to the gate of the n-type transistor 41. As a result, the term (V2−VTN) in the above equation (2) is replaced with (V2−VTN + | VTP |). As a result, voltage VB shown in equation (4) is expressed by equation (7) below in the digital / analog converter according to the second embodiment.

VB = Cp · (VTN− | VTP |) / (Cp + Co) (7)
The temperature coefficient of the absolute value of the threshold voltage of the n-type transistor 41 and the p-type transistor 43 is obtained by the so-called pairing effect by making the n-type transistor 41 and the p-type transistor 43 close by the same manufacturing process. Can be almost the same. As a result, the temperature dependency of the term (VTN− | VTP |) in the equation (7) is canceled out.

  As a result, the digital / analog conversion device according to the second embodiment can suppress the temperature dependence of the output voltage in addition to the effects exhibited by the digital / analog conversion device according to the first embodiment.

[Modification of Embodiment 2]
FIG. 8 is a circuit diagram showing a configuration of digital / analog converter 13 according to the modification of the second embodiment.

  Referring to FIG. 8, digital / analog conversion device 13 according to the modification of the second embodiment is different from digital / analog conversion device 12 shown in FIG. 7 in that charge pump circuit 131 is substituted for charge pump circuit 130. It differs in that it is equipped with. The charge pump circuit 131 is different from the charge pump circuit 130 in that it includes a bias circuit 141 instead of the bias circuit 140.

  The bias circuit 141 is different from the bias circuit 140 shown in FIG. 7 in that the current limiting element 42 is composed of a constant current source 44. The constant current source 44 supplies a constant small current to the node N3, and this small current flows to the ground node via the p-type transistor 43. As a result, the voltage at the node N3 is set in the same manner as in FIG.

  In particular, by using the constant current source 44 as the current limiting element 42, the relationship between the voltage VN3 of the node N3 and the output voltage VNo can be kept constant without depending on the voltage difference between the node N3 and the power supply node NR. . In other words, in the digital / analog conversion device 12 of FIG. 7 including the bias circuit 140, the amount of voltage drop at the current limiting element 42 formed of a resistance element may change according to the output voltage VNo. The temperature dependency of the voltage VNo is slightly inferior to the digital / analog converter 13 shown in FIG.

  As described above, in the digital / analog conversion device according to the modification of the second embodiment, in addition to the effect exhibited by the digital / analog conversion device according to the second embodiment, the stepwise voltage change amount ΔV of the output voltage VNo is expressed as a temperature. The dependency can be further suppressed and set accurately.

[Embodiment 3]
In the digital / analog conversion device according to the second embodiment and the modification thereof, as understood from the equation (7), the voltage VB affecting the output voltage VNo includes the term (VTN− | VTP |).

  Each of the threshold voltages VTN and | VTP | of the transistor may vary due to process variations during manufacturing. If the value of (VTN− | VTP |) varies due to this influence, the level of the output voltage VNo may vary due to variations in transistor characteristics (threshold voltage). In the configuration according to the third embodiment, a configuration for solving such problems and setting the output voltage VNo with higher accuracy will be described.

  FIG. 9 is a circuit diagram showing a configuration of digital / analog conversion device 14 according to the third embodiment of the present invention.

  Referring to FIG. 9, digital / analog conversion device 14 according to the third embodiment includes charge pump circuit 132 instead of charge pump circuit 130 as compared with digital / analog conversion device 12 shown in FIG. 7. It is different. The charge pump circuit 132 is different from the charge pump circuit 130 in that it includes a bias circuit 142 instead of the bias circuit 140.

  Compared to bias circuit 140 shown in FIG. 7, bias circuit 142 is connected between n-type transistor 41 and node N2, and between node N3 and p-type transistor 43. And the n-type transistor 46. P-type transistor 45 is diode-connected, and its gate is connected to node N2. Similarly, n-type transistor 46 is also diode-connected, and its gate is connected to node N3.

  Since the configuration of other parts of digital / analog converter 14 is the same as that of digital / analog converter 12 shown in FIG. 7, detailed description thereof will not be repeated.

In the bias circuit 142, the voltage V3 at the node N3 is expressed by the following equation (8).
V3 = VNo + VTN + | VTP | (8)
That is, a voltage larger than the output voltage VNo by VTN + | VTP | is applied to the gate of the n-type transistor 41. On the other hand, by connecting the diode-connected p-type transistor 45, the term (V2-VTN) in the above equation (2) becomes (V2-VTN- | VTP |). As a result, the term (V2-VTN) in the above equation (2) is replaced with V2, so that VB = 0 in the equation (4) can be obtained.

  As a result, the output voltage VNo in the digital / analog conversion device 14 according to the third embodiment is expressed by the following equation (9) depending only on V2 expressed by the equation (1).

VNo = m · V2 (9)
As a result, in the digital / analog conversion device according to the third embodiment, in addition to the effect exhibited by the digital / analog conversion device according to the first embodiment, the influence of the manufacturing variation of the threshold voltage of the transistor is eliminated, and the output The voltage VNo can be generated more accurately. Further, since it becomes easy to secure ΔV, the output voltage range can be widened.

[Modification of Embodiment 3]
FIG. 10 is a circuit diagram showing a configuration of digital / analog conversion device 15 according to a modification of the third embodiment.

  Referring to FIG. 10, digital / analog converter 15 according to the modification of the third embodiment is different from digital / analog converter 14 shown in FIG. 9 in that charge pump circuit 133 is used instead of charge pump circuit 132. It differs in that it is equipped with. The charge pump circuit 133 is different from the charge pump circuit 132 in that it includes a bias circuit 143 instead of the bias circuit 142.

  The bias circuit 143 is different from the bias circuit 142 shown in FIG. 9 in that the current limiting element 42 is composed of a constant current source 44. Since constant current source 44 is the same as that described in FIG. 8, detailed description thereof will not be repeated.

  As described above, by using the constant current source 44 as the current limiting element 42, in the digital / analog conversion device according to the modification of the third embodiment, in addition to the effects exhibited by the digital / analog conversion device according to the third embodiment, The output voltage VNo can be accurately set while further suppressing the temperature dependency.

  In the digital / analog converters 11 to 15 according to the second and third embodiments and the modifications thereof, the configuration including the pulse number control circuit 20 shown in FIG. 1 is described. However, these digital / analog converters are described. However, the pulse number control circuit 20 # shown in FIG. 6 can be used in place of the pulse number control circuit 20.

[Embodiment 4]
In the fourth embodiment, for the digital / analog converters 10 to 15 shown in the first to third embodiments and their modifications, the output voltage VNo is opposite in polarity, that is, in response to the input of each pulse CP. The configuration of the digital / analog conversion device that descends in stages will be described.

  FIG. 11 is a circuit diagram showing a configuration example of digital / analog conversion device 10 # according to the first configuration example of the fourth embodiment.

  Referring to FIG. 11, digital / analog conversion device 10 # has a configuration corresponding to digital / analog conversion device 10 shown in FIG. 1, and has a reverse polarity with respect to output voltage VNo.

  Digital / analog conversion device 10 # includes a pulse number control circuit 20 (or 20 #), a charge pump circuit 30 #, and precharge switches 51-53. Charge pump circuit 30 # has a pump capacitor 32, a switch element 34, and a bias circuit 40 #.

  Bias circuit 40 # has p-type transistor 41 # connected between power supply node NR # and node N2. The gate of p-type transistor 41 # is connected to output node No. Precharge switches 51-53 are respectively connected between power supply node NH to which high voltage VDH is supplied and nodes N1, N2 and output node No, and are turned on / off in response to precharge signal φp.

  Since the configuration and operation of pulse number control circuit 20 or 20 # are the same as those described in the first embodiment and its modifications, detailed description will not be repeated.

  High voltage VDH corresponds to, for example, the highest level of the control range of output voltage VNo generated according to input digital data, and power supply node NR # is supplied with a predetermined voltage VR # lower than at least high voltage VDH. The

  Charge pump circuit 30 # operates in the reverse characteristic to the operation waveform of charge pump circuit 30 shown in FIG. 4, and responds to the falling edge of pulse CP every time one pulse CP is transmitted to node N1. Thus, the output voltage VNo is decreased step by step by ΔV.

  Therefore, digital / analog conversion device 10 # according to the fourth embodiment enjoys the same effect as digital / analog conversion device 10 shown in FIG. 1, and is set at equal intervals and stepwise according to digital data. Analog voltage can be generated.

  FIG. 12 is a circuit diagram showing a configuration example of the digital / analog conversion device 12 # of the second configuration example according to the fourth embodiment.

  Referring to FIG. 12, digital / analog converting device 12 # includes a charge pump circuit 130 # in place of charge pump circuit 30 #, as compared to digital / analog converting device 10 # shown in FIG. Different. Charge pump circuit 130 # differs from charge pump circuit 30 # in that it includes a bias circuit 140 # instead of bias circuit 40 #.

  Bias circuit 140 # further includes a current limiting element 42 and an n-type transistor 43 # in addition to p-type transistor 41 #. Current limiting element 42 and n-type transistor 43 # are connected in series between power supply nodes receiving different voltages. In FIG. 12, current limiting element 42 and n-type transistor 43 # are connected between power supply node NR # and power supply node NH, but can also be connected to a power supply node to which another voltage is supplied.

  Since the configuration of other parts of digital / analog conversion device 12 # is similar to that of digital / analog conversion device 10 # shown in FIG. 11, detailed description thereof will not be repeated.

  In other words, digital / analog conversion device 12 # has a configuration corresponding to digital / analog conversion device 12 shown in FIG. 7, and has an opposite polarity with respect to output voltage VNo. Therefore, digital / analog conversion device 12 # according to the fourth embodiment enjoys the same effect as digital / analog conversion device 12 according to the second embodiment, and is set at equal intervals and stepwise according to the digital data. Analog voltage can be generated.

  FIG. 13 is a circuit diagram showing a configuration example of a digital / analog conversion device 13 # of the third configuration example according to the fourth embodiment.

Referring to FIG. 13, digital / analog conversion device 13 # includes charge pump circuit 131 # instead of charge pump circuit 130 #, as compared with digital / analog conversion device 12 # shown in FIG. Different. Charge pump circuit 131 # differs from charge pump circuit 130 # in that it includes a bias circuit 141 # instead of bias circuit 140 #. The bias circuit 141 # is different from the bias circuit 140 # shown in FIG. 12 in that the current limiting element 42 is formed of a constant current source 44. That is, the digital / analog converter 13 # is similar to the bias circuit 141 # shown in FIG. And the output voltage VNo has a reverse polarity. That is, the difference between digital / analog converters 12 # and 13 # is the same as the difference between digital / analog converters 12 and 13. Therefore, digital / analog conversion device 13 # has temperature dependency in addition to the effect exhibited by digital / analog conversion device 12 # of FIG. 12, similarly to digital / analog conversion device 13 according to the modification of the second embodiment. Further, the output voltage VNo can be accurately set with suppression.

  FIG. 14 is a circuit diagram showing a configuration example of a digital / analog conversion device 14 # of the fourth configuration example according to the fourth embodiment.

  Referring to FIG. 14, digital / analog conversion device 14 # includes a charge pump circuit 132 # instead of charge pump circuit 130 #, as compared with digital / analog conversion device 12 # shown in FIG. Different. Charge pump circuit 132 # differs from charge pump circuit 130 # in that it includes a bias circuit 142 # instead of bias circuit 140 #.

  Bias circuit 142 # is different from bias circuit 140 # shown in FIG. 12 in that n-type transistor 45 # connected between p-type transistor 41 # and node N2, and node N3 and n-type transistor 43 #. And p-type transistor 46 # connected between them. N-type transistor 45 # is diode-connected, and its gate is connected to node N2. Similarly, p-type transistor 46 # is also diode-connected and its gate is connected to node N3.

  Since the configuration of other parts of digital / analog conversion device 14 # is similar to that of digital / analog conversion device 12 # shown in FIG. 12, detailed description thereof will not be repeated. That is, digital / analog conversion device 14 # has a configuration corresponding to digital / analog conversion device 14 shown in FIG. 9, and has an opposite polarity with respect to output voltage VNo.

  Therefore, digital / analog conversion device 14 #, like digital / analog conversion device 14 according to the third embodiment, produces transistor threshold voltages in addition to the effects exhibited by digital / analog conversion device 10 # of FIG. The output voltage VNo can be generated more accurately by eliminating the influence of variation. Further, since it becomes easy to secure ΔV, the output voltage range can be widened.

  FIG. 15 is a circuit diagram showing a configuration example of a digital / analog conversion device 15 # of the fifth configuration example according to the fourth embodiment.

  Referring to FIG. 15, digital / analog conversion device 15 # includes charge pump circuit 133 # in place of charge pump circuit 132 #, as compared to digital / analog conversion device 14 # shown in FIG. Different. Charge pump circuit 133 # differs from charge pump circuit 132 # in that it includes a bias circuit 143 # instead of bias circuit 142 #. Bias circuit 143 # is different from bias circuit 142 # shown in FIG. 12 in that current limiting element 42 is formed of constant current source 44.

  That is, digital / analog conversion device 15 # has a configuration corresponding to digital / analog conversion device 15 shown in FIG. 10, and has an opposite polarity with respect to output voltage VNo. That is, the difference between digital / analog converters 14 # and 15 # is the same as the difference between digital / analog converters 14 and 15. Therefore, digital / analog conversion device 15 # has temperature dependency in addition to the effect exhibited by digital / analog conversion device 14 # of FIG. 14, similarly to digital / analog conversion device 15 according to the modification of the third embodiment. Furthermore, it is possible to set the output voltage VNo more accurately by suppressing it.

[Embodiment 5]
In the digital / analog conversion device according to the first to third embodiments and the modifications thereof and the fourth embodiment, the level of output voltage VNo is affected by the capacitance value Cp of the pump capacitance and the capacitance value Co of the output capacitance. Therefore, in order to precisely set the output voltage VNo, it is preferable that these capacitance values Cp and Co can be adjusted.

  FIG. 16 is a circuit diagram showing a configuration of a digital / analog conversion device according to the fifth embodiment.

  Referring to FIG. 16, digital / analog converting device 16 according to the fifth embodiment includes a pulse number control circuit 20 (or 20 #), a pump capacitor 32 and a circuit block 35 constituting a charge pump circuit, An output voltage VNo that is an analog voltage corresponding to the input digital data is generated at the output node No to which the output capacitor 5 is connected. The circuit block 35 generally indicates a circuit portion obtained by removing the pump capacitor 32 from the charge pump circuits 30, 131 to 133 (or 30 #, 131 # to 133 #) described so far.

  In the configuration according to the fifth embodiment, pump capacity 32 and output capacity 5 have a configuration that can be finely adjusted in response to an external input. Pump capacity 32 includes a plurality of regulating units 36 connected in parallel between nodes N1 and N2. Each adjustment unit 36 includes a unit capacitor SCa and a link element LKa connected in series between nodes N1 and N2.

  Similarly, the output capacitor 5 includes a plurality of adjustment units 37 connected in parallel between the predetermined voltage Vss and the output node No. Each adjustment unit 37 includes a unit capacitor SCb and a link element LKb connected in series between the predetermined voltage Vss and the output node No.

  Each link element LKa selectively sets the formation and non-formation of the electric path including the corresponding unit capacitor SCa between the nodes N1 and N2 in response to the program input from the outside of the adjustment unit 36 independently of each other. Is possible. Similarly, each link element LKb is formed independently of each other in response to a program input from the outside of the adjustment unit 37 to form and non-connect an electric path including the corresponding unit capacitor SCb between the output node No and the predetermined voltage Vss. Formation can be selectively set.

  As the link elements LKa and LKb, it is possible to apply a laser fuse blown using laser light irradiation as a program input, an electric fuse blown using high voltage application as a program input, or the like. Alternatively, the link element can be configured by an antifuse element that changes from a non-conducting state to a conducting state by using a high voltage application for breaking the insulating film as a program input.

  With such a configuration, in the digital / analog conversion device according to the fifth embodiment, the capacitance value Cp of the pump capacitor 32 and the capacitance value Co of the output capacitor 5 that affect the level of the output voltage VNo are supplied from the outside. It can be adjusted in steps by program input. As a result, the level of the output voltage VNo can be finely adjusted to obtain a more accurate analog voltage.

[Embodiment 6]
In the sixth embodiment, a configuration for supplying a gray scale voltage in a display device using the digital / analog conversion device based on the charge pump operation described in the first to fifth embodiments and modifications thereof will be described. .

FIG. 17 is a block diagram showing an overall configuration of a display device according to the sixth embodiment.
Referring to FIG. 17, display device 200 according to the sixth embodiment includes display panel unit 220, gate driver 230, and source driver 240. 17 illustrates the configuration of the display device in which the gate driver 230 and the source driver 240 are integrally formed with the display panel unit 220. However, these circuit portions are external circuits of the display panel unit 220. It is also possible to provide it.

  The display panel unit 220 includes a plurality of pixel circuits 225 arranged in a matrix. A gate line GL is arranged corresponding to each pixel circuit row (hereinafter also referred to as “pixel row”), and a data line DL is provided corresponding to each pixel circuit column (hereinafter also referred to as “pixel column”). . FIG. 17 representatively shows the pixel circuits in the first and second columns of the first row, and the corresponding gate lines GL1 and data lines DL1 and DL2.

  Each pixel circuit 225 includes a switch element 226 provided between the corresponding data line DL and the pixel node Np, a storage capacitor 227 and a liquid crystal display element 228 connected in parallel between the pixel node Np and the common electrode node NC. And have. The orientation of the liquid crystal in the liquid crystal display element 228 changes according to the voltage difference between the pixel node Np and the common electrode node NC, and the display luminance of the liquid crystal display element 228 changes in response to this. As a result, the luminance of each pixel circuit can be controlled in accordance with the display voltage written to the pixel node Np via the data line DL and the switch element 226. Switch element 226 is formed of, for example, an n-type transistor.

  The gate driver 230 sequentially activates the gate lines GL based on a predetermined cycle. The gate of switch element 226 is connected to corresponding gate line GL. Therefore, the pixel node Np is connected to the corresponding data line DL during the activation (H level) period of the corresponding gate line GL. The switch element 226 is generally composed of a TFT formed on the same insulator substrate (glass substrate, resin substrate, etc.) as the liquid crystal display element 228. The display voltage transmitted to the pixel node Np is transmitted by the storage capacitor 227.

  Alternatively, the pixel circuit 225 in FIG. 17 can be replaced by a pixel circuit 225 # including a current-driven light emitting element shown in FIG.

  Referring to FIG. 18, pixel circuit 225 # includes a switch element 226, a holding capacitor 227 #, an EL (Electro-luminescence) element 228 # shown as a representative example of a current-driven light-emitting element, and a current-driven transistor 229. Including. Similar to the pixel circuit 225, the switch element 226 is provided between the corresponding data line DL and the pixel node Np, and the gate thereof is connected to the corresponding gate line GL. Retention capacitor 227 # is connected between pixel node Np and voltage Vdd. EL element 228 # and current drive transistor 229 are connected in series between voltage Vdd and voltage Vss. The current drive transistor 229 is configured by, for example, a p-type TFT. Switch element 226 and current drive transistor 229 are generally formed on the same insulator substrate as EL element 228 #.

  The switch element 226 connects the pixel node Np to the data line DL during the activation (H level) period of the corresponding gate line GL. Thereby, the display voltage on the data line DL is transmitted to the pixel node Np. The voltage at pixel node Np is held by holding capacitor 227 #.

  Current drive transistor 229 has a gate connected to pixel node Np, and supplies current Iel corresponding to the voltage of pixel node Np, that is, the display voltage (gray scale voltage) transmitted from the data line, to EL element 228 #. To do. The display brightness of EL element 228 # changes in accordance with supplied passing current Iel. Therefore, also in pixel circuit 225 #, the luminance of the EL element can be set in gradation by setting the display voltage applied to the pixel circuit in stages.

  As will be apparent from the following description, the sixth embodiment is directed to a peripheral circuit that generates a display voltage (grayscale voltage) to be supplied to each pixel circuit. In a display device having a pixel circuit that displays the corresponding luminance, the present invention can be applied without limiting the configuration of the pixel circuit.

Referring to FIG. 17 again, source driver 240 outputs a display voltage, which is set stepwise by n-bit display data SIG, to data line DL. Also in the sixth embodiment, the case where n = 4, that is, the case where the display data SIG is composed of data bits D0 to D3 will be representatively described. Also in the sixth embodiment, it is assumed that the data bit D0 is the least significant digit (LSB) and the data bit D3 is the most significant digit (MSB). Therefore, in display device 200 according to the sixth embodiment, 2 ⁴ = 16 gradations can be displayed in each pixel circuit based on 4-bit display data SIG.

  Source driver 240 includes a shift register 250, data latch circuits 252 and 254, and a display voltage generation circuit 270.

  The display data SIG is generated serially corresponding to the display luminance for each pixel circuit 225. That is, the data bits D0 to D3 at each timing indicate display luminance in one pixel circuit 225 in the display panel unit 220. The shift register 250 instructs the data latch circuit 252 to take in the data bits D0 to D3 at a timing synchronized with a predetermined cycle at which the setting of the display data SIG is switched. The data latch circuit 252 sequentially captures and holds display data SIG for one pixel row generated serially.

  The display data group latched in the data latch circuit 252 in response to the activation of the latch signal LT at the timing when the display data SIG for one pixel row is taken into the data latch circuit 252 is the data latch circuit 254. Is transmitted to.

  The display voltage generation circuit 270 includes a gradation voltage generation circuit 280 provided corresponding to each data line DL. Each of the gradation voltage generation circuits 280 outputs a gradation voltage obtained by digital-analog conversion of the corresponding data bits D0 to D3 held in the data latch circuit 254 to the output node No as a display voltage. Each output node No of the gradation voltage generation circuit 280 is connected to a corresponding data line DL. For example, output nodes No1 and No2 of grayscale voltage generation circuit 280 provided corresponding to data lines DL1 and DL2 shown in FIG. 17 are connected to data lines DL1 and DL2.

  The gradation voltage generation circuit 280 includes a pulse number control circuit 290 and a charge pump circuit 295. Pulse number control circuit 290 can be applied, for example, to the configuration of pulse number control circuits 20 and 20 # shown in FIGS. 1 and 6, respectively, and receives continuously supplied pulses CP to receive corresponding data bits. The number of pulses CP # corresponding to D0 to D3 is input to the charge pump circuit 295. That is, the number of pulses CP # input to charge pump circuit 295 is set according to a value obtained by digital-analog conversion of data bits D0 to D3.

  The charge pump circuit 295 changes the voltage of the output node No stepwise in response to each input of the pulse CP # input by the pulse number control circuit 290. As the charge pump circuit 295, the charge pump circuits 30, 131 to 133 and the charge pump circuits 30 #, 131 # to 133 # described in the first to fifth embodiments and their modifications can be used.

  With such a structure, a display voltage for gradation display can be generated with low power consumption using a charge pump circuit. In particular, if the charge pump circuits 295 shown in Embodiments 1 to 5 and the modifications thereof are used as the charge pump circuit 295, it is possible to generate gradation voltages with high accuracy. Alternatively, a charge pump circuit having a general configuration in which the arrangement of the bias circuit described in the first to fifth embodiments and the modifications thereof is omitted depending on the required gradation voltage setting accuracy and circuit area is applied. It is also possible to do.

  However, in particular, in a display device including a liquid crystal display element in each pixel circuit (hereinafter also referred to as “liquid crystal display device”), the parasitic capacitance of the data line DL corresponding to the output capacitance of the charge pump circuit has temperature dependence. Therefore, it is necessary to deal with this point.

  FIG. 19 is a cross-sectional view illustrating the parasitic capacitance of the data line which is the output capacitance of the charge pump circuit in the liquid crystal display device.

  Referring to FIG. 19, the liquid crystal display device is formed on a glass substrate 300 shown as a typical example of an insulator substrate. An insulating layer 340, a metal wiring layer 320, an insulating layer 350, and a liquid crystal layer 360 are sequentially stacked on the glass substrate 300, and a common electrode 330 is provided on the upper surface of the liquid crystal layer 360. In the metal wiring layer 320, the data line DL shown in FIG. The data line DL is typically formed of an aluminum wiring. The common electrode 330 corresponds to the common electrode node NC shown in FIG.

  Further, since the gate line GL shown in FIG. 17 is used as a gate electrode of a TFT (not shown) formed on the glass substrate 300, the gate line GL is formed on the metal wiring layer 310 provided in the middle of the insulating layer 340. The The gate line GL is typically formed of an aluminum-chrome wiring.

  As a result, the capacitance Ca corresponding to the parasitic capacitance between the data line DL and the gate line GL, and the capacitance Cb corresponding to the parasitic capacitance in each of the insulating layer 350 portion and the liquid crystal layer 360 portion between the data line DL and the common electrode 330. And Cc, the parasitic capacitance of the data line DL, that is, the output capacitance Co of the charge pump circuit is expressed as the sum of the capacitors Cb and Cc connected in series and the capacitance Ca.

  The capacitances Ca and Cb generated in the insulating layer portion have almost no temperature dependence, but the capacitance Cc of the liquid crystal layer portion changes depending on the temperature. As a result, the output capacitance (Co) of the charge pump circuit has temperature dependence.

  As a result, as can be understood from the above equations (1) and (4), the output voltage VNo of the charge pump circuit, that is, the gradation voltage supplied to the pixel circuit also varies depending on the temperature. End up.

  Therefore, in the display device according to the sixth embodiment, the pump capacity in the charge pump circuit, for example, the pump capacity 32 in the charge pump circuit shown in the first to fifth embodiments and their modifications will be described below. Thus, by forming according to the same structure as the periphery of the data line DL, fluctuations in the gradation voltage are suppressed.

FIG. 20 is a conceptual diagram illustrating formation of a pump capacity according to the sixth embodiment.
Referring to FIG. 20, in the configuration according to the sixth embodiment, pump capacitor 32 in the charge pump circuit includes capacitor Ca # formed at nodes N1 and N2, and capacitor Cb connected in series to nodes N1 and N2. This is realized by parallel connection with # and Cc #. Further, these capacitors Ca # to Cc # are formed in the same structure as the capacitors Ca to Cc shown in FIG.

FIG. 21 shows a first structure example of the pump capacity according to the sixth embodiment.
Referring to FIG. 21, in the region where pump capacitance 32 is formed, insulating layers 340 and 350 and liquid crystal layer 360 are formed as in the region where data line DL is arranged (display panel unit 220 in FIG. 17). . Further, a pump capacitor 32 is formed between electrodes 380 and 382 corresponding to nodes N1 and N2, respectively, formed in the same metal wiring layer 320 as the data line DL. Each of electrodes 380 and 382 is preferably made of the same material as data line DL.

  The pump capacitor 32 includes capacitors Ca # to Cc # having the same structure as the capacitors Ca to Cc constituting the output capacitor. In order to form the capacitor Ca #, the dummy electrode 315 is formed on the same metal wiring layer 310 as the gate line GL so as to face the electrode 380 with the insulating layer 340 interposed therebetween. Further, the dummy electrode 315 is electrically connected to the electrode 382 through a contact 383 formed in a through hole provided in the insulating layer 340.

  A dummy electrode 332 is formed in the same layer as the common electrode 330 so as to face the electrode 380 with the insulating layer 350 and the liquid crystal layer 360 interposed therebetween. Therefore, capacitances Cb # and Cc # corresponding to parasitic capacitances in the insulating layer 350 portion and the liquid crystal layer 360 portion exist between the dummy electrode 332 and the electrode 380, respectively, connected in series.

  Further, the electrode 382 is connected to the dummy electrode 332 by a contact electrode 384 and a conductive resin 386 that form a contact portion formed in a through hole provided in the insulating layer 350 and the liquid crystal layer 360. The contact electrode 384 is formed of aluminum or an ITO (Indium-Tin-Oxide) film. The dummy electrode 332 and the contact electrode 384 are connected to each other by pressure bonding with a conductive resin 386. The dummy electrode 332 is electrically separated from at least the common electrode 330 by the insulating film 370.

  By adopting such a structure, a structure similar to the parasitic capacitance of the data line DL (that is, the output capacitance of the charge pump circuit) is formed between the electrodes 380 and 382 by the series-parallel connection of the capacitors Ca # to Cc #. Thus, the pump capacity 32 is formed. The areas of the dummy electrodes 315 and 332 and the electrodes 380 and 382 are designed such that “Ca # + Cb # · Cc # / (Cb # + Cc #)”, which is the combined capacitance of the capacitance components Ca # to Cc #, is Cp. The

  By providing the pump capacity with such a structure, the temperature dependence of the capacity value Cp of the pump capacity and the capacity value Co of the output capacity becomes the same. For this reason, in the above equations (1), (4), etc., even if temperature dependence occurs in the capacitance values Cp, Co, they are canceled out by the ratio between them, so the levels of the voltages V2, VB, that is, the output voltage VNo are , Will not have a large temperature dependence. As a result, the temperature dependency can be eliminated and the gradation voltage can be generated with high accuracy using the charge pump circuit.

FIG. 22 is a diagram showing a second structure example of the pump capacity according to the sixth embodiment.
22 is compared with FIG. 21, in the second structural example, the dummy electrode 332 and the common electrode 330 are opposed to both the electrodes 380 and 382 with the insulating layer 350 and the liquid crystal layer 360 interposed therebetween. It is formed in the same layer. Furthermore, the electrical contact between the dummy electrode 332 and the electrode 382, that is, the arrangement of the contact electrode 384 and the conductive resin 386 in FIG. Furthermore, since the dummy electrode 332 needs to be in an electrically floating state, an insulating film 372 for electrically separating the dummy electrode 332 from other nodes and wirings is provided as necessary.

  Thereby, between each of the electrodes 380 and 382 and the dummy electrode 332, a capacitance 2Cb # that is a parasitic capacitance in the insulating layer 350 and a capacitance 2Cc # that is a parasitic capacitance in the liquid crystal layer 360 are connected in series. These capacitors are connected in series. Capacitances 2Cb # and 2Cc # are each twice the capacitances Cb # and Cc # shown in FIG.

  A capacitor Ca # is formed between the electrode 380 and the dummy electrode 315 with the same structure as that of FIG.

  As a result, the capacitance value between the electrodes 380 and 382, that is, between the nodes N1 and N2, is Ca # + Cb # · Cc # / (Cb # + Cc #), as in the structure example of FIG. Therefore, similarly to the structure example shown in FIG. 21, by making the pump capacity and the output capacity of the charge pump circuit the same structure, it is possible to eliminate the temperature dependence and generate the gradation voltage with high accuracy. . Furthermore, in the structure example of FIG. 22, crimping with a conductive resin having low dimensional accuracy is not required, so that manufacturing is facilitated and yield improvement can be expected.

[Embodiment 7]
In the seventh embodiment, a structure of a display device capable of promptly generating a gray scale voltage to the data line DL will be described.

  FIG. 23 is a block diagram showing a first configuration example of the gradation voltage generating circuit according to the seventh embodiment.

  Referring to FIG. 23, gradation voltage generating circuit 400 according to the seventh embodiment includes a pulse control unit 405, a pulse number control circuit 292, switch units 410 and 420, a rising charge pump circuit 295U, Type charge pump circuit 295D.

  The pulse control unit 405 includes an inverter 406 that inverts the pulse CP and outputs an inverted pulse / CP, and switches 407 and 408 that are complementarily turned on / off in response to the data bit D3 of the most significant digit.

  The pulse number control circuit 292 receives the pulse CP or the inverted pulse / CP transmitted to the node N4 by the pulse control unit 405, and supplies the number of pulses CP or the inverted pulse / CP corresponding to the data bits D0 to D3 to the node N5. Output.

  The switch unit 410 includes a switch 412 provided between the node N5 and the ascending charge pump circuit 295U, and a switch 414 provided between the node N5 and the descending charge pump circuit 295D. The switch unit 420 is provided between the output node of the ascending charge pump circuit 295U and the data line DL, and between the output node of the descending charge pump circuit 295D and the data line DL. A switch 424.

  In the gradation voltage generating operation, the switches 412 and 422 are turned on when the data bit D3 is “1” and turned off when the data bit D3 is “0”. Switches 414 and 424 are turned on or off complementarily with switches 412 and 422 in accordance with data bit D3.

  The rising type charge pump circuit 295U increases the voltage of the output node step by step by ΔV each time one pulse CP is input. That is, as the ascending type charge pump circuit 295U, the charge pump circuits 30, 131 to 133 described in the first to third embodiments and their modifications can be representatively used.

  The drop type charge pump circuit 295D drops the voltage of the output node step by step by ΔV every time one inversion pulse / CP is inputted. In other words, charge pump circuits 30 # and 131 # to 133 # described in the fourth embodiment can be representatively used as descending charge pump circuit 295D.

  Alternatively, depending on the required gradation voltage setting accuracy and circuit area, a charge pump circuit having a general configuration in which the arrangement of the bias circuit described in the first to fifth embodiments and the modifications thereof is omitted is charged. It is also possible to apply as the pump circuits 295U and 295D.

  As described in FIG. 17, the pixel circuit 225 (or 225 #) corresponding to the selected gate line GL is connected to the data line DL.

  Further, an intermediate voltage generation circuit 440 and a precharge switch 445 for connecting the intermediate voltage generation circuit 440 and the data line DL in response to a precharge signal PE are provided for the data line DL.

  The intermediate voltage generation circuit 440 generates an intermediate voltage Vm between the high voltage VDH and the low voltage VDL corresponding to the highest level and the lowest level of the gradation voltage, respectively. That is, the high voltage VDH is a gradation voltage corresponding to (D3, D2, D1, D0) = (1, 1, 1, 1), and the low voltage VDL is (D3, D2, D1, D0) = (0, Assuming that the gradation voltage corresponds to (0, 0, 0), the precharge voltage Vm corresponds to the intermediate level (D3, D2, D1, D0) = (1, 0, 0, 0). Set to

  The precharge switch 445 precharges the data line DL to the intermediate voltage Vm by turning on in response to the precharge signal PE before the grayscale voltage generating operation. On the other hand, the precharge switch 445 is turned off during the gradation voltage generating operation, that is, at the timing when the charge pump circuit 295U or 295D is connected to the data line DL by the switch unit 420.

FIG. 24 is a circuit diagram showing a configuration of pulse number control circuit 292 shown in FIG.
Referring to FIG. 24, pulse number control circuit 292 differs from pulse number control circuit 20 # shown in FIG. 6 in that it includes a switch control circuit 297 instead of switch control circuit 27 #. Switches 22-25 and 22 # -25 # are provided for controlling connection between nodes N4 and N5. Switches 22 # -25 # are turned on / off in response to control signals D0 # -D3 # from switch control circuit 297, respectively. The switches 22 to 24 are turned on / off in response to the control signals C0 to C2, and the switch 25 is turned on / off in response to the control signal C0.

  Switch control circuit 297 includes a multiplexer 293 that outputs control signals D0 # to D2 #, and an inverter 294 that outputs control signal D3 #. Multiplexer 293 receives data bits D0 to D2 and data bits / D0 to / D2 inverted by the inverter, and when data bit D3 = "1", data bits D0 to D2 are used as control signals D0 # to D2 #. On the other hand, when data bit D3 = "0", inverted data bits / D0 to / D2 are output as control signals D0 # to D2 #. Inverter 294 outputs inverted data bit / D3 as control signal D3 #.

  Referring to FIG. 23 again, when data bit D3 = "1", pulse CP is output from pulse control unit 405 to node N4. The pulse number control circuit 292 uses the configuration shown in FIG. 24 to transmit the number of pulses CP corresponding to the difference between the gradation voltage to be generated and the intermediate voltage Vm to the node N5. # Is generated.

  The pulse CP transmitted to the node N5 is input to the charge pump circuit 295U via the switch 412. The output node of charge pump circuit 295U is connected to data line DL by switch 422. On the other hand, inversion pulse / CP is not input to charge pump circuit 295D, and its output node is also disconnected from data line DL. As a result, the voltage of the data line DL, that is, the gradation voltage, rises from the intermediate voltage Vm to the voltage corresponding to the data bits D0 to D3 corresponding to the number of pulses CP input to the charge pump circuit 295U.

  In contrast, when data bit D3 = “0”, pulse control unit 405 outputs inverted pulse / CP to node N4. The pulse number control circuit 292 generates control signals D0 # to D3 # so as to transmit the number of inversion pulses / CP corresponding to the difference between the gradation voltage to be generated and the intermediate voltage Vm to the node N5.

  The inversion pulse / CP transmitted to the node N5 is input to the charge pump circuit 295D through the switch 414. The output node of charge pump circuit 295D is connected to data line DL by switch 424. On the other hand, no pulse CP is input to charge pump circuit 295U, and its output node is also disconnected from data line DL. As a result, the voltage (gradation voltage) of the data line DL drops from the intermediate voltage Vm to the voltage corresponding to the data bits D0 to D3, corresponding to the number of inversion pulses / CP input to the charge pump circuit 295D. .

  As described above, in the configuration according to the seventh embodiment, after the data line DL is precharged to the intermediate voltage Vm, the ascending charge pump circuit and the descending charge pump circuit are selectively operated to generate the gradation voltage. . Thereby, the generation of the gradation voltage can be speeded up as compared with the configuration using only one of the ascending charge pump circuit and the descending charge pump circuit.

[Modification of Embodiment 7]
FIG. 25 is a circuit diagram showing a configuration example of a grayscale voltage generation circuit according to a modification of the seventh embodiment.

  Referring to FIG. 25, in the configuration according to the modification of the seventh embodiment, gray scale voltage generating circuit 400 is substituted for gray scale voltage generating circuit 400 as compared with the configuration according to the seventh embodiment shown in FIG. The difference is that # is provided and that a precharge circuit 450 is provided instead of the intermediate voltage generation circuit 440 and the precharge switch 445.

  Precharge circuit 450 has a switch 452 arranged between high voltage VDH and data line DL, and a switch 454 provided between data line DL and low voltage VDL. Switches 452 and 454 are turned on and off in response to data bit D3 in response to signals PE3 and / PE3, respectively, during the turn-on period of precharge switch 445 shown in FIG.

  Grayscale voltage generation circuit 400 # differs from grayscale voltage generation circuit 400 shown in FIG. 23 in that it includes a pulse number control circuit 296 instead of pulse number control circuit 292. Further, on / off of the switches 407, 412, 422 and the switches 408, 414, 424 is controlled opposite to the gradation voltage generation circuit 400. That is, when the data bit D3 = “1”, the switches 407, 412, 422 are turned off and the switches 408, 414, 424 are turned on, whereas when the data bit D3 = “0”, the switches 407, 407, Each of 412 and 422 is turned on, and each of switches 408, 414 and 424 is turned off.

FIG. 26 is a circuit diagram showing a configuration of pulse number control circuit 296 shown in FIG.
Referring to FIG. 26, pulse number control circuit 296 does not require the arrangement of switches 25 and 25 # corresponding to data bit D3 as compared with pulse number control circuit 292 shown in FIG. The difference is that switch control circuit 297 # is included instead of control circuit 297.

  Switch control circuit 297 # includes a multiplexer 293 that generates control signals D0 # -D2 #. Contrary to the case of FIG. 24, multiplexer 293 outputs inverted data bits / D0 to / D2 as control signals D0 # to D2 # when data bit D3 = "1", while data bit D3 = "0". When "," data bits D0 to D2 are output as control signals D0 # to D2 #.

  Switches 22 # -24 # are turned on / off in response to control signals D0 # -D2 # from switch control circuit 297 #, and switches 22-24 are turned on / off in response to control signals C0-C2. Turn off.

  Referring again to FIG. 25, when data bit D3 = “1”, precharge circuit 450 precharges data line DL to high voltage VDH before the generation of the gradation voltage. From this state, the pulse control unit 405 outputs the inversion pulse / CP to the node N4. The pulse number control circuit 296 has a configuration shown in FIG. 26 and transmits the control signals D0 # ˜D0 # to transmit the number of inversion pulses / CP corresponding to the difference between the grayscale voltage to be generated and the high voltage VDH to the node N5. D2 # is generated.

  The inversion pulse / CP transmitted to the node N5 is input to the charge pump circuit 295D through the switch 414. The output node of charge pump circuit 295D is connected to data line DL by switch 424. On the other hand, no pulse CP is input to charge pump circuit 295U, and its output node is also disconnected from data line DL. As a result, the voltage (grayscale voltage) of the data line DL drops from the high voltage VDH to the voltage corresponding to the data bits D0 to D3 corresponding to the number of inversion pulses / CP input to the charge pump circuit 295D. .

  On the other hand, when the data bit D3 = “0”, the precharge circuit 450 precharges the data line DL to the low voltage VDL before the gradation voltage is generated. From this state, the pulse controller 405 outputs the pulse CP to the node N4. The pulse number control circuit 296 generates control signals D0 # to D2 # so as to transmit the number of pulses CP corresponding to the difference between the gradation voltage to be generated and the low voltage VDL to the node N5.

  The pulse CP transmitted to the node N5 is input to the charge pump circuit 295U via the switch 412. The output node of charge pump circuit 295U is connected to data line DL by switch 422. On the other hand, inversion pulse / CP is not input to charge pump circuit 295D, and its output node is also disconnected from data line DL. As a result, the voltage (gradation voltage) of the data line DL rises from the low voltage VDL to the voltage corresponding to the data bits D0 to D3 corresponding to the number of pulses CP input to the charge pump circuit 295U.

  Thus, in the configuration according to the modification of the seventh embodiment, the gradation voltage is generated by the combination of the ascending charge pump circuit and the descending charge pump circuit, and the data line is precharged according to the specific bit of the display data. Since the voltage can be switched, the generation of the gradation voltage can be further speeded up as compared with the configuration according to the seventh embodiment.

  The embodiment disclosed this time should be considered as illustrative in all points and not restrictive. The scope of the present invention is defined by the terms of the claims, rather than the description above, and is intended to include any modifications within the scope and meaning equivalent to the terms of the claims.

It is a circuit diagram which shows the structure of the digital / analog converting device according to Embodiment 1 of this invention. FIG. 2 is a circuit diagram showing a configuration of a switch control circuit shown in FIG. 1. FIG. 2 is an operation waveform diagram for explaining the operation of the pulse number control circuit shown in FIG. 1. It is a figure explaining operation | movement of the digital / analog converting device shown by FIG. FIG. 5 is a circuit diagram showing an internal state of the charge pump circuit before and after time t6 in FIG. 6 is a circuit diagram showing a configuration of a digital / analog conversion device according to a modification of the first embodiment. FIG. It is a circuit diagram which shows the structure of the digital / analog converting device according to Embodiment 2 of this invention. FIG. 11 is a circuit diagram showing a configuration of a digital / analog conversion device according to a modification of the second embodiment. It is a circuit diagram which shows the structure of the digital / analog converting device according to Embodiment 3 of this invention. FIG. 11 is a circuit diagram showing a configuration of a digital / analog conversion device according to a modification of the third embodiment. FIG. 10 is a circuit diagram showing a configuration example of a digital / analog conversion device according to a first configuration example of a fourth embodiment. FIG. 10 is a circuit diagram showing a configuration example of a digital / analog conversion device according to a second configuration example of the fourth embodiment. FIG. 11 is a circuit diagram showing a configuration example of a digital / analog conversion device according to a third configuration example of the fourth embodiment. FIG. 10 is a circuit diagram showing a configuration example of a digital / analog conversion device according to a fourth configuration example of the fourth embodiment. FIG. 10 is a circuit diagram showing a configuration example of a digital / analog conversion device according to a fifth configuration example of the fourth embodiment. FIG. 10 is a circuit diagram showing a configuration of a digital / analog conversion device according to a fifth embodiment. It is a block diagram which shows the whole structure of the display apparatus according to Embodiment 6. It is a circuit diagram which shows the structural example of the pixel circuit containing an EL element. It is sectional drawing explaining the parasitic capacitance of the data line which is an output capacitance of the charge pump circuit in a liquid crystal display device. It is a conceptual diagram explaining formation of the pump capacity | capacitance according to Embodiment 6. It is a figure which shows the 1st structural example of the pump capacity | capacitance according to Embodiment 6. FIG. It is a figure which shows the 2nd structural example of the pump capacity | capacitance according to Embodiment 6. FIG. FIG. 20 is a block diagram showing a first configuration example of a gradation voltage generation circuit according to the seventh embodiment. FIG. 24 is a circuit diagram showing a configuration of a pulse number control circuit shown in FIG. 23. FIG. 38 is a block diagram showing a configuration example of a gradation voltage generation circuit according to a modification of the seventh embodiment. FIG. 26 is a circuit diagram showing a configuration of a pulse number control circuit shown in FIG. 25.

Explanation of symbols

  5 output capacity, 10 to 16, 10 # to 15 # digital / analog converter, 20,292,292,296 pulse number control circuit, 21 nodes (pulse input), 27,27 #, 297,297 # switch control circuit , 30, 30 #, 130-133, 130 # -133 #, 295 Charge pump circuit, 32 pump capacity, 34 switch element, 36, 37 adjustment unit, 40, 40 #, 140-143, 140 # -143 # bias Circuit, 41, 43 #, 45 #, 46 n-type transistor, 42 current limiting element, 41 #, 43, 45, 46 # p-type transistor, 44 constant current source, 51-53 precharge switch, 200 display device, 220 Display panel section, 225, 225 # pixel circuit, 226 switch element, 227 holding capacitor, 228 Crystal display element, 228 # EL element, 229 current drive transistor, 230 gate driver, 240 source driver, 270 display voltage generation circuit, 280 gradation voltage generation circuit, 290, 292, 296 pulse number control circuit, 295D charge pump circuit ( 295U charge pump circuit (rising type), 300 glass substrate, 310, 320 metal wiring layer, 315, 332 dummy electrode, 330 common electrode, 340, 350 insulating layer, 360 liquid crystal layer, 370, 372 insulating film, 380,382 electrodes, 383,384 contacts, 386 conductive resin, 400,400 # gradation voltage generation circuit, 405 pulse control unit, 440 intermediate voltage generation circuit, 445 precharge switch, 450 precharge circuit, C0 to C3 D0C ~ D3C system Control signal, CP pulse, / CP inversion pulse, Co output capacitance value, Cp pump capacitance value, D0 to D3 data bit, / D0 to / D3 data bit (inversion), DL data line, GL gate line, LKa, LKb link Element, N1-N5 node, NH, NL, NR, NR # power supply node, NC common electrode node, No output node, SCa, SCb unit capacitor, SL scan line, VDH high voltage, VDL low voltage, VNo output voltage, VR , Vss Predetermined voltage.

Claims (8)

A display device that performs gradation display based on display data composed of weighted n bits (n: an integer of 2 or more),
A plurality of pixel circuits each configured to perform display according to a supplied voltage;
A selection line for selecting the plurality of pixel circuits;
A data line connected to the plurality of pixel circuits;
A gradation voltage generating circuit for supplying a gradation voltage, which is an analog voltage corresponding to the display data, to the data line;
The gradation voltage generation circuit includes:
The number of pulses given to the first node by the number corresponding to the display data, including the first transition edge changing from the initial level to the predetermined level and the second transition edge returning from the predetermined level to the initial level A control circuit;
A display device comprising: a charge pump circuit that changes the voltage of an output node connected to the data line in a stepwise manner each time one pulse is applied to the first node. The charge pump circuit includes a pump capacitor for transmitting a voltage variation of the first node due to the pulse by capacitive coupling,
The display device according to claim 1, wherein the pump capacitance is formed to have a structure similar to a parasitic capacitance of the data line. Each of the pixel circuits includes a liquid crystal element connected between a pixel node connected to the data line and a common electrode according to a state of the selection line,
Between the first metal wiring layer in which the data line is provided and the layer in which the common electrode is formed, a first insulating layer and a liquid crystal layer in which the liquid crystal element is formed are stacked and provided,
Between the second metal wiring layer provided with the selection line and the first metal wiring layer, there is a second insulating layer,
The pump capacity is
First and second electrodes provided on the first metal wiring layer;
A first dummy electrode formed in the same layer as the common electrode so as to face the first electrode across the liquid crystal layer and the first insulating layer;
A second dummy electrode formed in the second metal wiring layer so as to face the first electrode with the second insulating layer interposed therebetween;
A first contact portion for electrically connecting the first dummy electrode and the second electrode formed in a through hole provided in the liquid crystal layer and the first insulating layer;
A second contact portion for electrically connecting the second dummy electrode and the second electrode formed in a through hole provided in the second insulating layer;
The display device according to claim 2, wherein a capacity value of the pump capacity is given by a combined capacity value between the first and second electrodes. Each of the pixel circuits includes a liquid crystal element connected between a pixel node connected to the data line and a common electrode according to a state of the selection line,
Between the first metal wiring layer in which the data line is provided and the layer in which the common electrode is formed, a first insulating layer and a liquid crystal layer in which the liquid crystal element is formed are stacked and provided,
Between the second metal wiring layer provided with the selection line and the first metal wiring layer, there is a second insulating layer,
The pump capacity is
First and second electrodes provided on the first metal wiring layer;
A first dummy electrode formed in the same layer as the common electrode so as to face both the first and second electrodes across the liquid crystal layer and the first insulating layer;
A second dummy electrode formed in the second metal wiring layer so as to face the first electrode with the second insulating layer interposed therebetween;
An insulating film for electrically floating the second dummy electrode;
A contact portion for electrically connecting the second dummy electrode and the second electrode formed in a through hole provided in the second insulating layer;
The display device according to claim 2, wherein a capacity value of the pump capacity is given by a combined capacity value between the first and second electrodes. The pixel circuit includes:
A current-driven light-emitting element that emits luminance according to the supplied current;
The display device according to claim 1, further comprising: a current driver that supplies current corresponding to the gradation voltage supplied from the data line to the current-driven light emitting element. A display device that performs gradation display based on display data composed of weighted n bits (n: an integer of 2 or more),
A plurality of pixel circuits each configured to perform display according to a supplied voltage;
A data line connected to the plurality of pixel circuits;
A gradation voltage generating circuit for supplying a gradation voltage, which is an analog voltage corresponding to the display data, to the data line;
The gradation voltage generation circuit includes:
Continuously receiving a pulse including a first transition edge changing from an initial level to a predetermined level and a second transition edge returning from the predetermined level to the initial level, and according to a specific bit of the n bits A pulse control unit that outputs one of the pulse and an inverted pulse obtained by inverting the pulse;
A pulse number control circuit that receives the one of the pulse and the inversion pulse output from the pulse control unit and transmits the number of pulses or the inversion pulse corresponding to the display data to a first node;
A first charge pump circuit for stepwise increasing the voltage of the first output node connected to the data line in response to each of the pulses transmitted to the first node;
A second charge pump circuit for stepwise dropping the voltage of the second output node connected to the data line in response to each of the inversion pulses transmitted to the first node. apparatus.   The display device according to claim 6, further comprising a precharge circuit that precharges the data line to an intermediate voltage having a maximum level and a minimum level of the grayscale voltage before the grayscale voltage is generated.   The display according to claim 6, further comprising a precharge circuit that precharges the data line to one of a highest level and a lowest level of the grayscale voltage according to the specific bit before the grayscale voltage is generated. apparatus.

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