JP2006133444A - Voltage follower and display device using same - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a voltage follower which satisfactorily operates even if TFT etc., varying largely in threshold voltage are used, and a display device using the same. <P>SOLUTION: A voltage generator includes the voltage follower consisting of a comparator circuit 45, an inverter circuit 46 and a current supply circuit 47. An input voltage Vin from a voltage dividing circuit 44 is input through a first input terminal T1 to the voltage follower in the state of maintaining a control signal Cc at a high level and capacitors C1 to C4 are charged, and thereby the threshold voltage of transistors Q1 and Q3 is compensated. As a result, thereafter, when the output voltage Vc of the voltage follower from a second input terminal T2 is inputted with a control signal Cc held at low level, the transistor Q1 is turned to an OFF state and the transistor Q3 to an ON state at the time of Vc>Vin and the transistor Q1 is turned to the ON state and the transistor Q3 to an OFF state at the time of Vc<Vin and therefore, the output voltage Vc is eventually equaled to the input voltage Vin. <P>COPYRIGHT: (C)2006,JPO&NCIPI

Description

  The present invention relates to a voltage follower and a display device such as an organic EL (Electro Luminescence) display or a liquid crystal display using the voltage follower.

  A voltage driving element such as a liquid crystal display or a current driving element such as an organic EL display requires a plurality of control voltages in order to control the display state of the pixel. For example, in an active liquid crystal display device having a non-linear resistance element described in Patent Document 1 (Japanese Patent Application Laid-Open No. 4-269708), in addition to a gate selection potential VDD and a gate non-selection potential VLC, a common consisting of an intermediate potential thereof is used. Potentials V10, V1E, etc. are required, and this document discloses a voltage supply circuit shown in FIG. 20 as the common potential generating means. In this voltage supply circuit, a desired potential is generated by disposing the resistors 18 and 19 and the variable resistor 22 between the maximum voltage VDD and the minimum voltage VLC, and the operational amplifiers 25 and 26 that operate as the voltage follower. The common potentials V10, V1E, etc. are obtained.

  As the operational amplifiers 25, 26, etc., for example, an operational amplifier having a circuit configuration disclosed in Patent Document 2 (Japanese Patent Laid-Open No. 8-32386), that is, an operational amplifier having a circuit configuration shown in FIG. This operational amplifier comprises a constant voltage supply circuit 4a, a differential amplifier 5, an output buffer 6, and a phase compensation capacitor 7a. In the differential amplifier 5, a pair of p-channel FETs (Field Effect Transistors) 9a. , 9b constitute a current mirror circuit, and the outputs of the p-channel FETs 9a, 9b are supplied to the n-channel FETs 8a, 8b, respectively. The gate terminals of the n-channel FETs 8a and 8b are an inverting input terminal 2 and a non-inverting input terminal 1, respectively.

  In the operational amplifier of FIG. 21 configured as described above, when the potential V1 of the non-inverting input terminal 1 becomes lower than the potential V2 of the inverting input terminal 2, the current flowing through the n-channel FET 8b is greater than the current flowing through the n-channel FET 8a. Less. On the other hand, since the current flowing through the p-channel FET 9b constituting the current mirror circuit is equal to the current flowing through the p-channel FET 9a (ie, the current flowing through the n-channel FET 8a), the connection point between the p-channel FET 9b and the n-channel FET 8b. The potential Vx increases. Since this potential Vx is applied to the gate terminal of the p-channel FET 6a in the output buffer 6, the p-channel FET 6a is turned off (off state), and the potential of the output terminal 3 of the operational amplifier drops. Conversely, when the potential V1 of the non-inverting input terminal 1 becomes higher than the potential V2 of the inverting input terminal 2, the current flowing through the n-channel FET 8b becomes larger than the current flowing through the n-channel FET 8a. On the other hand, since the current flowing through the p-channel FET 9b is equal to the current flowing through the p-channel FET 9a (ie, the current flowing through the n-channel FET 8a), the potential Vx at the connection point decreases and the p-channel FET 6a is turned on (ON). State), and the potential of the output terminal 3 rises. Therefore, when the inverting input terminal 2 and the output terminal 3 of the operational amplifier of FIG. 21 are connected, the potential of the output terminal 3 can be set to the potential V1 of the non-inverting input terminal 1. That is, the operational amplifier of FIG. 21 can be operated as a voltage follower by connecting the inverting input terminal 2 and the output terminal 3.

  As a voltage follower that does not use the current mirror circuit configuration, the voltage follower having the circuit configuration shown in Patent Document 3 (Japanese Patent Laid-Open No. 9-146500), that is, the voltage follower having the circuit configuration shown in FIG. it can. FIG. 22 shows the configuration of the sampling hold circuit 251A in one column of the data driver of the liquid crystal display device, and this sampling hold circuit 251A is held in the capacitor CP by sampling the positive potential of the alternating video signal VSA. A voltage follower on the positive polarity side that outputs substantially the same voltage as the voltage to be output, and a voltage follower on the negative polarity side that outputs substantially the same voltage as the voltage held in the capacitor CN by sampling the negative potential of the AC video signal VSA. Is included. The positive voltage follower is composed of a source follower circuit 39P, a primary correction circuit 41P, and a secondary correction circuit 42P. The negative voltage follower is a source follower circuit 39N, a primary correction circuit 41N, and a secondary correction circuit. These voltage followers are used to correct for the difference between the input voltage (the voltage of the video signal VSA held in the hold capacitor) and the output voltage (the output voltage of the source follower). A capacitor is used. For example, in the positive voltage follower, the capacitor C1P is used to fill the difference between the input voltage held in the capacitor CP and the output voltage VDL of the transistor T3P.

With the circuit configuration shown in FIG. 20 using such an operational amplifier, the control voltage required by the liquid crystal display or the like can be obtained by impedance-converting the voltage generated by the resistance division.
JP-A-4-269708 JP-A-8-32386 JP-A-9-146500

  When a voltage follower is constituted by an operational amplifier including a differential amplifier (current mirror circuit) as shown in FIG. 21, it is produced adjacently even if the characteristics of FETs constituting the differential amplifier or the like vary. If the FET characteristics (threshold voltage and the like) are equal to each other, the voltage follower operates well, and the input voltage and the output voltage are equal (the potential of the output terminal 3 is equal to the potential V1 of the non-inverting input terminal 1).

  Incidentally, in a display device such as a liquid crystal display or an organic EL display, a low-temperature polysilicon TFT (Thin Film Transistor) or an amorphous silicon TFT is used in a pixel circuit for forming a pixel. Therefore, if a voltage generator or the like can be realized using these TFTs, the number of parts can be reduced and the cost can be reduced as compared with the case of using an external operational amplifier.

  However, these TFTs have a large variation in threshold voltage, and the threshold voltages are different from each other between adjacent TFTs. Therefore, a current mirror circuit with high accuracy cannot be manufactured using TFTs, and as a result, a voltage follower that operates well or a voltage generator with high accuracy cannot be realized using the voltage follower.

  Further, the voltage follower of FIG. 22 corrects the characteristic variation of the transistor T3P using the capacitor C1P without using the current mirror circuit, but requires the constant current circuit 40P. However, these TFTs have large variations in threshold voltage, and it is difficult to realize a stable constant current circuit.

  Therefore, an object of the present invention is to provide a voltage follower that operates well even when a field effect transistor (FET) such as a TFT whose threshold voltage varies greatly. Another object of the present invention is to provide a display device using such a voltage follower.

1st invention has the 1st and 2nd input terminal and the output terminal connected to the said 2nd input terminal, The voltage substantially equal to the voltage given to the said 1st input terminal is the said output terminal A voltage follower output from
A comparison circuit that compares a first input voltage applied to the first input terminal and a second input voltage applied to the second input terminal;
A current supply circuit for supplying current from the output terminal,
The comparison circuit is
A field effect transistor for comparing the first input voltage and the second input voltage;
A threshold compensation circuit for compensating a threshold voltage of the field effect transistor,
The current supply circuit reduces the voltage of the output terminal when the second input voltage is higher than the first input voltage based on the output voltage of the comparison circuit, and the second input voltage is the first input voltage. When the input voltage is lower than 1, the output terminal voltage is raised.

According to a second invention, in the first invention,
The comparison circuit includes a first transistor as the field effect transistor,
The threshold compensation circuit includes:
A first capacitor connected between a gate terminal and a source terminal of the first transistor;
A second capacitor having one end connected to the gate terminal of the first transistor;
A first switching element connected between a gate terminal and a drain terminal of the first transistor;
A second switching element connected between the other end of the second capacitor and the first input terminal and turned on / off in conjunction with the first switching element;
And a third switching element connected between the other end of the second capacitor and the second input terminal and turned on / off reciprocally with the first switching element.

According to a third invention, in the second invention,
The comparison circuit is
A second transistor as the field effect transistor having a channel shape different from that of the first transistor;
A fourth switching element connected between the drain terminal of the first transistor and the drain terminal of the second transistor, and turned off when the first switching element is on; The threshold compensation circuit includes:
A third capacitor connected between a gate terminal and a source terminal of the second transistor;
A fourth capacitor connected between the gate terminal of the second transistor and the other end of the second capacitor; and connected between a gate terminal and a drain terminal of the second transistor; And a fifth switching element that is turned on / off in conjunction with one switching element.

According to a fourth invention, in any one of the first to third inventions,
The current supply circuit includes a third transistor which is a field effect transistor for supplying a current from the output terminal.

A fifth invention is the fourth invention,
The current supply circuit further includes a field effect transistor having a channel type different from that of the third transistor, and further includes a fourth transistor that forms an inverter circuit together with the third transistor.

According to a sixth invention, in the fifth invention,
The first to fourth transistors and the first to fifth switching elements are thin film transistors.

According to a seventh invention, in the first invention,
The threshold compensation circuit includes:
A gate-source capacitor connected between a gate terminal and a source terminal of the field effect transistor; and an input capacitor having one end connected to the gate terminal of the field effect transistor;
During the first predetermined period, the gate-source capacitor is charged to a voltage equal to the threshold voltage of the field effect transistor, and the input capacitor is charged with a difference between the first input voltage and the threshold voltage of the field effect transistor. To a voltage equal to
Applying the second input voltage to the other end of the input capacitor in a second predetermined period after the first predetermined period;
The field effect transistor outputs a voltage indicating a comparison result between the first input voltage and the second input voltage during the second predetermined period.

The eighth invention is a display device,
A voltage follower according to any one of the first to seventh inventions is provided.

A ninth invention is a display device including a voltage generator,
The voltage generator is
A voltage follower according to any one of the first to seventh inventions;
And a voltage dividing circuit for generating the first input voltage.

A tenth invention is a display device according to the ninth invention,
The voltage dividing circuit includes first and second resistance elements that determine the first input voltage.

  According to the first aspect, the comparison circuit compares the voltage of the output terminal of the current supply circuit given as the second input voltage with the first input voltage, and the voltage indicating the comparison result is the threshold voltage. Output from the compensated field effect transistor. Based on the voltage indicating the comparison result, the current supply circuit reduces the voltage at the output terminal when the second input voltage, which is the voltage at the output terminal, is higher than the first input voltage. When the voltage is lower than that, the voltage at the output terminal is increased. As a result, a voltage equal to the first input voltage is impedance-converted and output from the current supply circuit. Here, the control for making the output voltage from the current supply circuit, that is, the voltage at the output terminal equal to the first input voltage is performed based on the voltage output from the field effect transistor whose threshold voltage is compensated. Even if a transistor such as a TFT whose threshold voltage varies is used as the field effect transistor, a voltage equal to the first input voltage can be impedance-converted and output from the current supply circuit.

  According to the second aspect of the invention, the first input voltage is applied to the other end of the second capacitor by turning on the first and second switching elements and turning off the third switching element. The first capacitor is charged to a voltage equal to the threshold voltage of the first transistor (field effect transistor) and the second capacitor is charged to a voltage equal to the difference between the first input voltage and the threshold voltage. As a result, the threshold voltage of the first transistor is compensated. Thereafter, by turning off the first and second switching elements and turning on the third switching element, the second input voltage is applied to the other end of the second capacitor, and the first input voltage and A voltage corresponding to the magnitude relationship with the second input voltage, that is, a voltage indicating a comparison result is output from the first transistor without being affected by variations in the threshold voltage. The output voltage from the current supply circuit, that is, the voltage at the output terminal is controlled based on the voltage indicating the comparison result. Therefore, even if a transistor such as a TFT whose threshold voltage varies is used as the first transistor, a voltage equal to the first input voltage can be impedance-converted and output from the current supply circuit.

  According to the third aspect of the invention, the first, second and fifth switching elements are turned on and the third and fourth switching elements are turned off, so that the first input voltage is the second and second switching elements. And the third capacitor is charged to a voltage equal to the threshold voltage of the first transistor, and the third capacitor is charged to a voltage equal to the threshold voltage of the second transistor. The second capacitor has a voltage equal to the difference between the first input voltage and the threshold voltage of the first transistor, and the fourth capacitor has a voltage equal to the difference between the first input voltage and the threshold voltage of the second transistor. By charging each, the threshold voltages of the first and second transistors are compensated. Thereafter, the first, second, and fifth switching elements are turned off and the third and fourth switching elements are turned on, so that the second input voltage is applied to the other ends of the second and fourth capacitors. A voltage corresponding to the magnitude relationship between the first input voltage and the second input voltage, that is, a voltage indicating a comparison result is output from the first and second transistors without being affected by variations in their threshold voltages. Is done. The output voltage from the current supply circuit, that is, the voltage at the output terminal (output voltage) is controlled based on the voltage indicating the comparison result. Therefore, even if a transistor such as a TFT whose threshold voltage varies is used for the first and second transistors, a voltage equal to the first input voltage can be impedance-converted and output from the current supply circuit. Further, since the voltage indicating the comparison result is output from the first and second transistors having different channel shapes, the voltage can be reacted more quickly due to the output voltage fluctuation of the current supply circuit, and stable regardless of the load fluctuation of the current supply circuit. Output voltage can be obtained.

  According to the fourth aspect of the present invention, when the voltage (output voltage) of the output terminal of the current supply circuit is equal to or higher than the first input voltage, or when the voltage is equal to or lower than the first input voltage, Since the third transistor is turned on, current flowing in other periods can be saved.

  According to the fifth aspect of the invention, since the current supply circuit is composed of an inverter circuit, the output voltage is either higher than the first input voltage or lower than the first input voltage. Based on the voltage indicating the comparison result, the output voltage is controlled to be equal to the first input voltage. Therefore, the output voltage as the voltage follower can be stabilized regardless of the voltage pull-in direction of the load to be connected to the output terminal.

  According to the sixth invention, since the voltage follower is realized by the thin film transistor, the number of components in the display device can be reduced by forming the voltage follower on an insulating substrate such as a glass substrate constituting the display panel. Cost can be reduced.

  According to the seventh aspect, the gate-source capacitor is charged to a voltage equal to the threshold voltage of the field effect transistor and the input capacitor is connected to the first input voltage and the field effect transistor during the first predetermined period. It is charged to a voltage equal to the difference from the threshold voltage, and the second input voltage is applied to the other end of the input capacitor during the second predetermined period, and the magnitude relationship between the first input voltage and the second input voltage In other words, the voltage indicating the comparison result, that is, the voltage indicating the comparison result, is output from the field effect transistor without being affected by variations in the threshold voltage. And the output voltage from a current supply circuit is controlled based on the voltage which shows such a comparison result. Therefore, even if a transistor such as a TFT whose threshold voltage varies is used as the field effect transistor, a voltage equal to the first input voltage can be impedance-converted and output from the current supply circuit.

  According to the eighth aspect of the invention, a transistor having a threshold voltage variation such as a TFT can be used as the field effect transistor constituting the voltage follower. Therefore, such a voltage follower is insulated from the glass substrate or the like constituting the display panel. By forming it on a conductive substrate, it can be realized without using an external operational amplifier or the like. As a result, the number of parts in the display device can be reduced and the cost can be reduced.

  According to the ninth aspect, the first input voltage generated in the voltage dividing circuit can be reduced in impedance through the voltage follower. Since a transistor with a varying threshold voltage such as a TFT can be used as a field effect transistor that constitutes a voltage generator including this voltage follower, such a voltage generator is used as an insulating material such as a glass substrate that constitutes a display panel. By forming it on the substrate, it can be realized without using an external operational amplifier or the like. As a result, the number of parts in the display device can be reduced and the cost can be reduced. Even if a transistor having a large threshold variation such as a low-temperature polysilicon TFT or an amorphous silicon TFT is used in the voltage generator, the threshold voltage compensation circuit can suppress the variation in the output voltage of the voltage generator. It is possible to save labor for adjusting the cost and reduce the cost accordingly. Further, when the threshold compensation circuit is composed of the first and second transistors having different channel shapes, it becomes easy to react to the output voltage fluctuation from the current supply circuit, and even if the load fluctuates, The output voltage can be stabilized. For this reason, since the pixel circuit of the display panel is controlled by the stabilized voltage, the display quality of the display device can be improved. Furthermore, when the current supply circuit is composed of third and fourth transistors having different channel shapes, the output voltage can be stabilized regardless of the voltage pull-in direction of the load, and therefore the voltage pull-in direction of the load varies. Also in the display device, display quality can be improved by controlling the pixel circuit with a stabilized voltage.

  According to the tenth aspect, the first resistance element is formed in the display panel, and the second resistance element is formed outside the display panel, so that the value of the second resistance element can be obtained even after the panel substrate is manufactured. Therefore, the output voltage from the voltage generator can be adjusted in accordance with the change in the display element characteristics. Thereby, since it can respond flexibly to the improvement of element characteristics, the delivery time of the display device can be shortened and the cost can be reduced.

Hereinafter, embodiments of the present invention will be described with reference to the accompanying drawings.
An active element such as a switching element used in the voltage follower according to the present invention can be composed of a low-temperature polysilicon TFT, a CG silicon (Continuous Grain Silicon) TFT, or the like, but in each embodiment described below, It is assumed that CG silicon TFT is used.

  Here, the structure of the CG silicon TFT is, for example, Kazutaka Inukai and 7 others (Semiconductor Energy Laboratory), “4.0-inch TFT-OLED display and new digital driving method (4.0-in. TFT-OLED Displays and a Novel Digital Driving Method) ", SID'00 Digest, 2000, p. The manufacturing process of CG silicon TFT is disclosed in, for example, Toru Takayama and 6 others (Semiconductor Energy Laboratory), “Continuous Grain Silicon Crystal Technology and Application to Active Matrix Silicon (Continuous Grain Silicon) Technology and Its Applications for Active Matrix Display), AM-LCD 2000, 2000, p. 25-28. That is, since the configuration of the CG silicon TFT and the manufacturing process thereof are both known, the description thereof is omitted here.

  The configuration of the organic EL element which is an electro-optical element used in each embodiment described below is, for example, R.I. H. R. H. Friend, “Polymer Light-Emitting Diodes for Use in Flat Panel Displays”, AM-LCD'01, 2001, p. 211-214, which is publicly known, so the description thereof is omitted here.

<1. First Embodiment>
<1.1 Overall configuration and operation>
FIG. 1 is a block diagram showing a configuration of a display device according to the first embodiment of the present invention. This display device includes a display control circuit 100, a display panel 300, and a power supply circuit 500. The display panel 300 includes a display unit 31 composed of a plurality of pixel circuits arranged in a matrix, a source driver circuit 32 for driving the display unit 31, a first gate driver circuit 33, and a second gate driver. A circuit 38 and a voltage generator 41 for generating a control voltage used in the driver circuits 32 and 38 are included. The display control circuit 100 receives an image signal DV representing an image to be displayed and horizontal and vertical synchronization signals HSY, VSY from the outside, and serial data Dx to be supplied to the source driver circuit 32 as data representing an image to be displayed. In addition to outputting, a start pulse signal SP, a clock signal clk, and a latch pulse signal LP as control signals to be supplied to the source driver circuit 32 are output. Further, the display control circuit 100 outputs an address signal Add and an output control signal OE to be supplied to the first gate driver circuit 33, and outputs a clock signal yck and a control signal YI to be supplied to the second gate driver circuit 38. Output. Further, the display control circuit 100 outputs control signals Pc, Cc, Rc to be supplied to the voltage generator 41. On the other hand, the power supply circuit 500 supplies the display control circuit 100 and the display panel 300 with a power supply voltage (such as a voltage Vcc described later) necessary for their operation.

  FIG. 2 is a block diagram showing a configuration of the display panel 300 in the present embodiment. Hereinafter, each component of the display panel 300, that is, a display unit 31 having a plurality of pixel circuits A (i, j), a source driver circuit 32, a first gate driver circuit 33, and a second gate driver. The circuit 38 and the voltage generator 41 will be described.

  The display unit 31 includes a plurality (n) of source lines SL1 to SLn connected to the source driver circuit 32 and a plurality (m) of gate lines GL1 to GLm connected to the gate driver circuit 33. The control wirings PLi and the potential wirings ULi are arranged so as to intersect with each other in a grid pattern (i = 1, 2,..., M) in parallel with the gate wirings GLi, and the power supply wirings in parallel with the source wirings SLj. Are arranged (j = 1, 2,..., N). Each pixel circuit A (i, j) is arranged in a matrix corresponding to the intersections of the plurality of source lines SL1 to SLn and the plurality of gate lines GL1 to GLm. The source driver circuit 32 includes an n-bit (n-stage) shift register 34, an n-bit register 35, an n-bit latch 36, and n analog switch circuits 37. The display control circuit 100 receives the start pulse signal SP and the clock signal clk, the serial data Dx from the register 35, and the latch pulse signal LP from the latch 36 circuit.

  In the source driver circuit 32, the start pulse signal SP is input to the first register of the n-stage shift register 34, and the start pulse signal SP is transferred in the shift register 34 by the clock signal clk. It is output to the register 35 as a timing pulse SSP. The n-bit register 35 holds n-bit data input as the serial data Dx at positions corresponding to the source lines SL1 to SLn, respectively, by the timing pulse SSP output from the shift register 34. The latch 36 takes in the n-bit data held in the register 35 at the timing of the latch pulse signal LP and outputs it to the n analog switch circuits 37. n source lines SL1 to SLn are connected to the n analog switch circuits 37, and each analog switch circuit 37 has a source line SLj (j = 1, 2,..., n) connected thereto. On the other hand, a potential corresponding to the data input from the latch 36 is output as the data signal Dj out of the two types of predetermined potentials VH and VL (the potential VH> the potential VL as shown in FIG. 4A described later). Hereinafter, the potential VH is referred to as “high potential VH”, and the potential VL is referred to as “low potential VL”).

  The first gate driver circuit 33 includes a decoder circuit and a buffer circuit (not shown). An address signal Add is input to the decoder circuit, and an output control signal OE is input to the buffer circuit from the display control circuit 100. In the gate driver circuit 33, the decoder circuit decodes the address signal Add to output a signal corresponding to any of the gate wirings GL1 to GLm. Then, the buffer circuit outputs the signal output from the decoder circuit to the corresponding gate wiring GLi (i = 1, 2,..., M) at the timing controlled by the output control signal OE.

  The second gate driver circuit 38 includes an m-bit (m-stage) shift register circuit 39 and m analog switch circuits 40. In the shift register circuit 39, the clock signal yck and the control signal YI are display-controlled. Input from the circuit 100. The control signal YI includes first and second control signals YP and YU, is input to the head of the shift register circuit 39, and is transferred in the shift register circuit 39 by the clock signal yck. Based on the control signal YI transferred in this way, the potentials of the control signal line PLi and the potential wiring ULi are controlled.

  That is, when the configuration of the second gate driver circuit 38 is described with reference to FIG. 3 showing the configuration of the pixel circuit A (i, j), the shift register 39 of the second gate driver circuit 38 receives the control signal YI. An n-stage shift register including two cascaded D-type flip-flops 42 for transferring the first control signal YP and the second control signal YU constituting the second synchronous signal YU in synchronization with the clock signal yck, Each stage corresponds to one row of pixel circuits arranged in a matrix and one of m analog switch circuits 40. Of the control signals YI transferred by the shift register 39, the first control signal YP is sent to the corresponding stage via the internal buffer 43 provided in each stage of the shift register 39 according to the transfer. The second control signal YU is output to the control signal line PLi of the corresponding row, and is input to the analog switch circuit 40 corresponding to each stage in accordance with the transfer. Each analog switch circuit 40 includes a P-channel thin film transistor Q25 and an N-channel thin film transistor Q26, and selects one of two types of potentials Vcc and Vc according to the second control signal YU input thereto. The selected potential is output to the potential wiring ULi in the row corresponding to the analog switch circuit 40.

<1.2 Configuration and Operation of Pixel Circuit>
Next, the configuration and operation of the pixel circuit in this embodiment will be described with reference to FIG. In this embodiment, a TFT (thin film transistor) is used as an active element. In the following, an n-channel thin film transistor is abbreviated as “Nch transistor”, and a p-channel thin film transistor is abbreviated as “Pch transistor”. And

  As described above, pixel circuits are provided corresponding to the intersections of the source lines SL1 to SLn and the gate lines GL1 to GLm. In the following description, the i-th gate line GLi and the j-th source line SLj are provided. The pixel circuit corresponding to the intersection with is denoted by reference numeral “A (i, j)”. As shown in FIG. 3, each pixel circuit A (i, j) includes a driving Pch transistor Q21, switching Nch transistors Q22 and Q24, switching Pch transistor Q23, capacitors C11 and C12, and organic EL element EL1 is included. The common wiring VLcom is arranged on the entire surface of the display unit 31 so as to cover the organic EL element EL1 of each pixel circuit A (i, j), and the control wiring PLi and the potential wiring ULi are arranged in the direction in which the gate wiring GLi extends. The power supply wiring VLp is arranged so as to pass through the pixel circuit A (i, j) in the extending direction of the source wiring SLj.

  In each pixel circuit A (i, j), the driving transistor Q21 has its source terminal connected to the power supply wiring VLp and its drain terminal connected to the anode of the organic EL element EL1 via the switching transistor Q23. The cathode of the organic EL element EL1 is connected to the common wiring VLcom. That is, the driving transistor Q21, the switching transistor Q23, and the organic EL element EL1 are connected in series between the power supply wiring VLp and the common wiring VLcom. A switching transistor Q22 is connected between the gate terminal and the drain terminal of the driving transistor Q21, and a capacitor C11 is connected between the gate terminal of the driving transistor Q21 and the potential wiring ULi. A switching transistor Q24 is connected between the gate terminal of the switching transistor Q23 and the source line SLj, and a capacitor C12 is connected between the gate terminal of the switching transistor Q23 and the power supply line VLp. The control wiring PLi is connected to the gate terminal of the switching transistor Q22, and the gate wiring GLi is connected to the gate terminal of the switching transistor Q24.

Hereinafter, the operation of the pixel circuit A (i, j) in the present embodiment will be described with reference to the timing chart shown in FIG. 4B, 4C, and 4D respectively show the gate signal Gi on the gate wiring GLi, the control signal Pi on the control wiring PLi, and the potential signal Ui on the potential wiring ULi, and these signals Gi, Pi and Ui are given to the pixel circuit A (i, j). Figure 4 (f) (g) ( h) , the gate wiring GL _{i +} gate signals G _{i + 1} on the _1, control signal P _{i + 1} on the control line PL _{i + 1,} the potential wiring UL _{i + 1} above Potential signals U _{i + 1} are respectively shown, and these signals G _{i + 1} , P _{i + 1} , U _{i + 1} are given to the pixel circuit A (i + 1, j). FIG. 4A shows a data signal Dj on the source line SLj, and this data signal Dj represents instruction data Da1 to Da3 and DB. Here, the instruction data DB is blanking data, and the blanking data DB is given to the pixel circuit A (i, j) between times 8t1 and 12t1. During this period, the potential of the potential signal Ui is set to the power supply potential Vcc, the control signal Pi is set to the High (GH) level, and the switching transistor Q22 is turned on (on state).

  As a result, the gate terminal and the drain terminal of the driving transistor Q21 are short-circuited. Then, the gate signal Gi is set to the High (GH) level, the switching transistor Q24 is turned on, the potential VL of the data signal Dj is applied from the source line SLj to the gate terminal of the switching transistor Q23, and the switching transistor Q23 is turned on. And As a result, the gate terminal potential of the driving transistor Q21 is lowered, and the driving transistor Q21 is turned on.

  Thereafter, the potential of the data signal Dj is changed to the high potential VH, the switching transistor Q23 is turned off (off state), the gate signal Gi is set to the Low (GL) level, and the switching transistor Q24 is turned off. . When the switching transistor Q23 is turned off, as shown in FIG. 4E, the drain terminal potential Vd of the driving transistor Q21 increases, and the gate terminal potential Vg connected to the drain terminal also increases. As a result, the driving transistor Q21 changes from the ON state to the OFF state. The gate-source voltage of the driving transistor Q21 in this OFF state is equal to the threshold voltage of the driving transistor Q21. FIG. 4E schematically shows how the drain terminal potential Vd of the driving transistor Q21 changes.

  Thereafter, after a predetermined time has elapsed (at time 27t1 in FIG. 4), the control signal Pi is set to the Low (GL) level, the switching transistor Q22 is turned off, and a voltage equal to the threshold voltage of the driving transistor Q21 is set. Hold in capacitor C11.

  FIG. 5 shows a result of simulating changes in the gate potential Vg, drain potential Vd, and current Ids flowing between the source and drain of the driving transistor Q21 under the following conditions during the above period.

  In FIG. 5, the waveforms of the potentials Vg (1), Vg (2), and Vg (3) indicate changes in the gate potential Vg of the driving transistor Q21 under the above conditions (1), (2), and (3), respectively. The waveform of the potential Vd (1), Vd (2), and Vd (3) indicates the waveform of the driving transistor Q21 under the conditions (1), (2), and (3), respectively. The simulation result about the change of the drain potential Vd is shown. As can be seen from the waveforms of the potentials Vg (1) to Vg (3) shown in FIG. 5, the gate potential Vg is set corresponding to the threshold voltage of the driving transistor Q21.

  Thereafter, as shown in FIG. 4, at time 28t1, the potential of the potential signal Ui is changed from Vcc to Vc (Vcc> Vc). At this time, a voltage equal to the threshold voltage of the driving transistor Q21 is held in the capacitor C11. Therefore, by changing the potential of the potential signal Ui from Vcc to Vc, the voltage between the source and drain of the driving transistor Q21 is changed. The flowing current Ids can be set to be constant regardless of variations in the threshold voltage of the driving transistor Q21.

  Thereafter, as shown in FIG. 4, the set current Ids has a gate potential at which the gate signal Gi is set to the High (GH) level and the switching transistor Q23 is turned on during the period of time 32t1 to 36t1. Is supplied to the organic EL element EL1. Therefore, by setting the gate potential for turning on the switching transistor Q23 a plurality of times in one frame period, time-division gradation display is possible. Note that this time-division gradation display method is a known technique and is disclosed in, for example, Japanese Patent Application Laid-Open No. 2004-4501.

<1.3 Configuration of voltage generator>
As shown in FIG. 2, the display device according to the present embodiment generates a data signal Dj and a potential signal Ui that are signals for controlling the display state of the pixel in the pixel circuit A (i, j) as described above. A voltage generator 41 is provided as means for generating the necessary voltages VH, VL, Vc, etc. (hereinafter, these voltages are collectively referred to as “control voltage”). The voltage generator 41 generates control voltages VH, VL, Vc and the like from the power supply voltage Vcc and the like supplied from the power supply circuit 500. Among these control voltages VH, VL, Vc, etc., the high voltage VL and the low voltage VL are given to the analog switch circuit 37 in the source driver circuit 32, and the analog switch circuit 37 uses the voltages VH and VL to Data signal Dj (j = 1 to n) is generated. The control voltage Vc is supplied to the analog switch circuit 40 in the second gate driver circuit 38 together with the power supply voltage Vcc, and the analog switch circuit 40 uses the voltages Vc and Vcc to output the potential signal Ui (i = 1 to 1). m).

  FIG. 6 is a circuit diagram showing a configuration of a portion that generates the control voltage Vc in the voltage generator 41 as described above. Hereinafter, the configuration of the voltage generator 41 as a means for generating the control voltage Vc will be described with reference to FIG. In the following description, the configuration and operation of the voltage generator 41 are illustrated or described only for the portion that generates the control voltage Vc, and the configuration and operation of the portion that generates the other control voltage are clear from the following description. Therefore, illustration and description are omitted. In the voltage generator 41, a TFT (thin film transistor) is used as an active element. In the following description, an n-channel thin film transistor is abbreviated as “Nch transistor”, and a p-channel thin film transistor is referred to as “Pch transistor”. It shall be abbreviated.

  The voltage generator 41 includes a voltage dividing circuit 44, a comparison circuit 45, an inverter circuit 46, and a current supply circuit 47. The comparison circuit 45, the inverter circuit 46, and the current supply circuit 47 constitute a voltage follower. ing.

  Voltage divider circuit 44 includes an internal resistor R1 as a first resistor element formed on the display panel, an external resistor R2 as a second resistor element, Nch transistors Q10 and Q11, and a capacitor C5. . The internal resistor R1, the two Nch transistors Q10 and Q11, and the external resistor R2 are connected in series between the power supply line VLcc for supplying the voltage Vcc and the ground (ground line). . The connection point of the Nch transistors Q10 and Q11 is connected to one end of the capacitor C5 and to the output terminal To of the voltage dividing circuit 44, and the other end of the capacitor C5 is connected to the power supply line VLcc. Has been.

  The comparison circuit 45 includes an output unit including Pch transistors Q1 and Q2 and an Nch transistor Q3, and a threshold compensation circuit including a Pch transistor Q9, Nch transistors Q4 to Q8, and capacitors C1 to C4, and includes a first input terminal T1. Is compared with the voltage applied to the second input terminal T2, and a voltage indicating the comparison result is output. Specifically, the elements constituting the output unit and the threshold compensation circuit are connected as follows.

  That is, a Pch transistor Q1 (first transistor) for outputting a voltage indicating the comparison result, a Pch transistor Q2 as a switching element, and a voltage indicating the comparison result between the power supply line VLcc and the ground. An Nch transistor Q3 (second transistor) for output is connected in series. Since the first transistor Q1 and the second transistor Q3 constitute an output unit for outputting a voltage indicating the comparison result, the transistors Q1 and Q3 are hereinafter also referred to as “comparison output transistors”. .

  A capacitor C1 (first capacitor) is connected between the gate terminal of the Pch transistor Q1 (first transistor) and the power supply line VLcc, and a switching element is provided between the gate terminal and the drain terminal of the Pch transistor Q1. An Nch transistor Q4 (first switching element) is connected. Furthermore, one end of a capacitor C2 (second capacitor) is connected to the gate terminal of the Pch transistor Q1, and the other end of the capacitor C2 is connected to the comparison circuit via an Nch transistor Q8 (second switching element) as a switching element. The first input terminal T <b> 1 is connected to one end of the capacitor C <b> 5 via the output terminal To of the voltage dividing circuit 44. The other end of the capacitor C2 (second capacitor) is connected to the second input terminal T2 of the comparison circuit 45 via a Pch transistor Q9 (third switching element) as a switching element. The second input terminal T <b> 2 is connected to the output terminal Tout of the current supply circuit 47.

  In this embodiment, in order to show a particularly preferable example, an Nch transistor Q3 (second transistor) is further used as a comparison output transistor, and a capacitor C3 (third transistor) is connected between the gate terminal and the ground. A capacitor) is connected, and an Nch transistor Q5 (fifth switching element) as a switching element is connected between the gate terminal and the drain terminal. Furthermore, one end of a capacitor C4 (fourth capacitor) is connected to the gate terminal of the Nch transistor Q3, and the other end of the capacitor C4 is connected to the other end of the capacitor C2.

  The drain terminal of the Nch transistor Q3 (second transistor) and the drain terminal of the Pch transistor Q1 (first transistor) are connected to each other via a Pch transistor Q2 (fourth switching element) as a switching element. The drain terminal of the Nch transistor Q3 is the output terminal of the comparison circuit 45.

  Further, the gate terminal of the Pch transistor Q1 (first transistor) is connected to the ground via an Nch transistor Q6 as a switching element, and the gate terminal of the Nch transistor Q3 (second transistor) is Nch as a switching element. The transistor Q7 is connected to the power supply line VLcc.

  Inverter circuit 46 includes a Pch transistor Q12 whose source terminal is connected to power supply line VLcc, and an Nch transistor Q13 whose source terminal is connected to ground. The drain terminals of these transistors Q12 and Q13 are connected to each other, and the connection point is the output terminal of the inverter circuit 46. The gate terminals of these transistors Q12 and Q13 are also connected to each other, and the connection point serves as the input terminal of the inverter circuit 46. This input terminal is connected to the output terminal of the comparison circuit 45, that is, the drain terminal of the Nch transistor Q3.

  Current supply circuit 47 includes Pch transistors Q14-16, Nch transistor Q17, and capacitor C6, and these elements are connected as follows to form an inverter circuit with an output control function. That is, Pch transistors Q14, Q15, Q16 and Nch transistor Q17 are connected in series between power supply line VLcc and ground. A connection point between the Pch transistors Q15 and Q16 is connected to the power supply line VLcc via the capacitor C6 and to the output terminal Tout of the current supply circuit 47. The gate terminal of the Pch transistor Q14 and the gate terminal of the Nch transistor Q17 are connected to each other and become the input terminal of the current supply circuit 47. This input terminal is connected to the output terminal of the inverter circuit 46, that is, the drain terminals of the transistors Q12 and Q13. It is connected.

  As described above, the comparison circuit 45, the inverter circuit 46, and the current supply circuit 47 are configured such that the output terminal Tout of the current supply circuit 47 is connected to the second input terminal T2 of the comparison circuit 45. Constructs a voltage follower.

  Control signals Pc, Cc, and Rc described later are supplied from the display control circuit 100 as signals for controlling the voltage generator 41 configured as described above. That is, the gate terminals of the transistors Q6 and Q7 as switching elements are connected to each other and to a signal line that supplies the control signal Pc to the voltage generator 41. The gate terminals of the transistors Q4, Q5, Q8, Q9, Q10, and Q11 as switching elements are connected to each other and to a signal line that supplies the control signal Cc to the voltage generator 41. Furthermore, the gate terminals of the transistors Q2, Q15, and Q16 as switching elements are connected to each other and to a signal line that supplies the control signal Rc to the voltage generator 41.

  The voltage generator 41 configured as described above includes an external capacitor C7, and the output terminal Tout of the current supply circuit 47 is connected to the ground via the external capacitor C7.

<1.4 Operation of voltage generator>
A circuit composed of a comparison circuit 45, an inverter circuit 46, and a current supply circuit 47 by inputting the control signals Rc, Pc, and Cc that change at the timing shown in FIG. Operates as a voltage follower, and the voltage supplied from the voltage dividing circuit 44 to the comparison circuit 45 is impedance-converted and output from the current supply circuit 47. Hereinafter, details of the operation of the voltage generator 41 will be described.

  First, at time 0, the control signal Rc is set to High (GH) level to turn off the Pch transistors Q2, Q15, and Q16. As a result, the connection between the drain terminal of the Pch transistor Q1 and the drain terminal of the Nch transistor Q3 is disconnected, and the output current of the current supply circuit 47 is 0 regardless of the states of the Pch transistor Q14 and the Nch transistor Q17. Become.

  Next, at time t1, with the control signal Cc at the Low (GL) level, the control signal Pc is temporarily set at the High (GH) level, and the Nch transistors Q6 and Q7 are turned on. As a result, the potential of the gate terminal of the Pch transistor Q1 becomes the ground potential (ground potential), and the potential of the gate terminal of the Nch transistor Q3 becomes the power supply potential Vcc. Therefore, both the Pch transistor Q1 and the Nch transistor Q3 as the comparison output transistors are turned on.

  Next, at time 3t1, the control signal Cc is set to High (GH) level, and the Nch transistors Q4, Q5, Q8, Q10, and Q11 are turned on. As a result, a current flows from the power supply line VLcc to the ground in the voltage dividing circuit 44, and the voltage Vin divided by the resistors R1 and R2 is held in the capacitor C5. The voltage Vin is input from the first input terminal T1 to the comparison circuit 45, and is connected to the connection point between the capacitors C2 and C4 (the other ends of the capacitors C2 and C4) N1 via the ON-state Nch transistor Q8. (Hereinafter, the voltage Vin is referred to as “input voltage Vin”, and the connection point N1 is referred to as “input connection point N1”).

  Thereafter, the levels of the control signals Cc, Pc, Rc are maintained as they are until the Pch transistor Q1 and the Nch transistor Q3 are turned off, and at the time 5t1 after the transistors Q1, Q3 are turned off, the control signal Cc Is set to the Low (GL) level. At this time 5t1, the capacitor C1 connected between the gate terminal and the source terminal of the Pch transistor Q1 holds a voltage equal to the threshold voltage of the Pch transistor Q1, and the input connection point N1 and the gate of the Pch transistor Q1 A capacitor C2 connected to the terminal holds a voltage equal to the difference between the input voltage Vin and the threshold voltage of the Pch transistor Q1. In addition, a voltage equal to the threshold voltage of the Nch transistor Q3 is held in the capacitor C3 connected between the gate terminal and the source terminal of the Nch transistor Q3, and the input node N1 and the gate terminal of the Nch transistor Q3 are connected. The capacitor C4 connected in between holds a voltage equal to the difference between the input voltage Vin and the threshold voltage of the Nch transistor Q3. Therefore, regardless of variations in the threshold voltage of each transistor (TFT), the Pch transistor Q1 as the comparison output transistor is in the OFF state when the voltage at the input connection point N1 is equal to or higher than the input voltage Vin, and the voltage at the input connection point N1. Is turned on when the input voltage Vin is smaller than the input voltage Vin. On the other hand, the Nch transistor Q3 as the comparison output transistor is turned on when the voltage at the input connection point N1 is larger than the input voltage Vin, and the voltage at the input connection point N1. Is in the OFF state when is equal to or lower than the input voltage Vin. This means that charging of the capacitors C1 and C2 compensated for the threshold voltage of the Pch transistor Q1, and charging of the capacitors C3 and C4 compensated for the threshold voltage of the Nch transistor Q3.

  As described above, when the control signal Cc is set to the Low (GL) level at the time 5t1, the Nch transistors Q4, Q5, Q8, Q10, and Q11 are turned off at the same time, the Pch transistor Q9 is turned on, and the input connection point N1 ( The output voltage Vc of the current supply circuit 47 is applied to the connection point between the capacitors C2 and C4. Thus, the magnitude relationship between the output voltage Vc and the voltage Vin and the on / off states of the Pch transistor Q1 and the Nch transistor Q3 are associated as follows.

  At time 6t1, the control signal Rc is set to the Low (GL) level to turn on the Pch transistors Q2, Q15, and Q16. Thereby, the comparison circuit 45, the inverter circuit 46, and the current supply circuit 47 operate so that the output voltage Vc of the current supply circuit 47 becomes equal to the input voltage Vin from the voltage dividing circuit 44, as described below.

  FIG. 8 is a waveform diagram showing the results of simulating changes in the gate potential Vgp of the Pch transistor Q1 and the gate potential Vgn of the Nch transistor Q3 over the above-described period under the following conditions.

  In FIG. 8, the waveforms of the voltages Vgp (1) and Vgp (2) show the simulation results for the change in the gate potential Vgp of the Pch transistor Q1 under the conditions (1) and (2), respectively. The waveforms of Vgn (1) and Vgn (2) show the simulation results for the change in the gate potential Vgn of the Nch transistor Q3 under the conditions (1) and (2), respectively.

  When the control signal Cc becomes the Low (GL) level, as can be seen from the waveforms of the gate potentials Vgp (1), Vgp (2), Vgn (1), and Vgn (2) shown in FIG. It can be seen that the gate potential Vgp of the Pch transistor Q1 and the gate potential Vgn of the Nch transistor Q3 are voltages corresponding to the respective threshold voltages. Thus, after the time point when the control signal Cc becomes the Low (GL) level, the output voltage Vdn of the comparison circuit 45 does not depend on the variation of the threshold voltage of each transistor (TFT), as shown in Table 2. This is determined by the magnitude relationship between the output voltage Vc of the current supply circuit 47 and the input voltage Vin from the voltage dividing circuit 44.

  The output voltage Vdn of the comparison circuit 45 is inverted by the inverter circuit 46 and input to the input terminal of the current supply circuit 47, that is, the connection point between the gate terminal of the Pch transistor Q14 and the gate terminal of the Nch transistor Q17. Therefore, the ON / OFF states of Pch transistor Q14 and Nch transistor Q17 are set as follows according to the magnitude relationship between output voltage Vc of current supply circuit 47 and input voltage Vin from voltage dividing circuit 44.

  As described above, in the voltage generator 41 in the present embodiment, when the output voltage Vc of the current supply circuit 47 becomes smaller than the input voltage Vin from the voltage dividing circuit 44, the Pch transistor Q14 is turned on, and the output voltage Vc is increased. Let On the other hand, when the output voltage Vc of the current supply circuit 47 becomes larger than the input voltage Vin from the voltage dividing circuit 44, the Nch transistor Q17 is turned on, and the output voltage Vc is lowered. As a result, the output voltage Vc of the current supply circuit 47 is controlled to be equal to the input voltage Vin from the voltage dividing circuit 44. This means that a circuit including the comparison circuit 45, the inverter circuit 46, and the current supply circuit 47 operates as a voltage follower.

  Since this operation does not depend on the threshold voltage of the transistor (TFT) constituting the voltage generator 41, a desired potential can be generated only by changing the value of the external resistor R2. Therefore, a simulation result for confirming this point will be described below.

  FIG. 9 shows the output voltage Vdn of the comparison circuit 45 and the Pch transistor Q14 when the threshold and mobility of the Pch transistor and Nch transistor are set to the best conditions (mobility maximum, threshold minimum) in the circuit configuration shown in FIG. FIG. 14 is a waveform diagram showing the results of simulating changes in source-drain current Ip, source-drain current In of Nch transistor Q17, and output voltage Vc of current supply circuit 47. According to this simulation result, although the stability of the output voltage Vc varies depending on the capacitance value of the external capacitor C7, it is assumed that C7 = 1 [μF], the internal resistance R1 = 100 [kΩ], and the external resistance R2 = 1 [MΩ. When the variation of the output voltage Vc was examined under the condition of the power supply voltage Vcc = 8 [V], Vc = 7.04 to 7.16 [V]. Note that the load of the voltage generator 41 at this time is a resistor connected between the output terminal Tout and the ground (GND).

  On the other hand, FIG. 10 shows that the threshold voltage / mobility of the Pch transistor and Nch transistor is set to the worst condition (mobility minimum, threshold maximum) in the circuit configuration shown in FIG. It is a waveform diagram showing the result of simulating changes in the source-drain current Ip of the transistor Q14, the source-drain current In of the Nch transistor Q17, and the output voltage Vc of the current supply circuit 47. According to this simulation result, when the variation in the output voltage Vc is examined under the same conditions as described above for the external capacitor C7, the internal resistor R1, the external resistor R2, and the power supply voltage Vcc, Vc = 7.24 to 7.26 [ V].

  In the above two simulations, the threshold voltage variation of the Pch transistor and the Nch transistor is set to about 2 [V]. However, since only a difference of about 0.1 [V] appears in the output voltage Vc under these conditions, the voltage It can be said that a sufficiently uniform voltage was obtained as the output voltage of the generating means.

  Thus, according to the voltage generator 41 in the present embodiment, a control voltage determined by the external resistor R2 can be obtained even in a configuration using a thin film transistor (TFT) having a large variation in threshold voltage. Therefore, the labor for adjusting the output voltage can be saved, and the cost can be reduced accordingly. Further, by changing the value of the external resistor R2, it is possible to flexibly cope with the improvement of the element characteristics, so that the delivery time of the display device using the voltage generator 41 can be shortened and the cost can be reduced.

  In the comparison circuit 45 of FIG. 6, the capacitors C1 and C3 are not necessarily required because the gate terminal of each transistor has a stray capacitance.

<2. Second Embodiment>
In the first embodiment, as shown in the simulation results of FIGS. 9 and 10, current flows through either the Pch transistor Q14 or the Nch transistor Q17 while the control signal Rc is at the Low (GL) level. For this reason, there is a problem that a large amount of current flows wastefully in the current supply circuit 47 due to the current supply from the voltage generator 41 (the generation means of the control voltage Vc) configured as shown in FIG. There is. On the other hand, if the nature of the load of the voltage generator 41 is examined and it can be specified whether the load pulls the voltage toward the power supply voltage Vcc side or the load pulls the voltage toward the ground potential (ground potential GND) side. The above problems can be solved.

  For example, as shown in FIG. 3, the analog switch circuit 40 included in the display panel 300 in the first embodiment shown in FIG. 2 uses the power supply voltage Vcc and the control voltage Vc from the voltage generator 41 as shown in FIG. There is no other power source that is switched between and supplied to the potential wiring ULi and connected to the potential wiring ULi. Therefore, the direction in which the output of the voltage generator 41 is pulled can be specified as the power supply voltage Vcc side. Therefore, the Pch transistors Q14 and Q15 can be removed from the current supply circuit 47 shown in FIG. 6, and a current supply circuit 47b as shown in FIG. 11 can be used. Hereinafter, a display device including the voltage generator 41b shown in FIG. 11 using the current supply circuit 47b will be described as a display device according to the second embodiment of the present invention. However, since the configuration other than the voltage generator 41b in the present embodiment is substantially the same as that of the first embodiment, detailed description thereof will be omitted, and hereinafter, the configuration and operation of the voltage generator 41b will be mainly described. . In addition, the same reference numerals are assigned to the same portions of the configuration of the voltage generator 41b in the present embodiment as in the configuration of the voltage generator 41 in the first embodiment.

  In the voltage generator 41b in this embodiment, as shown in FIG. 11, in the comparison circuit 45, the drain terminal of the Pch transistor Q1 serves as the output terminal instead of the drain terminal of the Nch transistor Q3, and the drain terminal of the Pch transistor Q1 Are connected to the gate terminals of Pch transistor Q12 and Nch transistor Q13 in inverter circuit 46. Except for this point, the internal configurations of the voltage dividing circuit 44, the comparison circuit 45, and the inverter circuit 46 of the voltage generator 41b in this embodiment are the same as those in the first embodiment (the external capacitor C7 and the external capacitor C7). The same applies to the connection of the resistor R2.) Further, the control signals Rc, Pc, and Cc input to the voltage generator 41b in the present embodiment also change at the timing shown in FIG. 7 as in the first embodiment.

  As described above, in the comparison circuit 45, the drain terminal of the Pch transistor Q1 is used as the output terminal. The voltage Vin obtained by the voltage dividing circuit 44 is input to the comparison circuit 45, and the Pch transistor Q1 and the Nch transistor in the comparison circuit 45 are input. Immediately after the end of the period (first predetermined period) for charging the capacitors C1, C2, C3, and C4 to compensate for the threshold voltage of Q3, that is, immediately after time 5t1 shown in FIG. This is because the Nch transistor Q17 should be set to be in the OFF state. In order to turn off the Nch transistor Q17, it is necessary to apply a potential on the ground line side (GND side) to its gate terminal, and considering that the output from the comparison circuit 45 is inverted by the inverter circuit 46. The power supply voltage must be on the Vcc side. Therefore, as the output terminal of the comparison circuit 45, the drain terminal of the Nch transistor Q3 is not preferable, and the drain terminal of the Pch transistor Q1 is preferable.

  FIG. 12 shows the threshold voltage / mobility of the Pch transistor and Nch transistor set to the best conditions (maximum mobility, minimum threshold) in the circuit configuration shown in FIG. 11, and the drain voltage Vdn of the Nch transistor Q3 of the comparison circuit 45. FIG. 14 is a waveform diagram showing the results of simulating changes in the source-drain current In of the Nch transistor Q17 of the current supply circuit 47b and the output voltage Vc of the current supply circuit 47b. The conditions such as the capacitance value of the external capacitor C7, the value of the external resistor, and the power supply voltage Vcc in this simulation are the same as those in the simulation for obtaining the result shown in FIG. According to the simulation result shown in FIG. 12, it can be seen that the current flowing through the current supply circuit 47b (source-drain current In of the Nch transistor Q17) is reduced compared to the simulation result of FIG. That is, as shown in FIG. 12, the current In flows about once every 1 ms, which is much less than the currents Ip and In that flow every 0.2 ms in the simulation result of FIG. ing. Further, when the variation of the output voltage Vc was examined under the above conditions, it was Vc = 7.25 to 7.31 [V].

  On the other hand, FIG. 13 shows that the threshold and mobility of the Pch transistor and the Nch transistor are set to the worst conditions (minimum mobility and maximum threshold) in the circuit configuration shown in FIG. It is a wave form diagram showing the result of having simulated the change of voltage Vdn, source-drain current In of Nch transistor Q17, and output voltage Vc of current supply circuit 47b. The conditions such as the capacitance value of the external capacitor C7, the value of the external resistor, and the power supply voltage Vcc in this simulation are the same as those in the simulation for obtaining the result shown in FIG. According to the simulation result shown in FIG. 13, it can be seen that the current flowing through the current supply circuit 47b (the source-drain current In of the Nch transistor Q17) is reduced compared to the simulation result of FIG. That is, as shown in FIG. 13, the current In flows about once every 1 ms, which is much less than the currents Ip and In that flow every 0.2 ms in the simulation results of FIG. ing. Further, when the variation of the output voltage Vc was examined under the above conditions, it was Vc = 7.25 to 7.26 [V].

  In the above two simulations, the threshold voltage variation of the Pch transistor and the Nch transistor is set to about 2 [V]. However, only a difference of about 0.05 [V] appears in the output voltage Vc under these conditions. It can be said that a sufficiently uniform voltage can be obtained as the output voltage of the generating means.

  As described above, according to the voltage generator 41b in the present embodiment, similarly to the first embodiment, even when the thin film transistor (TFT) having a large variation in threshold voltage is used, the control is determined by the external resistor R2. Since the voltage can be obtained, the labor for adjusting the output voltage for each panel can be saved, and the cost can be reduced accordingly. Moreover, according to the present embodiment, since only the current necessary for maintaining the output voltage Vc flows in the current supply circuit constituting the voltage generator 41b, the power consumption can be reduced as compared with the first embodiment. it can.

<3. Modification>
<3.1 First Modification>
The pixel circuit shown in FIG. 3 as the pixel circuit in the first and second embodiments has a configuration for displaying a monochrome image. On the other hand, in order to perform color image display, a pixel circuit having the configuration shown in FIG. 14 may be used instead of the pixel circuit having the configuration shown in FIG. Hereinafter, the configuration of a pixel circuit for performing color image display will be described with reference to FIG. In the following description, in the pixel circuit configuration for performing color image display, the same or corresponding parts as those of the pixel circuit configuration shown in FIG. (The same applies to other modifications described below).

  FIG. 14 shows a configuration of a pixel circuit for performing color image display based on the three primary colors of R (red), G (green), and B (blue). Here, R is a pixel circuit for red. An adjacent three-pixel circuit including a pixel circuit Ar (i, j), a G pixel circuit Ag (i, j) that is a pixel circuit for green, and a B pixel circuit Ab (i, j) that is a pixel circuit for blue. A display panel is configured as a unit for displaying a color image. When displaying a color image with such a configuration, as shown in FIG. 14, the current value to be output from the driving transistor Q21 is different for each RGB color, so that instead of the potential wiring ULi in the case of monochrome display, RGB Three potential wirings ULri, ULgi, ULbi corresponding to each color are required.

  On the other hand, one electrode of the capacitor C11 to be connected between the gate terminal of the driving transistor Q21 and any of the potential wirings ULri, ULgi, ULbi is connected to the potential wiring Uxi (x =) to be connected to one end of the capacitor C11. If formed by r, g, b), the capacitor C11 can be formed in the potential wiring region, so that the area of the pixel circuit can be reduced. Therefore, when one electrode of the capacitor C11 is formed by the potential wiring Uxi in order to reduce the area of each pixel circuit with the configuration of adjacent three pixel circuits corresponding to RGB three colors as a unit, these adjacent three pixel circuits Ar ( i, j), Ag (i, j), and Ab (i, j) have a circuit configuration as shown in FIG. That is, in each pixel circuit Ar (i, j), Ag (i, j), Ab (i, j), two capacitors Ca and one capacitor Ca are formed as capacitors corresponding to the capacitor C11. .

  In this case, as shown in FIG. 16, the width of the potential wiring ULri is thickened in the region of the R pixel circuit Ar (i, j), and the width of the potential wiring ULgi is thickened in the region of the G pixel circuit Ag (i, j). Then, the width of the potential wiring ULbi is increased in the region of the B pixel circuit Ab (i, j), the potential wirings ULri, ULgi, ULbi and their pixel circuits Ar (i, j), Ag (i, j). , Ab (i, j), capacitors Ca and Cb corresponding to the capacitor C11 are formed between the silicon electrodes Sr (i, j), Sg (i, j), and Sb (i, j). For example, in the R pixel circuit Ar (i, j), a capacitor Ca is formed between the potential wiring ULbi and the silicon electrode Sr (i, j) and between the potential wiring ULgi and the silicon electrode Sr (i, j). The capacitor Cb is formed between the potential wiring ULri and the silicon electrode Sr (i, j).

Even when the capacitors Ca and Cb are formed in this way, the time 8t1 shown in FIG. 4 is a period in which the gate potential is set corresponding to the threshold voltage of the driving transistor Q21 of the pixel A (i, j). In the period 28t1 (hereinafter referred to as “threshold correction period”), the potential Vcc is applied to the potential wirings ULbi, ULgi, ULri, and then appropriate potentials are applied to the potential wirings ULbi, ULgi, ULri, respectively. The output current of the driving transistor Q21 of the pixel circuits Ar (i, j), Ag (i, j), and Ab (i, j) respectively corresponding to can be set to a desired current value. Here, the appropriate potentials to be applied to the potential wirings ULbi, ULgi, and ULri after the threshold correction period are set as Vcc-V1, Vcc-V2, and Vcc-V3, respectively, and the pixel circuit Ar ( If the amount of change in the gate potential of the driving transistor Q21 at i, j), Ag (i, j), and Ab (i, j) is Vr, Vg, and Vb, respectively, the following relationship is established. In the following, reference symbols “Ca” and “Cb” indicating capacitors also indicate capacitance values of these capacitors.
Ca (−V1 + Vr) + Ca (−V2 + Vr) + Cb (−V3 + Vr) = 0
Ca (−V1 + Vg) + Cb (−V2 + Vg) + Ca (−V3 + Vg) = 0
Cb (−V1 + Vb) + Ca (−V2 + Vb) + Ca (−V3 + Vb) = 0
Therefore,
(2Ca + Cb) Vr = Ca (V1 + V2) + Cb · V3
(2Ca + Cb) Vg = Ca (V1 + V3) + Cb · V2
(2Ca + Cb) Vb = Ca (V2 + V3) + Cb · V1
It becomes. By adjusting the voltages V1, V2, and V3, the voltages Vr, Vg, and Vb that determine the output current of the driving transistor Q21 for each of the RGB pixels are adjusted by adjusting the voltages V1, V2, and V3. can do.

<3.2 Second Modification>
If the amount of change Vr, Vg, Vb of the gate potential of the driving transistor Q21 is determined in advance for each pixel of RGB, it is connected between the potential wiring and the gate terminal of the driving transistor Q21 in the pixel circuit of FIG. By changing the area ratio of the capacitor corresponding to the capacitor C11, the potential wirings ULri, ULgi, ULbi can be unified. For example, capacitors Cr1 and Cr2, Cg1 and Cg2, and Cb1 and Cb2 corresponding to the capacitor C11 can be formed as shown in FIG. 17, and the potential wiring ULi can be unified. That is, in the R pixel circuit Ar (i, j), the capacitor Cr1 is formed on the potential wiring ULi side, and the capacitor Cr2 is formed on the power supply wiring VLpr side. In the G pixel circuit Ag (i, j), the capacitor Cg1 is formed on the potential wiring ULi side. The capacitor Cg2 is formed on the power supply line VLpg side, and the capacitor Cb1 is formed on the potential line ULi side and the capacitor Cb2 is formed on the power supply line VLpb side in the B pixel circuit Ab (i, j). In this case, the potential to be applied to the potential wiring ULi after the threshold correction period is set to Vcc−V1 (that is, the potential change amount of the potential wiring ULi after the threshold correction period is set to V1), and the pixel circuits Ar (i, j), If the amount of change in the gate potential of the driving transistor Q21 at Ag (i, j) and Ab (i, j) is Vr, Vg and Vb, respectively, the following relationship is established. In the following, reference numerals “Cx1” and “Cx2” (x = r, g, b) indicating capacitors also indicate capacitance values of these capacitors.
Cr1 (−V1 + Vr) + Cr2 · Vr = 0
Cg1 (−V1 + Vg) + Cg2 · Vg = 0
Cb1 (−V1 + Vb) + Cb2 · Vb = 0
From the above relational expression, the area ratio (x = r, g, b) between the capacitors Cx1 and Cx2 may be set so as to satisfy the following expression.
Cr2 / Cr1 = Vr / (V1-Vr)
Cg2 / Cg1 = Vg / (V1-Vg)
Cb2 / Cb1 = Vb / (V1-Vb)

<3.3 Third Modification>
One electrode of the capacitor C11 in the pixel circuit having the configuration shown in FIG. 14 may be formed by a power supply wiring and a potential wiring as shown in FIGS. That is, in the R pixel circuit Ar (i, j), one electrode of the capacitor C11 is formed by the power supply wiring VLpr and the potential wiring ULri, and in the G pixel circuit Ag (i, j), one electrode of the capacitor C11 is formed by the power supply wiring VLpg. And the potential wiring ULri and the potential wiring ULgi, and in the B pixel circuit Ab (i, j), one electrode of the capacitor C11 may be formed by the power supply wiring VLpb, the potential wiring ULri, the potential wiring ULgi, and the potential wiring ULbi. . Thereby, as shown in FIG. 18, in the R pixel circuit Ar (i, j), a capacitor Ca is formed between the gate terminal of the driving transistor Q21 and the potential wiring ULri as a capacitor corresponding to the capacitor C11. A capacitor Cb is formed between the gate terminal and the power supply wiring VLpr. In the G pixel circuit Ag (i, j), a capacitor Ca is formed between the gate terminal of the driving transistor Q21 and the potential wirings ULri and ULgi as a capacitor corresponding to the capacitor C11. A capacitor Cb is formed between the wiring VLpg. In the B pixel circuit Ab (i, j), a capacitor Ca is formed as a capacitor corresponding to the capacitor C11 between the gate terminal of the driving transistor Q21 and the potential wirings ULri, ULgi, and ULbi. A capacitor Cb is formed between the power supply wiring VLpb.

  In the case of the above configuration, first, the potential of the potential wiring ULri is adjusted to match the luminance of the R pixel. Next, the potential of the potential wiring ULgi is adjusted to match the luminance of the G pixel. Finally, the potential of the potential wiring ULbi is adjusted to match the luminance of the B pixel. In this way, it is possible to easily adjust the luminance of each RGB pixel.

  Further, in the case of the configuration as described above, the power supply wirings VLpr, VLpg, VLpb can be wired in parallel with the potential wirings ULri, ULgi, ULbi (see FIG. 19). In this way, the potentials are averaged between the power supply lines VLp of adjacent pixels, crosstalk and the like are prevented, and display luminance is stabilized.

<3.4 Voltage Generator in Modification>
Voltage generation for generating a potential signal Ui or potential signals Uri, Ugi, Ubi, which is a voltage applied to the pixel circuits of the first to third modifications via the potential wiring ULi or the potential wirings ULri, ULgi, ULbi. By using the voltage generators 41 and 41b having the configurations shown in FIGS. 6 and 11 as means, a necessary voltage can be obtained without using an external operational amplifier. In this manner, the display quality of the display device is improved by using the voltage generators 41 and 41b in the first or second embodiment and the pixel circuit having the configuration shown in FIGS. Can do.

<3.5 Other modifications>
In the first and second embodiments, TFTs (thin film transistors) are used as active elements such as driving transistors, comparative output transistors, and switching element transistors. However, the present invention is limited to this. A field effect transistor other than a TFT may be used instead. However, when a TFT is used, the pixel circuit, the drive circuit, and the voltage generator in a display panel such as a liquid crystal panel or an organic EL panel are integrated with an insulating substrate such as a glass substrate that constitutes the display panel. Since it can be formed, it is advantageous in terms of reduction in the number of parts and cost in the display device.

  In the first and second embodiments, the comparison circuit 45, the inverter circuit 46, and the current supply circuit 47 constituting the voltage generators 41 and 41b are complementary types that use a Pch transistor and an Nch transistor in pairs. However, the present invention is not limited to this, and a part or all of the comparison circuit 45, the inverter circuit 46, and the current supply circuit 47 are either a Pch transistor or an Nch transistor. It is good also as a circuit structure in which one side is used. For example, when the Nch transistor Q3 and the related (C3, C4, Q5, Q7) are deleted from the output section of the comparison circuit 45, a load transistor corresponding to a resistor or a resistor is provided between the Pch transistor Q2 and the ground. What is necessary is just to set it as the structure to connect.

  The voltage follower in the first and second embodiments can be used not only as a component of the voltage generators 41 and 41b but also for other uses. For example, a source in a liquid crystal display device It can also be used as a driver output buffer.

It is a block diagram which shows the structure of the display apparatus which concerns on the 1st Embodiment of this invention. It is a block diagram which shows the structure of the display panel in the said 1st Embodiment. FIG. 3 is a circuit diagram illustrating configurations of a pixel circuit and a second gate driver circuit in the first embodiment. FIG. 4 is a waveform diagram showing operation timings of the pixel circuit shown in FIG. 3. FIG. 4 is a waveform diagram showing a result of simulating changes in a gate potential Vg, a drain potential Vd, and a source-drain current Ids of a driving TFT in the pixel circuit shown in FIG. 3. It is a circuit diagram which shows the structure of the voltage generator (part which produces | generates the control voltage Vc) in the said 1st Embodiment. FIG. 7 is a waveform diagram showing operation timings of the voltage generator shown in FIG. 6. FIG. 7 is a waveform diagram showing the results of simulating changes in the gate potential Vgp of Pch transistor Q1 and the gate potential Vgn of Nch transistor Q3 in the voltage generator shown in FIG. 6; The threshold and mobility of the Pch transistor and Nch transistor in the voltage generator shown in FIG. 6 are set to the best conditions (maximum mobility, minimum threshold), the source-drain current Ip of the Pch transistor Q14, and the Nch transistor Q17. It is a wave form diagram which shows the result of having simulated the change of source-drain electric current In and the output voltage Vc of a voltage generator. The threshold and mobility of the Pch transistor and Nch transistor in the voltage generator shown in FIG. 6 are set to the worst conditions (mobility minimum, threshold maximum), the source-drain current Ip of the Pch transistor Q14, the Nch transistor Q17 It is a wave form diagram which shows the result of having simulated the change of source-drain electric current In and the output voltage Vc of a voltage generator. It is a circuit diagram which shows the structure of the voltage generator in the display apparatus which concerns on the 2nd Embodiment of this invention. The threshold and mobility of the Pch transistor and Nch transistor in the voltage generator shown in FIG. 11 are set to the best conditions (maximum mobility, minimum threshold), and the source-drain current In of the Nch transistor Q17 and voltage generation It is a wave form diagram which shows the result of having simulated the change of the output voltage Vc of a device. The threshold value / mobility of the Pch transistor and the Nch transistor in the voltage generator shown in FIG. 11 is set to the worst conditions (minimum mobility, maximum threshold value), the source-drain current In of the Nch transistor Q17, and voltage generation It is a wave form diagram which shows the result of having simulated the change of the output voltage Vc of a device. FIG. 6 is a circuit diagram illustrating a configuration of a color image display pixel circuit which is a first modification of the pixel circuit in the first and second embodiments. FIG. 6 is a circuit diagram illustrating a configuration of a color image display pixel circuit which is a second modification of the pixel circuit in the first and second embodiments. FIG. 16 is a layout diagram illustrating a configuration of a capacitor in a pixel circuit according to a second modification illustrated in FIG. 15. FIG. 10 is a circuit diagram showing a configuration of a pixel circuit for color image display which is a third modification of the pixel circuit in the first and second embodiments. FIG. 10 is a circuit diagram showing a configuration of a color image display pixel circuit which is a fourth modification of the pixel circuit in the first and second embodiments. FIG. 19 is a layout diagram illustrating a configuration of a capacitor for the pixel circuit illustrated in FIG. 18. It is a circuit diagram which shows the structural example of the drive voltage supply circuit as a voltage generator used with the conventional display apparatus. FIG. 21 is a circuit diagram illustrating a configuration example of an operational amplifier used in the drive voltage supply circuit illustrated in FIG. 20. It is a circuit diagram which shows the structural example of the conventional voltage follower used in the data driver of a liquid crystal display device.

Explanation of symbols

DESCRIPTION OF SYMBOLS 31 ... Display part 32 ... Source driver circuit 33 ... 1st gate driver circuit 38 ... 2nd gate driver circuit 34, 39 ... Shift register circuit 35 ... Register circuit 36 ... Latch 37, 40 ... Analog switch circuit 41, 41b ... Voltage generator 44 ... Voltage dividing circuit 45 ... Comparison circuit 46 ... Inverter 47, 47v ... Current supply circuit 100 ... Display control circuit 300 ... Display panel 500 ... Power supply circuit A (i, j) ... Pixel circuit (i = 1 to m) , J = 1 to n)
SLj: Source wiring (j = 1 to n)
GLi: Gate wiring (i = 1 to m)
PLi: Control wiring (i = 1 to m)
VLp: power supply wiring ULi: potential wiring (i = 1 to m)
T1 ... First input terminal T2 ... Second input terminal Tout ... Output terminal Q1 ... Pch transistor (first transistor)
Q2 Pch transistor (fourth switching element)
Q3 ... Nch transistor (second transistor)
Q4 ... Nch transistor (first switching element)
Q5 ... Nch transistor (fifth switching element)
Q6 ... Nch transistor (switching element)
Q7 ... Nch transistor (switching element)
Q8 ... Nch transistor (second switching element)
Q9 ... Pch transistor (third switching element)
C1, C3 ... Capacitor (gate-source capacitor)
C2, C4 ... Capacitors (input capacitors)

Claims (10)

A voltage follower that has first and second input terminals and an output terminal connected to the second input terminal, and that outputs a voltage substantially equal to the voltage applied to the first input terminal from the output terminal. There,
A comparison circuit that compares a first input voltage applied to the first input terminal and a second input voltage applied to the second input terminal;
A current supply circuit for supplying current from the output terminal,
The comparison circuit is
A field effect transistor for comparing the first input voltage and the second input voltage;
A threshold compensation circuit for compensating a threshold voltage of the field effect transistor,
The current supply circuit reduces the voltage of the output terminal when the second input voltage is higher than the first input voltage based on the output voltage of the comparison circuit, and the second input voltage is the first input voltage. A voltage follower, wherein when the input voltage is lower than 1, the voltage at the output terminal is increased. The comparison circuit includes a first transistor as the field effect transistor,
The threshold compensation circuit includes:
A first capacitor connected between a gate terminal and a source terminal of the first transistor;
A second capacitor having one end connected to the gate terminal of the first transistor;
A first switching element connected between a gate terminal and a drain terminal of the first transistor;
A second switching element connected between the other end of the second capacitor and the first input terminal and turned on / off in conjunction with the first switching element;
Including a third switching element connected between the other end of the second capacitor and the second input terminal and turned on / off in a reciprocal manner with the first switching element, The voltage follower according to claim 1. The comparison circuit is
A second transistor as the field effect transistor having a channel shape different from that of the first transistor;
A fourth switching element connected between the drain terminal of the first transistor and the drain terminal of the second transistor, and turned off when the first switching element is on; The threshold compensation circuit includes:
A third capacitor connected between a gate terminal and a source terminal of the second transistor;
A fourth capacitor connected between the gate terminal of the second transistor and the other end of the second capacitor; and connected between a gate terminal and a drain terminal of the second transistor; The voltage follower according to claim 2, further comprising a fifth switching element that is turned on / off in conjunction with the one switching element.   4. The voltage follower according to claim 1, wherein the current supply circuit includes a third transistor that is a field effect transistor for supplying a current from the output terminal. 5.   5. The current supply circuit according to claim 4, further comprising a fourth transistor that is a field effect transistor having a channel type different from that of the third transistor and forms an inverter circuit together with the third transistor. The voltage follower described.   6. The voltage follower according to claim 5, wherein the first to fourth transistors and the first to fifth switching elements are thin film transistors. The threshold compensation circuit includes:
A gate-source capacitor connected between a gate terminal and a source terminal of the field effect transistor; and an input capacitor having one end connected to the gate terminal of the field effect transistor;
During the first predetermined period, the gate-source capacitor is charged to a voltage equal to the threshold voltage of the field effect transistor, and the input capacitor is charged with a difference between the first input voltage and the threshold voltage of the field effect transistor. To a voltage equal to
Applying the second input voltage to the other end of the input capacitor in a second predetermined period after the first predetermined period;
2. The voltage follower according to claim 1, wherein the field effect transistor outputs a voltage indicating a comparison result between the first input voltage and the second input voltage during the second predetermined period. .   A display device comprising the voltage follower according to claim 1. A display device comprising a voltage generator,
The voltage generator is
The voltage follower according to any one of claims 1 to 7,
And a voltage dividing circuit for generating the first input voltage. The display device according to claim 9, wherein the voltage dividing circuit includes first and second resistance elements that determine the first input voltage.

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