JP2002175034A - Active matrix type display device and portable terminal using the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide an active matrix type display device, enabling to miniaturization, decrease in noise, and also reduction in power consumption by making the device correspond to a power-saving mode. SOLUTION: The active matrix type liquid crystal display device, provided with a power supply circuit 15 comprising, for example, a charge pump type power supply voltage conversion circuit (DC-DC converter) for converting a single DC power supply voltage VCC into plural kinds of DC voltages of different voltage values and supplying them to H-drivers 13U, 13D, a V-driver 14, and a timing control circuit 16, a signal synchronized with a video signal, for example, a horizontal synchronous signal HD is used as a reference clock signal for the switching operation of the power supply circuit 15.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an active matrix display device and a portable terminal using the same, and more particularly, to an active matrix display device having a power supply circuit for converting a single DC voltage into a plurality of types of DC voltages having different voltage values. The present invention relates to a matrix type display device and a mobile terminal using the same for a display unit.

[0002]

2. Description of the Related Art In recent years, portable telephones and PDAs (Personal Digital
gital Assistants) and other mobile terminals are remarkable. One of the factors behind the rapid spread of these mobile devices is that
There is a liquid crystal display device mounted as the output display unit. The reason is that the liquid crystal display device has a characteristic that does not require power for driving in principle, and is a display device with low power consumption.

In a portable terminal, a battery of a single power supply voltage is used as a power supply. On the other hand, in a liquid crystal display device,
In a horizontal drive circuit that drives pixels arranged in a matrix, different DC voltages are used in the logic unit and the analog unit, and a vertical drive circuit that writes information to pixels has a larger absolute value than the horizontal drive circuit side. A DC voltage will be used. Therefore, a liquid crystal display device mounted on a portable terminal includes a power supply voltage conversion circuit (DC-DC) for converting a single DC voltage into a plurality of types of DC voltages having different voltage values.
Converter) is used as a power supply circuit.

The following two typical display devices are provided with a power supply circuit. One of them, that is, the display device according to Conventional Example 1 includes an oscillation circuit 102 when a charge pump type DC-DC converter is used as the power supply circuit 101, as shown in FIG. The generated clock is used as a clock for the switching operation of the power supply circuit 101. The DC voltage obtained by DC-DC conversion in the power supply circuit 101 is supplied to the timing control circuit 103 and the driver circuit 104.

[0005] The timing control circuit 103 operates using a DC voltage supplied from the power supply circuit 101 as a circuit power supply, and sends various signals to the driver circuit 104 based on a horizontal synchronization signal, a vertical synchronization signal, and a master clock signal supplied from outside. Is given. The driver circuit 104 is for driving a display area 105 in which a large number of pixels are arranged in a matrix, and includes a vertical drive system for selecting each pixel in the display area 105 on a row-by-row basis. A horizontal drive system for writing image information to each pixel in a row selected by the drive system.

As shown in FIG. 10, a display device according to another one of the prior arts, that is, a conventional example 2, has a horizontal transfer clock which is one of various timing signals generated by a timing control circuit 103. Is used as an operation clock of the power supply circuit 101. here,
The horizontal transfer clock is a clock signal used for circuit operation of a horizontal drive system in the driver circuit 104.

[0007]

Among these two prior arts, in the display device according to the prior art 1, the power supply circuit 101 is used.
Since it is not necessary to take in a clock signal used for the operation of the power supply circuit from the outside, even if the master clock signal is interrupted in a power saving mode or the like, there is an advantage that the power supply circuit 101 operates stably. Since the circuit area is increased by the provision of the circuit 102, and the oscillation clock of the oscillation circuit 102 is not synchronized with the video signal displayed on the display area 105, noise is generated to cause image disturbance or the like. There is a problem.

On the other hand, the display device according to the conventional example 2 has the advantages that the circuit area can be reduced by the unnecessary amount of the oscillation circuit 102 used in the conventional example 1, and image disturbance due to noise can be reduced. However, since the power supply circuit 101 must always be operating and cannot stop the horizontal transfer clock, the master clock signal serving as the reference of the horizontal transfer clock cannot be stopped in a power saving mode or the like. There is a problem that an effective low power consumption mode cannot be realized.

SUMMARY OF THE INVENTION The present invention has been made in view of the above problems, and has as its object to reduce the power consumption by making it possible to reduce the size and noise and to cope with a power saving mode. An active matrix display device and a portable terminal using the same are provided.

[0010]

In order to achieve the above object, according to the present invention, there is provided a display area in which pixels having electro-optical elements are arranged in a matrix, and each pixel in the display area is divided into rows. And a horizontal drive circuit for supplying an image signal to each pixel in a row selected by the vertical drive circuit. The power supply circuit that converts the DC voltage into a plurality of different types of DC voltages and supplies the DC voltage to at least the vertical drive circuit and the horizontal drive circuit operates based on a synchronization signal synchronized with a video signal displayed on the display area unit. This active matrix display device is used as a display unit of a portable terminal.

In the active matrix display device having the above configuration or a portable terminal using the same, the synchronization signal synchronized with the video signal is a reference signal for display control. The use of the clock signal as a reference for the clock signal eliminates the need for a circuit for generating the clock signal, and since the signal is originally synchronized with the video signal, noise due to the asynchronousness of the clock signal and the video signal is generated. Nor.

[0012]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention. Here, for example, a case where the present invention is applied to an active matrix type liquid crystal display device using a liquid crystal cell as an electro-optical element of each pixel will be described.

In FIG. 1, a pair of upper and lower H drivers (horizontal drive circuits) 13U are provided on a transparent insulating substrate, for example, a glass substrate 11, together with a display area 12 in which a large number of pixels including liquid crystal cells are arranged in a matrix. , 13D and a V driver (vertical drive circuit) 14, and a power supply circuit 15 and a timing control circuit 16 are integrated. The glass substrate 11 has an active element (for example,
The first substrate includes a plurality of pixel circuits including transistors, and the second substrate is disposed to face the first substrate with a predetermined gap. Then, a liquid crystal is sealed between the first and second substrates.

FIG. 2 shows an example of a specific configuration of the display area section 12. Here, for simplification of the drawing, a case of a pixel array of 3 rows (n-1 row to n + 1 row) and 4 columns (m-2 column to m + 1 column) is taken as an example. In FIG. 2, vertical scanning lines...
−1, 21n, 21n + 1,..., And data lines.
, 2m-2, 22m-1, 22m, 22m + 1,... Are wired in a matrix, and the intersection of the unit pixels 2
3 are arranged.

The unit pixel 23 has a configuration including a thin film transistor TFT as a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs. Here, the liquid crystal cell LC
Means a capacitance generated between a pixel electrode (one electrode) formed by a thin film transistor TFT and a counter electrode (the other electrode) formed opposite to the pixel electrode.

In the thin film transistor TFT, the gate electrodes have vertical scanning lines..., 21n-1, 21, n, 21n + 1,
, And the source electrode is connected to the data line.
2, 22m-1, 22m, 22m + 1,... In the liquid crystal cell LC, the pixel electrode is a thin film transistor T
The counter electrode is connected to the common line 24 and the drain electrode of the FT is connected. The storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 24. A predetermined DC voltage is applied to the common line 24 as a common voltage Vcom.

Vertical scanning lines..., 21n-1, 21n,
21n + 1 are connected to the V driver 14 shown in FIG.
Is connected to each output terminal of the corresponding row of. The V driver 14 is configured by, for example, a shift register,
A vertical selection pulse is sequentially generated in synchronization with a vertical transfer clock VCK (not shown) to generate vertical scanning lines.
, 21n + 1, 21n + 1,... To perform vertical scanning.

On the other hand, in the display area section 12, for example, odd-numbered data lines..., 22m-1, 22m +
, 22m are connected to the respective output ends of the corresponding columns of the H driver 13U shown in FIG.
Each of the other ends of −2, 22 m,.
D is connected to each output terminal of the corresponding column. FIG. 3 shows an example of a specific configuration of the H drivers 13U and 13D.

As shown in FIG. 3, the H driver 13U includes:
The configuration includes a shift register 25U, a sampling latch circuit (data signal input circuit) 26U, a line sequential latch circuit 27U, and a DA conversion circuit 28U. The shift register 25U performs horizontal scanning by sequentially outputting a shift pulse from each transfer stage in synchronization with a horizontal transfer clock HCK (not shown). The sampling latch circuit 26U responds to a shift pulse given from the shift register 25U, and samples and latches input digital image data of predetermined bits in a dot-sequential manner.

The line-sequentializing latch circuit 27U re-latches the digital image data latched dot-sequentially by the sampling latch circuit 26U on a line-by-line basis, thereby line-sequentially converting the digital image data for one line. Output to The DA conversion circuit 28U has, for example, a circuit configuration of a reference voltage selection type, and has a line-sequential latch circuit 27.
The digital image data for one line output from U is converted into an analog image signal to convert the digital image data into an analog image signal.
, 22m-2, 22m-1, 22m,
22m + 1, ....

The lower H driver 13D also has a shift register 25 just like the upper H driver 13U.
D, a sampling latch circuit 26D, a line sequential latch circuit 27D, and a DA conversion circuit 28D. In the liquid crystal display device according to this example, the H drivers 13U and 13D are arranged above and below the display area unit 12, but the present invention is not limited to this. It is also possible to adopt a configuration.

As is apparent from FIGS. 1 and 3, the power supply circuit 15 and the timing control circuit 16 also include H drivers 13U and 13D and a V driver 14.
Similarly, the same glass substrate 1 is used together with the display area 12.
1 are integrated. Here, for example, in the case of a liquid crystal display device adopting a configuration in which H drivers 13U and 13D are arranged above and below the display area section 12, a frame area of a side where the H drivers 13U and 13D are not mounted (the display area section 12). It is preferable to mount the power supply circuit 15 and the timing control circuit 16 in the (peripheral area).

The reason is that the H drivers 13U, 13D
As described above, since the number of components is larger than that of the V driver 14 and the circuit area is often very large as described above, the H driver 13U, 13D is mounted in the frame area on the side where the H driver 13U, 13D is not mounted. This is because the power supply circuit 15 and the timing control circuit 16 can be integrated on the same glass substrate 11 as the display area unit 12 without lowering the effective screen ratio (the area ratio of the effective area unit 12 to the glass substrate 11). is there.

In the liquid crystal display device according to the present embodiment, since the V driver 14 is integrated on one side of the frame area of the side where the H drivers 13U and 13D are not mounted, the opposite side is provided. Power supply circuit 1 in the frame area
5 and the timing control circuit 16 are integrated.

When the power supply circuit 15 is integrated, since the thin film transistor TFT is used as each pixel transistor of the display area section 12, a thin film transistor is also used as a transistor constituting the power supply circuit 15.
At least these transistor circuits are connected to the display area 12
By using the same process as described above, the production can be facilitated and can be realized at low cost.

At present, integration of thin film transistors has become easier with the recent improvement in performance and reduction in power consumption. Therefore, by integrally forming the power supply circuit 15, particularly at least the transistor circuit, on the same glass substrate 11 using the same thin film transistor as the pixel transistor in the display area section 12 in the same process, the manufacturing process is simplified. The cost can be reduced, and the thickness and the size can be reduced with the integration.

The power supply circuit 15 comprises, for example, a charge pump type power supply voltage conversion circuit (DC-DC converter).
A single DC power supply voltage VCC supplied from the outside is converted into a plurality of types of DC voltages having different voltage values, and these DC voltages are supplied to the H drivers 13U and 13D, the V driver 14, and the timing control circuit 16. The power supply circuit 15 according to the present embodiment includes a synchronization signal synchronized with a video signal displayed in the display area unit 12, for example, a horizontal synchronization signal HD.
Is used as a clock signal as a reference for the switching operation.

The timing control circuit 16 generates various timing signals used in the H drivers 13U, 13D and the V driver 14 based on the externally supplied horizontal synchronizing signal HD, vertical synchronizing signal VD and master clock signal MCK. As an example, the H driver 13
A horizontal start pulse HST and a horizontal transfer clock HCK are applied to U and 13D, and a vertical start pulse VST and a vertical transfer clock VCK are applied to the V driver 14.

As described above, in the active matrix type liquid crystal display device, by using a synchronizing signal synchronized with a video signal, for example, a horizontal synchronizing signal HD as a clock signal which is a reference of a switching operation of the power supply circuit 15, the horizontal synchronizing signal HD is used. Since the synchronization signal HD is a signal originally used in the timing control circuit 16, it is not necessary to newly provide a circuit for generating a clock signal, so that the circuit area created on the glass substrate 11 can be reduced. Therefore, the size and thickness of the liquid crystal display device can be reduced.

The horizontal synchronizing signal HD is a signal which is separated from the video signal displayed on the display area 12 by, for example, an external sync separation circuit (not shown), and is naturally synchronized with the video signal. Because it is a signal,
Since no noise is generated due to the asynchronous between the clock signal and the video signal, no problem such as image disturbance due to the noise is generated. Therefore, a liquid crystal display device having excellent image quality can be provided.

In this embodiment, the horizontal synchronizing signal HD is used as the signal synchronized with the video signal. However, the present invention is not limited to this. The vertical synchronizing signal VD, the horizontal synchronizing signal HD or the vertical synchronizing signal VD is used. It is also possible to use a signal or the like obtained by dividing the frequency, and all of them are signals synchronized with the video signal, so that the same operation and effect as described above can be obtained.

As the power supply voltage of the timing control circuit 16, it is not always necessary to use the DC voltage generated by the power supply circuit 15, but a power supply voltage directly input from the outside may be used.

Next, a specific configuration of the power supply circuit 15 will be described. Here, a case in which, for example, a charge pump type power supply voltage conversion circuit is used as the power supply circuit 15 will be described.

FIGS. 4A and 4B are circuit diagrams showing a first configuration example of a charge pump type power supply voltage conversion circuit, wherein FIG. 4A shows a negative voltage generation type and FIG. 4B shows a boost type. The charge pump type power supply voltage conversion circuit according to the present example is supplied with, for example, a horizontal synchronization signal HD as a clock signal. The horizontal synchronization signal HD is supplied to the duty conversion circuit 31. The duty conversion circuit 31 is configured by, for example, a frequency dividing circuit, and outputs a horizontal synchronization signal HD.
Is converted into a clock pulse having a duty ratio of approximately 50% to be a switching pulse.

On the other hand, an externally applied power supply voltage VCC
PchMOS transistor Qp11 and NchMOS transistor Qn11 between power supply and ground (GND).
Are connected in series, and the respective gates are commonly connected to form a CMOS inverter 32. This CMOS
A clock pulse obtained by duty-converting the horizontal synchronizing signal HD from the duty conversion circuit 31 is supplied as a switching pulse to the gate common connection point of the inverter 32.

One end of a capacitor C11 is connected to a common drain connection point (node B) of the CMOS inverter 32. The other end of the capacitor C11 is connected to a switch element, for example, a drain of an NchMOS transistor Qn12 and a source of a PMOS transistor Qp12. A load capacitor C12 is connected between the source of the NchMOS transistor Qn12 and the ground.

One end of a capacitor C13 is connected to the common gate connection point of the CMOS inverter 32. The other end of the capacitor C13 is connected to the anode of the diode D11. The cathode of the diode D11 is grounded to form a first clamp circuit 33. The other end of the capacitor C13 further includes an NchMOS transistor Qn12 and a PchMOS transistor Qp
Twelve gates are connected to each other. PchMOS
The drain of the transistor Qp12 is grounded.

A PchMOS transistor Qp13 is connected between the other end of the capacitor C13 and the ground. A clamp pulse generated by a pulse generation circuit 34 is level-shifted by a level shift circuit 35 and applied to the gate of the PchMOS transistor Qp13. The PchMOS transistor Qp13, the pulse generation circuit 34, and the level shift circuit 35 constitute a second clamp circuit 36 that clamps a switching pulse voltage of a switching transistor (NchMOS transistor Qn12 and PchMOS transistor Qp12).

In the second clamp circuit 36, the pulse generating circuit 34 generates a clamp pulse based on the horizontal synchronizing signal HD and a clock pulse obtained by duty-converting the horizontal synchronizing signal HD by the duty conversion circuit 31. The level shift circuit 35 uses the power supply voltage VCC as the positive side circuit power supply, the output voltage Vout of the present circuit derived from both ends of the load capacitor C12 as the negative side circuit power supply, and the amplitude VCC-0 [ V], the level of the clamp pulse is shifted to a clamp pulse having an amplitude of VCC−Vout [V], and the PchMOS transistor Qp1 is shifted.
Give to gate 3.

Next, the circuit operation of the negative voltage generation type charge pump type power supply voltage conversion circuit having the above configuration will be described with reference to the timing chart of FIG. Note that the timing chart of FIG.
Signal waveforms A to G at nodes A to G in the circuit of FIG.
Is shown.

At power-on (start-up), the output potential of the capacitor C13 based on the clock pulse (switching pulse) obtained by duty-converting the horizontal synchronizing signal HD by the duty conversion circuit 31, that is, the potential of the node D is:
First, by the diode D11, the potential is shifted from the ground (GND) level, which is the circuit power supply potential on the negative side, by the threshold voltage Vth of the diode D11.
H "level clamped.

When the switching pulse is at the "L" level (0 V), the P-channel MOS transistor Qp1
1 and Qp12 are turned on, so that the capacitor C11
Is charged. At this time, the NchMOS transistor Qn
Since 11 is in the off state, the potential of the node B becomes the VCC level. Next, when the switching pulse becomes “H” level (VCC), the NchMOS transistor Qn1
1 and Qn12 are turned on, and the potential of the node B becomes the ground level (0 V).
It becomes CC level. The potential of this node C remains unchanged for Nch
Output voltage Vout through MOS transistor Qn12
(= −VCC).

Next, when the output voltage Vout rises to some extent (at the end of the start-up process), the level shift circuit 35 for the clamp pulse starts operating. When the level shift circuit 35 starts operating, the clamping pulse having the amplitude VCC-0 [V] generated by the pulse generation circuit 34 is applied to the level shift circuit 35 by the amplitude VCC-Vou.
The level is shifted to a clamping pulse of t [V], and then applied to the gate of the PchMOS transistor Qp13.

At this time, since the "L" level of the clamping pulse is the output voltage Vout, that is, -VCC, the Pch
MOS transistor Qp13 is reliably turned on.
As a result, the potential of the node D is clamped to the ground level (negative circuit power supply potential) instead of the potential level shifted from the ground level by the threshold voltage Vth of the diode D11. Thereby, in the subsequent pumping operation, in particular, the PchMOS transistor Qp12
, A sufficient driving voltage can be obtained.

As described above, in the power supply voltage conversion circuit using the charge pump, the switching elements (NchMOS transistors Qn12 and Pn12)
The voltage of the control pulse (switching pulse) for the chMOS transistor Qp12) is first clamped by the diode D11 of the first clamp circuit 33 when the circuit is started, and the second clamp circuit 3 after the start process is completed.
6, the clamping is performed in two stages, such as the PchMOS transistor Qp1.
2, a sufficient driving voltage can be obtained.

Thus, the PchMOS transistor Qp
12, a sufficient switching current can be obtained, so that a stable DC-DC conversion operation can be performed and the conversion efficiency can be improved. In particular, since a sufficient switching current can be obtained without increasing the transistor size of the PchMOS transistor Qp12, a power supply voltage conversion circuit having a large current capacity and a small circuit scale can be realized.

The effect is particularly large when a transistor having a large threshold value Vth, for example, a thin film transistor is used. By using this configuration example, integration of the power supply voltage conversion circuit on the glass substrate 11 becomes easy, and as a result, it is possible to contribute to downsizing of the display device.

When the horizontal synchronizing signal HD is used as a reference signal of the switching pulse, a duty conversion circuit 31 is provided at the input stage, and the duty conversion circuit 31 makes the duty ratio of the switching pulse close to 50%. By doing so, it is possible to perform a DC-DC conversion operation more efficiently than when the horizontal synchronization signal HD is used as a switching pulse as it is.

The booster DD converter shown in FIG. 4B has the same basic circuit configuration and circuit operation.

That is, in FIG. 4B, the switching transistor and the clamping transistor (M
OS transistors Qp14, Qn14, Qn13)
The MOS transistors Qn12 and Qp in the circuit of FIG.
12, Qp13, the diode D11 is connected between the other end of the capacitor C11 and the power supply (VCC), and the level shift circuit 35 uses the output voltage Vout of this circuit as the positive circuit power supply, In this configuration, the ground level is used as the negative circuit power supply.
The only difference from the circuit of FIG.

In terms of circuit operation, basically, FIG.
This is exactly the same as the circuit of FIG. The difference is that the switching pulse voltage (control pulse voltage) is first diode-clamped at startup, clamped to the VCC level (positive circuit power supply potential) at the end of the startup process, and output voltage Vout is twice the power supply voltage VCC. Voltage value 2 × V
Only the point from which the CC is derived. FIG.
Signal waveforms A to G at nodes A to G in the circuit of FIG.
3 shows a timing chart.

Although the horizontal synchronizing signal HD is used as a reference signal of the switching pulse in this configuration example, the vertical synchronizing signal VD can be used. Here, the horizontal synchronizing signal HD and the vertical synchronizing signal VD have significantly different frequencies, but the frequency difference can be dealt with by changing the capacitance values of the capacitors C11 and C13.

It is also possible to use the vertical transfer clock VCK generated by the timing control circuit 16 as a clock signal serving as a reference for the switching operation. The vertical transfer clock VCK is a clock signal generated based on the horizontal synchronization signal HD and is a signal synchronized with the video signal. Therefore, the same operation and effect as when the horizontal synchronization signal HD and the vertical synchronization signal VD are used. Since the vertical transfer clock VCK is originally a clock signal having a duty ratio of 50%, there is no need to provide the duty conversion circuit 31, so that there is an advantage that the circuit area can be reduced accordingly.

FIGS. 6A and 6B are circuit diagrams showing a second configuration example of the charge pump type power supply voltage conversion circuit. FIG. 6A shows a negative voltage generation type, and FIG. 6B shows a step-up type. In the drawing, the same parts as those in FIG. 4 are denoted by the same reference numerals.

The power supply voltage conversion circuit according to this configuration example is mounted on a liquid crystal display device having a configuration that selectively employs a power saving mode in order to reduce the power consumption of the entire device.
For example, a horizontal synchronization signal HD is used as a reference clock signal for the switching operation. However, as in the case of the first configuration example, it is also possible to use the vertical synchronization signal VD, the vertical transfer clock VCK, or the like as the reference clock for the switching operation.

In FIG. 6, a two-input AND circuit 37 is newly added at the subsequent stage of the duty conversion circuit 31, and the rest is exactly the same as the configuration of FIG. The two-input AND circuit 37 receives the clock pulse obtained by duty-converting the horizontal synchronizing signal HD by the duty conversion circuit 31 as one input, and outputs the "L" level mode selection signal SEL supplied in the power saving mode to the other. Input.

In the power supply voltage conversion circuit according to the second configuration example of the above configuration, when the mode selection signal SEL of the “L” level is supplied in the power saving mode, the AND circuit 37 performs the clock pulse based on the horizontal synchronization signal HD. Supply to the circuit is stopped. As a result, the switching operation (pumping operation of the charge pump) in the present power supply voltage conversion circuit is temporarily stopped, so that current consumption in the present circuit is reduced and power saving is achieved. Note that the horizontal synchronization signal HD
The same can be said for a configuration in which the duty ratio is not converted and a direct input is performed (a configuration in which the duty conversion circuit 31 is omitted).

As described above, even when the clock supply is temporarily stopped due to the setting of the power saving mode, as described above, the switch element (NchM
Since the voltage of the control pulse (switching pulse) for the OS transistor Qn12 and the PchMOS transistor Qp12) is clamped in two stages at the time of startup and after the startup process, the clamp level of the node D becomes stable. Sufficient current capability can be secured even during the transition period of
-DC conversion operation is enabled.

FIGS. 7A and 7B are circuit diagrams showing a third configuration example of the charge pump type power supply voltage conversion circuit. FIG. 7A shows a negative voltage generation type, and FIG. 7B shows a boost type. In the drawing, the same parts as those in FIG. 4 are denoted by the same reference numerals. The power supply voltage conversion circuit according to this configuration example employs a configuration in which a horizontal synchronization signal HD (or a vertical synchronization signal VD) and a vertical transfer clock VCK are used together as a reference clock signal for the switching operation.

In FIG. 7, the duty conversion circuit 3 is provided at the input stage of the horizontal synchronizing signal HD / vertical transfer clock VCK.
The configuration is such that a changeover switch 38 is provided in place of 1, and the rest is exactly the same as the configuration in FIG. The changeover switch 38 has two inputs of the horizontal synchronization signal HD and the vertical transfer clock VCK, and selects the input based on a standby signal given during a standby period. Here, the stand-by period means that other circuits, that is, the H drivers 13U and 13U shown in FIG.
This is a period until the D and V drivers 14 and the timing control circuit 16 start operating.

In the power supply voltage conversion circuit according to the third configuration example of the above configuration, during the standby period, the changeover switch 38 selects the horizontal synchronizing signal HD in response to the standby signal. During this standby period, the H drivers 13U and 13D, the V driver 14, and the timing control circuit 16 are controlled by the standby signal so that current is not consumed as much as possible. This allows
Low power consumption is being achieved.

On the other hand, the power supply circuit 15, that is, the power supply voltage conversion circuit, uses the switch 38 to switch the horizontal synchronizing signal H
When D is selected, a switching operation is performed using the horizontal synchronization signal HD as an operation clock, and a DC voltage of a predetermined voltage value (in this example, −VCC and 2VCC, but this is only an example) is generated. I do. These DC voltages are H
The power is supplied to the drivers 13U and 13D, the V driver 14, and the timing control circuit 16 as a power supply voltage.

As a result, the timing control circuit 16 generates the vertical transfer clock VCK based on the horizontal synchronization signal HD. This vertical transfer clock VCK
Is selected instead of the horizontal synchronizing signal HD by the changeover switch 38 after a fixed period of time has elapsed since the power was turned on, that is, after the standby period has ended. Then, the power supply voltage conversion circuit performs the switching operation using the vertical transfer clock VCK as the operation clock, and continues the DC-DC conversion operation.

As described above, when the power is turned on, the switching operation is performed using the horizontal synchronization signal HD as the operation clock, and after the standby period ends, the vertical transfer clock V
Since the switching operation is performed using CK as an operation clock, an efficient DC-DC conversion operation based on the vertical transfer clock VCK having a duty ratio of 50% is possible even when the standby period ends and current consumption increases. Therefore, it is possible to have a sufficient current capability.

The circuit configuration of the power supply voltage conversion circuit of the charge pump type according to the first to third configuration examples described above is only an example, and the circuit configuration of the charge pump circuit can be variously modified. The present invention is not limited to the circuit configuration example.

In the above embodiment, the case where the present invention is applied to an active matrix type liquid crystal display device has been described as an example. However, the present invention is not limited to this, and the electroluminescent (EL) element may be replaced with the electro-optical element of each pixel. The present invention can be similarly applied to other active matrix display devices such as an EL display device used as a display device.

Further, the active matrix type display device according to the present invention is not only used as a display for OA equipment such as a personal computer and a word processor, but also for a display such as a television receiver. It is suitable for use as a display unit of a portable terminal such as a mobile phone or a PDA.

FIG. 8 is an external view schematically showing the configuration of a portable terminal to which the present invention is applied, for example, a portable telephone.

The mobile phone according to this embodiment has a configuration in which a speaker section 42, a display section 43, an operation section 44, and a microphone section 45 are arranged in this order from the upper side on the front side of an apparatus housing 41. In the mobile phone having such a configuration, the display unit 4
For example, a liquid crystal display device 3 is used as the liquid crystal display device 3, and the active matrix liquid crystal display device according to the above-described embodiment is used as the liquid crystal display device.

As described above, in a portable terminal such as a portable telephone, by using the active matrix type liquid crystal display device according to the above-described embodiment as the display unit 43,
Since the liquid crystal display device can reduce the size of the entire device and reduce noise, the size of the terminal body can be reduced and the image quality can be improved. In particular, current consumption in the circuit can be reduced in the power saving mode. Power consumption is also possible.

[0071]

As described above, according to the present invention,
In an active matrix type display device or a mobile terminal using the same, a signal for synchronizing with a video signal is used as a clock signal as a reference for operation of a power supply circuit, so that a circuit for generating a clock signal becomes unnecessary.
In addition, since no noise is generated due to the asynchronousness of the clock signal and the video signal, downsizing and low noise can be achieved, and power consumption can be reduced by supporting a power saving mode.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a display area of a liquid crystal display device.

FIG. 3 is a block diagram illustrating an example of a specific configuration of an H driver.

FIG. 4 is a circuit diagram showing a first configuration example of a charge pump type power supply voltage conversion circuit, where (A) shows a negative voltage generation type;
(B) shows the boost type.

5A and 5B are timing charts for explaining a circuit operation of a charge pump type power supply voltage conversion circuit, wherein FIG. 5A shows a case of a negative voltage generation type, and FIG. 5B shows a case of a boost type.

FIG. 6 is a circuit diagram showing a second configuration example of the charge pump type power supply voltage conversion circuit, where (A) shows a negative voltage generation type;
(B) shows the boost type.

FIG. 7 is a circuit diagram showing a third configuration example of the charge pump type power supply voltage conversion circuit, where (A) shows a negative voltage generation type;
(B) shows the boost type.

FIG. 8 is an external view schematically showing a configuration of a mobile phone which is a mobile terminal according to the present invention.

FIG. 9 is a block diagram showing a display device according to Conventional Example 1.

FIG. 10 is a block diagram showing a display device according to Conventional Example 2.

[Explanation of symbols]

11: glass substrate, 12: display area, 13U, 13
D: H driver (horizontal drive circuit), 14: V driver (vertical drive circuit), 15: power supply circuit, 16: timing control circuit, 23: unit pixel, 31: duty conversion circuit, 32: CMOS inverter, 33 ... 1 clamp circuit, 34 pulse generation circuit, 35 level shift circuit, 36 second clamp circuit, 37 AND circuit, 38 switch

 ──────────────────────────────────────────────────続 き Continued on the front page F term (reference) 2H093 NA16 NC01 NC09 NC11 ND39 ND42 5C006 BB16 BC20 BF45 BF46 FA31 FA41 FA47 GA02 5C080 AA06 AA10 BB05 DD12 DD22 DD26 FF11 JJ02 JJ03 JJ04 JJ06 KK07 KK47

Claims (16)

[Claims] 1. A display area in which pixels having an electro-optical element are arranged in a matrix, a vertical drive circuit for selecting each pixel of the display area in a row unit, and a vertical drive circuit selected by the vertical drive circuit. A horizontal drive circuit that supplies an image signal to each pixel in a row, and operates based on a synchronization signal synchronized with a video signal to be displayed in the display area, and converts a single DC voltage to a plurality of types having different voltage values. An active matrix display device, comprising: a power supply circuit that converts the voltage into a DC voltage and supplies it to at least the vertical drive circuit and the horizontal drive circuit. 2. The active matrix display device according to claim 1, wherein the power supply circuit is a charge pump type power supply voltage conversion circuit that performs a switching operation based on the synchronization signal. 3. The active matrix display device according to claim 2, wherein the power supply voltage conversion circuit has a unit for temporarily stopping a switching operation based on the synchronization signal. 4. The active matrix display device according to claim 1, wherein the synchronization signal is a horizontal synchronization signal, a vertical synchronization signal, or a clock signal serving as a reference for operation of the vertical drive circuit. 5. The power supply voltage conversion circuit according to claim 4, further comprising a duty conversion circuit for converting a duty ratio of the horizontal synchronization signal or the vertical synchronization signal.
The active matrix type display device according to the above. 6. The active matrix display device according to claim 5, wherein a duty ratio of said horizontal synchronizing signal or said vertical synchronizing signal after duty conversion by said duty conversion circuit is approximately 50%. 7. The power supply circuit operates based on a horizontal synchronizing signal or a vertical synchronizing signal immediately after power-on, and operates based on a clock signal serving as a reference for operation of the vertical driving circuit after a lapse of a predetermined period. 4. The method according to claim 4, wherein
The active matrix type display device according to the above. 8. The active matrix type display device according to claim 1, wherein said electro-optical element is a liquid crystal cell. 9. The active matrix display device according to claim 1, wherein said electro-optical element is an electroluminescence element. 10. In each pixel of the display area,
2. The active element for driving the electro-optical element comprises a thin film transistor, and at least the transistor circuit constituting the power supply circuit is formed integrally with the display area unit on the same substrate by the thin film transistor. The active matrix type display device according to the above. 11. A display area as a display section, in which pixels having electro-optical elements are arranged in a matrix, a vertical drive circuit for selecting each pixel of the display area on a row-by-row basis, and the vertical drive circuit. A horizontal drive circuit that supplies an image signal to each pixel of the row selected by the pixel, operates based on a synchronization signal synchronized with a video signal displayed in the display area unit, and outputs a single DC voltage as a voltage value. A mobile terminal using an active matrix display device including at least a power supply circuit that converts the voltage into a plurality of different types of DC voltages and applies the converted voltage to at least the vertical drive circuit and the horizontal drive circuit. 12. The portable terminal according to claim 11, wherein the power supply circuit is a charge pump type power supply voltage conversion circuit that performs a switching operation based on the synchronization signal. 13. The mobile terminal according to claim 11, wherein the synchronization signal is a horizontal synchronization signal, a vertical synchronization signal, or a clock signal serving as a reference for the operation of the vertical driving circuit. 14. The power supply circuit operates based on a horizontal synchronizing signal or a vertical synchronizing signal immediately after power-on, and operates based on a clock signal serving as a reference for operation of the vertical driving circuit after a certain period of time. The mobile terminal according to claim 13, wherein: 15. The portable terminal according to claim 11, wherein the active matrix display device is a liquid crystal display device using a liquid crystal cell as the electro-optical element. 16. The mobile terminal according to claim 11, wherein the active matrix display device is an electroluminescent display device using an electroluminescent element as the electro-optical element.