JP2002175035A - Timing generating circuit for display device, active matrix type display device, and portable terminal - Google Patents

Abstract

PROBLEM TO BE SOLVED: To solve the problem of impediment to miniaturizing a set and cost reduction for constructing a timing generating circuit on a substrate separate from a substrate, on which a display area part is formed. SOLUTION: The timing generating circuit 15 is formed on the same glass substrate integral with the display area part 12 as well as an H-driver 13U and a V-driver 14, and also based on the timing data generated by a shift register 25U of the H-driver 13U and a shift register 29 of the V-driver 14, timing pulses used for the H-driver 13U and V-driver 14 are generated.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a timing generation circuit for a display device, an active matrix type display device and a portable terminal, and more particularly to a timing for generating various timing pulses for controlling a drive system of the active matrix type display device. The present invention relates to a generation circuit, an active matrix display device equipped with the timing generation circuit, and a mobile terminal using the display device as a display unit.

[0002]

2. Description of the Related Art In recent years, portable telephones and PDAs (Personal Digital
gital Assistants) and other mobile terminals have become remarkably popular. One of the factors behind the rapid spread of these mobile devices is that
There is a liquid crystal display device mounted as the output display unit. The reason is that the liquid crystal display device has a characteristic that does not require power for driving in principle, and is a display device with low power consumption.

[0003] In a display device such as this liquid crystal display device in which pixels are arranged in a matrix and each of these pixels is driven, a vertical drive system for selecting each pixel in a row unit and a vertical drive system for selecting each pixel in a row are used. And a horizontal drive system for writing information to each pixel of the selected row. In these drive systems, various timing pulses are used for drive control.

[0004] These timing pulses are generated at appropriate timings in a timing generation circuit using a dedicated timing signal generation counter circuit or the like based on the horizontal synchronization signal HD, the vertical synchronization signal VD, and the master clock signal MCK. You. Conventionally, a timing generating circuit for generating these timing pulses is formed on a single crystal silicon substrate which is a separate substrate from the substrate on which the display area is formed.

[0005]

As described above, in a display device typified by a liquid crystal display device, a timing generation circuit for generating various timing signals for display driving is provided on a substrate on which a display area is formed. If they are formed on a different substrate, the number of components that make up the set increases, and they must be created in separate processes, which hinders downsizing and cost reduction of the set. Was.

The present invention has been made in view of the above problems, and has as its object to provide a timing generating circuit for a display device which can contribute to downsizing and cost reduction of a set.
An object of the present invention is to provide an active matrix type display device equipped with the timing generation circuit and a portable terminal using the display device as a display unit.

[0007]

In order to achieve the above object, according to the present invention, there is provided a display area in which pixels having electro-optical elements are arranged in a matrix, and each pixel in the display area is divided into rows. In the active matrix type display device having a vertical drive circuit selected in step (a) and a horizontal drive circuit for supplying an image signal to each pixel in a row selected by the vertical drive circuit, the timing generation circuit includes a vertical drive circuit. And a timing signal used for at least one of these drive circuits based on timing information generated for at least one of the horizontal drive circuit. An active matrix display device equipped with this timing generation circuit is used as a display unit of a portable terminal.

In the timing generating circuit having the above configuration, an active matrix type display device having the same or a portable terminal using the same, a timing signal is generated based on timing information generated by at least one of a vertical driving circuit and a horizontal driving circuit. The generation means that a part of at least one of the vertical drive circuit and the horizontal drive circuit is also used for generating the timing signal. Therefore, the circuit configuration of the timing generation circuit can be simplified by the amount of the circuit that also serves as the circuit.

[0009]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a schematic configuration diagram illustrating a configuration example of a display device according to the present invention. Here, for example, a case where the present invention is applied to an active matrix type liquid crystal display device using a liquid crystal cell as an electro-optical element of each pixel will be described.

In FIG. 1, on a transparent insulating substrate, for example, a glass substrate 11, a display area section 12 in which a large number of pixels including liquid crystal cells are arranged in a matrix, and a pair of upper and lower H
The driver (horizontal drive circuit) 13U, 13D and the V driver (vertical drive circuit) 14 together with the H driver 13
A timing generation circuit 15 for generating various timing pulses for driving the U, 13D and V drivers 14 is integrated. The glass substrate 11 has an active element (for example,
Transistors) are composed of a first substrate on which a large number of pixel circuits including transistors are arranged in a matrix, and a second substrate disposed opposite to the first substrate with a predetermined gap. Then, a liquid crystal is sealed between the first and second substrates.

FIG. 2 shows an example of a specific configuration of the display area section 12. Here, for simplification of the drawing, a case of a pixel array of three rows (n-1 to n + 1 rows) and four columns (m-2 to m + 1 columns) is shown as an example. In FIG. 2, the display area section 12 includes vertical scanning lines.
-1, 21n, 21n + 1,..., Data lines.
, 2m-2, 22m-1, 22m, 22m + 1,... Are arranged in a matrix, and a unit pixel 2
3 are arranged.

The unit pixel 23 has a configuration including a thin film transistor TFT as a pixel transistor, a liquid crystal cell LC, and a storage capacitor Cs. Here, the liquid crystal cell LC
Means a capacitance generated between a pixel electrode (one electrode) formed by the thin film transistor TFT and a counter electrode (the other electrode) formed opposite thereto.

In the thin film transistor TFT, the gate electrodes have vertical scanning lines..., 21n-1, 21, n, 21n + 1,
, And the source electrode is connected to the data line.
2, 22m-1, 22m, 22m + 1,... In the liquid crystal cell LC, the pixel electrode is a thin film transistor T
The FT is connected to the drain electrode, and the counter electrode is connected to the common line 24. The storage capacitor Cs is connected between the drain electrode of the thin film transistor TFT and the common line 24. A predetermined DC voltage is supplied to the common line 24 as a common voltage Vcom.

Vertical scanning lines..., 21n-1, 21n,
21n + 1 are connected to the V driver 14 shown in FIG.
Is connected to each output terminal of the corresponding row. The V driver 14 is constituted by, for example, a shift register.
A vertical selection pulse is sequentially generated in synchronization with a vertical transfer clock VCK (not shown) to generate vertical scanning lines.
, 21n, 21n + 1,... To perform vertical scanning.

On the other hand, in the display area section 12, for example, odd-numbered data lines..., 22m-1, 22m +
, 22m are connected to the respective output ends of the corresponding columns of the H driver 13U shown in FIG.
The other end of −2, 22 m,... Is the H driver 13 shown in FIG.
D is connected to each output terminal of the corresponding column. FIG. 3 shows an example of a specific configuration of the H drivers 13U and 13D.

As shown in FIG. 3, the H driver 13U includes:
The configuration includes a shift register 25U, a sampling latch circuit (data signal input circuit) 26U, a line sequential latch circuit 27U, and a DA conversion circuit 28U. The shift register 25U performs horizontal scanning by sequentially outputting a shift pulse from each transfer stage in synchronization with a horizontal transfer clock HCK (not shown). The sampling latch circuit 26U responds to a shift pulse given from the shift register 25U, and samples and latches input digital image data of predetermined bits in a dot-sequential manner.

The line-sequentializing latch circuit 27U re-latches the digital image data latched in the dot-sequential manner by the sampling latch circuit 26U line by line, thereby line-sequentially converting the digital image data for one line. Output to The DA conversion circuit 28U has, for example, a circuit configuration of a reference voltage selection type, and has a line-sequentialization latch circuit 27.
The digital image data for one line output from the U is converted into an analog image signal, and the pixel area 12 described above is converted.
, 22m-2, 22m-1, 22m,
22m + 1, ....

The lower H driver 13D also has a shift register 25 just like the upper H driver 13U.
D, a sampling latch circuit 26D, a line sequential latch circuit 27D, and a DA conversion circuit 28D. In the liquid crystal display device according to the present example, the H drivers 13U and 13D are arranged above and below the display area 12, but the present invention is not limited to this. It is also possible to adopt a configuration.

As is clear from FIGS. 1 and 3, the timing generation circuit 15 also has the H drivers 13U, 1
Similar to the 3D and V driver 14, the display area 12
And are integrated on the same glass substrate 11. here,
For example, H drivers 13U, 1 above and below the display area 12
In the case of a liquid crystal display device having a configuration in which 3D is provided, it is preferable to mount the timing generation circuit 15 in a frame area on the side where the H drivers 13U and 13D are not mounted (peripheral area of the display area section 12).

The reason is that the H drivers 13U, 13D
As described above, since the number of components is larger than that of the V driver 14 and the circuit area is often very large as described above, the H driver 13U or 13D is mounted in a frame area on the side where the H driver 13U or 13D is not mounted. Without reducing the effective screen ratio (the ratio of the effective area 12 to the glass substrate 11), the timing generation circuit 15
This is because they can be integrated on the same glass substrate 11.

In the liquid crystal display device according to the present embodiment, the V driver 14 is integrated on one side of the frame area on the side where the H drivers 13U and 13D are not mounted. The timing generation circuit 15 is integrated in the frame area.

When the timing generation circuit 15 is integrated, a thin film transistor TFT is used as each pixel transistor of the display area section 12. Therefore, a thin film transistor is also used as a transistor constituting the timing generation circuit 15, and at least these transistor circuits are used. Is manufactured using the same process as that of the display area section 12, the manufacture thereof becomes easy, and it can be realized at low cost.

At present, integration of thin film transistors has been facilitated with the recent improvement in performance and reduction in power consumption. Therefore, the timing generation circuit 1
5, in particular, at least a transistor circuit
By using the same thin film transistor as the two pixel transistors and integrally forming them on the same glass substrate 11 by the same process, the cost can be reduced due to the simplification of the manufacturing process, and further, the thickness can be reduced due to the integration, and the compactness can be achieved. Can be achieved.

Here, the case where the present invention is applied to an active matrix type liquid crystal display device has been described as an example.
The present invention is not limited to this, and can be similarly applied to other active matrix display devices such as an EL display device using an electroluminescence (EL) element as an electro-optical element of each pixel.

FIG. 4 is a block diagram showing an example of the configuration of an active matrix type display device having a timing generation circuit 15 according to an embodiment of the present invention. Here, for simplification of the drawing, only the upper H driver 13U is shown, but the relationship with the lower H driver 13D is the same as that of the upper H driver 13U.

The timing generation circuit 15 receives a horizontal synchronization signal HD, a vertical synchronization signal VD, and a master clock MCK supplied from the outside, and based on these, first, a horizontal start pulse HST supplied to the shift register 25U of the H driver 13U. And horizontal transfer pulse HC
K, and a vertical start pulse VST and a vertical transfer pulse VC applied to the shift register 29 of the V driver 14.
Generate K.

Here, the horizontal start pulse HST is a pulse signal generated after a lapse of a predetermined time after the generation of the horizontal synchronizing signal HD, and the horizontal transfer pulse HCK is a pulse signal obtained by dividing the master clock MCK, for example. . The vertical start pulse VST is a pulse signal generated after a predetermined time has elapsed after the generation of the vertical synchronization signal VD, and the vertical transfer pulse VCK is a horizontal transfer pulse HC.
This is a pulse signal obtained by dividing K, for example.

Therefore, in the timing generation circuit 15, the horizontal start pulse HST, the horizontal transfer pulse HCK, the vertical start pulse VCK, and the horizontal synchronizing signal HD, the vertical synchronizing signal VD, and the master clock MCK are used as references.
A circuit for generating the ST and the vertical transfer pulse VCK can be realized by a simple counter circuit having several stages.

The timing generation circuit 15 further outputs timing data obtained from an appropriate transfer stage of the shift register 25U of the H driver 13U and timing data (timing information) obtained from an appropriate transfer stage of the shift register 29 of the V driver 14. Also, a timing pulse used by the H driver 13U and a timing pulse used by the V driver 14 are generated based on these timing data.

The timing pulse used in the H driver 13U is, for example, a latch control pulse used in the line sequential latch circuit 27U shown in FIG. However, it is not limited to this. On the other hand, the timing pulse used in the V driver 14 is, for example, a display period control pulse for specifying the display period in the partial display mode in which display is performed only during a certain period in the vertical direction of the display area unit 12. . However, it is not limited to this.

FIG. 5 is a block diagram showing a specific configuration example of the timing generation circuit 15. As shown in FIG. Here, the timing generation circuit 15 is the shift register 2 of the H driver 13U.
A case where a latch control pulse used in the line sequential latch circuit 27U is generated based on timing data given from 5U will be described as an example.

In FIG. 5, first, a shift register 25U of the H driver 13U is provided with an M-stage D-type flip-flop (hereinafter, referred to as N-number of horizontal pixels in the display area section 12).
DFF) 31-1 to 31-M. When the horizontal start pulse HST is supplied, the shift register 25U having such a configuration transfers the horizontal transfer pulse HC.
The shift operation is performed in synchronization with K. As a result, the DFF 31
−1 to 31-M, the horizontal transfer pulse H
Pulses (timing information) are sequentially output in synchronization with CK.

Each of the Q output pulses of the DFFs 31-1 to 31-M is sequentially supplied to the sampling latch circuit 26U as a sampling pulse. DFF31-
Q output pulses of an appropriate transfer stage among the Q output pulses of 1 to 31-M, here, as an example, the first stage DFF3
1-1, the Q output pulse A and the M-1 stage DFF 31-
The Q output pulse B of M−1 is supplied to the timing generation circuit 15.

In the timing generation circuit 15, a latch control pulse generation circuit 32 for generating a latch control pulse has, for example, a configuration including a DFF 33 and a buffer. The DFF 33 includes a shift register 25
A clock (CK) is input to the Q output pulse A of the first stage DFF 31-1 supplied from U, and the M-1 stage DFF 31
The -M-1 Q output pulse B is used as a clear (CLR) input, and its own inverted Q output is used as a data (D) input.

As a result, as is apparent from the timing chart of FIG. 6, the "H" level is maintained during the period from the rising timing of the Q output pulse A of the DFF 31-1 to the rising timing of the Q output pulse B of the DFF 31-M-1. (High level) pulse is the DFF 33
As a latch control pulse C via the buffer 34 from the Q output terminal of

As described above, in the timing generator 15 for the display device, the H drivers 13U, 13D and V
For generating the timing pulse used in the driver 14, the shift registers 25U and 25D of the H drivers 13U and 13D are used.
And the shift register 29 of the V driver 14 are used, and the timing pulse is generated based on the timing data obtained from these shift registers. This eliminates the need for a dedicated circuit such as a counter circuit and simplifies the circuit configuration. Therefore, the set can be reduced in size, cost and power consumption can be reduced.

In particular, when the timing generation circuit 15 is integrally formed on the same glass substrate 11 together with the display area section 12 similarly to the H drivers 13U, 13D and the V driver 14, the circuit of the timing generation circuit 15 Since the configuration is extremely simple and the power consumption is low, the frame of the display can be narrowed, the cost can be reduced, and the power consumption can be reduced.

In the above embodiment, the horizontal synchronizing signal H
D, a horizontal start pulse HST and a horizontal transfer pulse HC based on the vertical synchronization signal VD and the master clock MCK.
K, vertical start pulse VST and vertical transfer pulse V
Although the circuit portion for generating CK is also integrally formed on the glass substrate 11, this circuit portion may be formed on a substrate different from the glass substrate 11. This is because, as described above, since the above circuit portion can be realized by a simple counter circuit, even if it is formed on another substrate, the configuration of the peripheral circuit is not so complicated.

In the above embodiment, the H driver 13
Although the description has been made on the assumption that the U, 13D and V drivers 14 have a configuration using a shift register, the present invention is not limited to the case where a shift register is used.
If the U, 13D or V driver 14 performs address control and performs a count operation for generating timing data, it can be similarly applied to a configuration using a different type of counter circuit. It is.

FIG. 7 is a block diagram showing an example of the configuration of an active matrix type display device according to another embodiment of the present invention provided with a timing generation circuit 15. In FIG. Are attached. even here,
For simplification of the drawing, only the upper H driver 13U is shown, but the relationship with the lower H driver 13D is the same as that of the upper H driver 13U.

The active matrix type display device according to the present embodiment includes a power supply circuit 16 in addition to the timing generation circuit 15, and this power supply circuit 16 is the same as the timing generation circuit 15 together with the display area section 12. It has a configuration integrally formed on a glass substrate 11.

The power supply circuit 16 is composed of, for example, a charge pump type power supply voltage conversion circuit (DC-DC converter), and converts a single externally supplied DC power supply voltage VCC into a plurality of types of DC voltages having different voltage values. These DC voltages are supplied to H drivers 13U and 13D, V driver 14, and the like. In the present embodiment, the timing generation circuit 15 is configured to also generate a timing pulse used in the power supply circuit 16.

The specific configuration of the power supply circuit 16 will be described. Here, a case where a charge pump type power supply voltage conversion circuit is used as the power supply circuit 16 will be described as an example.

FIGS. 8A and 8B are circuit diagrams showing a configuration example of a charge pump type power supply voltage conversion circuit. FIG. 8A shows a negative voltage generation type, and FIG. 8B shows a step-up type.
A clock pulse for performing a switching operation and a clamping pulse for performing a clamping operation are supplied as timing pulses to the charge pump type power supply voltage conversion circuit from the timing generation circuit 15.

In FIG. 8, a single DC power supply voltage VCC
PchM between the power supply and ground (GND)
OS transistor Qp11 and NchMOS transistor Q
n11 are connected in series, and each gate is connected in common to form a CMOS inverter 36. This C
A timing pulse supplied from the timing generation circuit 15 is applied as a switching pulse to a gate common connection point of the MOS inverter 36.

One end of a capacitor C11 is connected to a common drain connection point (node B) of the CMOS inverter 36. The other end of the capacitor C11 has an NchMOS
The drain of the transistor Qn12 and the source of the PMOS transistor Qp12 are respectively connected. N
A load capacitor C12 is connected between the source of the chMOS transistor Qn12 and the ground.

One end of the capacitor C13 is connected to a common connection point of the gates of the CMOS inverter 36. The other end of the capacitor C13 is connected to the anode of the diode D11. The other end of the capacitor C13 further includes an NchMOS transistor Qn12 and a PchMOS
Each gate of the transistor Qp12 is connected to each other. The drain of PchMOS transistor Qp12 is grounded.

A PchMOS transistor Qp13 is connected between the other end of the capacitor C13 and the ground. A timing pulse supplied from the timing generation circuit 15, that is, a clamping pulse is supplied to the gate of the PchMOS transistor Qp13 by the level shift circuit 37.
Is given by a level shift. The PchMOS transistor Qp13 and the level shift circuit 37 include a switching transistor (NchMOS transistor Qn).
12 and a clamping circuit for clamping the switching pulse voltage of the PchMOS transistor Qp12).

In this clamp circuit, the level shift circuit 37 converts the power supply voltage VCC input to the present power supply voltage conversion circuit into a positive circuit power supply and the output voltage Vout of this circuit derived from both ends of the load capacitor C12 into a negative side. The amplitude VC supplied from the timing generation circuit 15 as a circuit power supply
The clamp pulse of C-0 [V] is applied to the amplitude VCC-Vo.
ut [V] to Pch
This is applied to the gate of MOS transistor Qp13. Thereby, the switching operation of the PchMOS transistor Qp13 is performed more reliably.

Next, the circuit operation of the negative voltage generation type charge pump type power supply voltage conversion circuit having the above configuration will be described with reference to the timing chart of FIG. Note that the timing chart of FIG.
Signal waveforms A to G at nodes A to G in the circuit of FIG.
Is shown.

At power-on (at startup), the output potential of the capacitor C13 based on the switching pulse supplied from the timing generation circuit 15, that is, the potential of the node D is:
First, the diode D11 clamps the “H” level to a potential shifted from the ground (GND) level, which is the negative circuit power supply potential, by the threshold voltage Vth of the diode D11.

When the switching pulse is at the "L" level (0 V), the P-channel MOS transistor Qp1
1 and Qp12 are turned on, so that the capacitor C11
Is charged. At this time, the Nch MOS transistor Qn
Since 11 is in the off state, the potential of the node B becomes the VCC level. Next, when the switching pulse becomes “H” level (VCC), the NchMOS transistor Qn1
1 and Qn12 are turned on, and the potential of the node B becomes the ground level (0 V).
It becomes CC level. The potential of this node C remains unchanged for Nch
Output voltage Vout through MOS transistor Qn12
(= −VCC).

Next, when the output voltage Vout rises to some extent (at the end of the starting process), the clamp pulse level shift circuit 37 starts operating. When the level shift circuit 37 starts operating, the clamp pulse having the amplitude VCC-0 [V] supplied from the timing generation circuit 15 is supplied to the level shift circuit 37 by the amplitude VCC-V.
The level is shifted to a clamping pulse of Vout [V], and then applied to the gate of the PchMOS transistor Qp13.

At this time, since the “L” level of the clamping pulse is the output voltage Vout, ie, −VCC, the Pch
MOS transistor Qp13 is reliably turned on.
As a result, the potential of the node D is clamped to the ground level (negative circuit power supply potential) instead of the potential shifted from the ground level by the threshold voltage Vth of the diode D11. Thereby, in the subsequent pumping operation, in particular, the PchMOS transistor Qp12
, A sufficient driving voltage can be obtained.

In the charge pump type power supply voltage conversion circuit having the above configuration, the switch element (Nch
A control pulse (switching pulse) voltage for the MOS transistor Qn12 and the PchMOS transistor Qp12) is first supplied to the diode D11 when the circuit is started.
, And after the start-up process, the clamping operation is performed in two stages, such as clamping by a clamping circuit including the PchMOS transistor Qp13 and the level shift circuit 37.
A sufficient drive voltage can be obtained for the transistor Qp12.

Thus, the PchMOS transistor Qp
12, a sufficient switching current can be obtained, so that a stable DC-DC conversion operation can be performed and the conversion efficiency can be improved. In particular, since a sufficient switching current can be obtained without increasing the transistor size of the PchMOS transistor Qp12, a power supply voltage conversion circuit with a large current capacity and a small circuit scale can be realized. The effect is the threshold V
This is particularly large when a transistor having a large th, for example, a thin film transistor is used.

The booster DD converter shown in FIG. 8B has the same basic circuit configuration and circuit operation.

That is, in FIG. 8B, the switching transistor and the clamping transistor (MO
The S transistors Qp14, Qn14, Qn13) are the MOS transistors Qn12, Qp1 of the circuit of FIG.
2, Qp13 and the diode D
11 is connected between the other end of the capacitor C11 and the power supply (VCC), and the level shift circuit 37 uses the output voltage Vout of this circuit as a positive circuit power supply and the ground level as a negative circuit power supply. Figure 8
The only difference from the circuit of FIG.

In terms of circuit operation, basically, FIG.
This is exactly the same as the circuit of FIG. The difference is that the switching pulse voltage (control pulse voltage) is first diode-clamped at startup, clamped to the VCC level (positive circuit power supply potential) at the end of the startup process, and output voltage Vout is twice the power supply voltage VCC. Voltage value 2 × V
Only the point from which the CC is derived. FIG.
Signal waveforms A to G at nodes A to G in the circuit of FIG.
3 shows a timing chart.

The circuit configuration of the power supply voltage conversion circuit of the charge pump type described above is merely an example, and various modifications can be made to the circuit configuration of the charge pump circuit, and are not limited to the above-described circuit configuration example. Absent.

In each of the above embodiments, as the timing pulse generated by the timing generation circuit 15, the latch control pulse used in the latch circuits 27U and 27D of the H drivers 13U and 13D and the power supply composed of a charge pump type power supply voltage conversion circuit Although the switching pulse and the clamping pulse used in the circuit 16 have been described as examples, the invention is not limited thereto.

As an example, when the V driver 14 has a configuration having an output enable circuit that outputs a scan pulse when an output enable pulse is supplied, an output enable pulse used in the output enable circuit or a display device is used. Has a configuration in which a partial screen display mode for displaying information only in a partial area of the display area, which is one mode of the power saving mode, is selectively used. Pulse).

The active matrix type display device according to each of the above-described embodiments is used not only as a display for OA equipment such as a personal computer and a word processor, but also for a display such as a television receiver. Mobile phones and PDAs
It is suitable for use as a display unit of a portable terminal such as a portable terminal.

FIG. 10 shows a portable terminal to which the present invention is applied,
FIG. 1 is an external view schematically illustrating a configuration of a mobile phone, for example.

The portable telephone according to the present embodiment has a configuration in which a speaker section 42, a display section 43, an operation section 44, and a microphone section 45 are arranged in order from the upper side on the front side of an apparatus housing 41. In the mobile phone having such a configuration, the display unit 4
For example, a liquid crystal display device 3 is used as the liquid crystal display device 3, and the active matrix liquid crystal display device according to each of the above-described embodiments is used as the liquid crystal display device.

As described above, in a portable terminal such as a portable telephone, by using the active matrix type liquid crystal display device according to each of the above-described embodiments as the display section 43, a circuit of a timing generation circuit mounted on the liquid crystal display device is used. The configuration is simple, the size of the display device is reduced, the cost is reduced,
Further, power consumption can be reduced, so that the terminal body can be reduced in size, cost can be reduced, and power consumption can be reduced.

[0067]

As described above, according to the present invention,
In a timing generation circuit, an active matrix display device equipped with the same, or a portable terminal using the same as a display unit, a vertical drive circuit and a horizontal drive circuit are generated based on timing information generated by at least one of a vertical drive circuit and a horizontal drive circuit. Since the timing signal used for at least one of the driving circuits is generated, a circuit configuration can be simplified by a part of at least one of the vertical driving circuit and the horizontal driving circuit that can be used for generating the timing signal. Thus, it is possible to reduce the size, cost, and power consumption of the set.

[Brief description of the drawings]

FIG. 1 is a schematic configuration diagram showing a configuration example of an active matrix display device according to the present invention.

FIG. 2 is a circuit diagram illustrating a configuration example of a display area of a liquid crystal display device.

FIG. 3 is a block diagram illustrating an example of a specific configuration of an H driver.

FIG. 4 is a block diagram illustrating a configuration example of an active matrix display device according to an embodiment of the present invention.

FIG. 5 is a block diagram illustrating an example of a specific configuration of a timing generation circuit.

FIG. 6 is a timing chart for explaining the operation of the timing generation circuit.

FIG. 7 is a block diagram illustrating a configuration example of an active matrix display device according to another embodiment of the present invention.

FIG. 8 is a circuit diagram showing a configuration example of a charge pump type power supply voltage conversion circuit, where (A) shows a negative voltage generation type;
(B) shows the boost type.

9A and 9B are timing charts for explaining the circuit operation of the charge pump type power supply voltage conversion circuit, where FIG. 9A shows a case of a negative voltage generation type, and FIG. 9B shows a case of a step-up type.

FIG. 10 is an external view schematically showing a configuration of a mobile phone which is a mobile terminal according to the present invention.

[Explanation of symbols]

11: glass substrate, 12: display area, 13U, 13
D: H driver (horizontal drive circuit), 14: V driver (vertical drive circuit), 15: timing generation circuit, 16:
Power supply circuit, 23: unit pixel, 25U, 25D, 29: shift register, 31-1 to 31-M, 32: latch control pulse generation circuit, 33: D-type flip-flop (DF
F)

Continued on the front page (51) Int.Cl. ⁷ Identification symbol FI Theme coat II (Reference) G09G 3/20 680 G09G 3/20 680G G02F 1/133 550 G02F 1/133 550 G09G 3/30 G09G 3/30 Z 3 / 36 3/36 F term (reference) 2H093 NA16 NC16 NC22 NC27 NC34 ND39 ND42 ND49 ND54 5C006 BB16 BC02 BC20 BF03 BF04 BF22 BF46 FA41 FA47 FA51 5C080 AA06 AA10 BB05 DD22 DD26 DD27 JJ02 JJ03 KK04 KK06

Claims (14)

[Claims] 1. A display area in which pixels having an electro-optical element are arranged in a matrix, a vertical drive circuit for selecting each pixel in the display area on a row-by-row basis, and a vertical drive circuit selected by the vertical drive circuit. A timing generation circuit used in an active matrix display device including a horizontal drive circuit that supplies an image signal to each pixel in a row, wherein a timing generated by at least one of the vertical drive circuit and the horizontal drive circuit A timing generating circuit for a display device, wherein a timing signal used for at least one of the vertical driving circuit and the horizontal driving circuit is generated based on information. 2. A display area section in which pixels having electro-optical elements are arranged in a matrix, a vertical drive circuit for selecting each pixel of the display area section on a row-by-row basis, and a vertical drive circuit selected by the vertical drive circuit. A horizontal drive circuit that supplies an image signal to each pixel in a row; and at least one of the vertical drive circuit and the horizontal drive circuit based on timing information generated by at least one of the vertical drive circuit and the horizontal drive circuit And a timing generating circuit for generating a timing signal used in the active matrix display device. 3. At least one of the vertical drive circuit and the horizontal drive circuit has a shift register or a counter circuit that performs address control and performs a count operation for generating timing data. 3. The active matrix display device according to claim 2, wherein the timing signal is generated based on the timing data generated by the shift register or the counter circuit. 4. The horizontal drive circuit according to claim 1, further comprising: a shift register or a counter circuit for performing address control and performing a count operation for generating timing data; and a timing data sequentially output from the shift register or the counter circuit. A latch circuit for latching a video signal to be displayed in the display area section, wherein the timing generation circuit uses a part of the timing data generated by the shift register or the counter circuit to operate the latch circuit. 4. The active matrix type display device according to claim 3, wherein a latch control pulse is generated. 5. The vertical drive circuit has an output enable circuit that outputs a scan pulse when an output enable pulse is supplied, and the timing generation circuit sequentially outputs from a shift register or a counter circuit of the horizontal drive circuit. 4. The active matrix display device according to claim 3, wherein the output enable pulse is generated based on the timing data. 6. A partial screen display mode for displaying information only in a partial area of the display area portion, wherein the timing generation circuit is sequentially output from a shift register or a counter circuit of the horizontal drive circuit. 4. The active matrix display device according to claim 3, wherein the control signal for the partial screen display mode is generated based on the timing data. 7. The active matrix type display device according to claim 2, wherein said electro-optical element is a liquid crystal cell. 8. The active matrix display device according to claim 2, wherein said electro-optical element is an electroluminescence element. 9. In each pixel of the display area, an active element for driving the electro-optical element is formed of a thin film transistor, and at least the transistor circuit forming the timing generation circuit is formed on the same substrate as the display area by the thin film transistor. The active matrix display device according to claim 2, wherein the active matrix display device is formed integrally with the display device. 10. A power supply circuit for converting a single DC voltage into a plurality of types of DC voltages having different voltage values and applying the converted voltage to at least the vertical drive circuit and the horizontal drive circuit, 3. The active matrix display device according to claim 2, wherein a timing signal used in the circuit is also generated. 11. The active matrix according to claim 10, wherein said power supply circuit is a charge pump type power supply voltage conversion circuit, and said timing signal is a switching pulse used in said charge pump type power supply voltage conversion circuit. Type display device. 12. A display area, in which pixels having electro-optical elements are arranged in a matrix as a display, a vertical drive circuit for selecting each pixel of the display area on a row-by-row basis, and the vertical drive circuit. A horizontal drive circuit that supplies an image signal to each pixel of a row selected by the vertical drive circuit and the horizontal drive circuit based on timing information generated by at least one of the vertical drive circuit and the horizontal drive circuit. A mobile terminal using an active matrix display device including a timing generation circuit for generating a timing signal used in at least one of the circuits. 13. The mobile terminal according to claim 12, wherein the active matrix display device is a liquid crystal display device using a liquid crystal cell as the electro-optical element. 14. The mobile terminal according to claim 12, wherein the active matrix display device is an electroluminescence display device using an electroluminescence element as the electro-optical element.