JP2007057554A - Electro-optical device and electronic apparatus - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide an electro-optical device and an electronic apparatus in which the capability of a power supply is increased in a display region requiring much load current while the capability of the power supply is decreased in a non-display region requiring no load current in a partial display mode by controlling a clock in a charge pump circuit, and thereby, the electric energy power is efficiently supplied. <P>SOLUTION: The electro-optical device includes: a scan line driving circuit which sequentially selects scan lines; a data line driving circuit which supplies display data to a data line when the scan line is selected; a switching element to connect the data line and a pixel when a selection voltage is applied to the scan line; and a power supply circuit including a charge pump circuit in which the power supply capability is controlled by clocks, and generating a plurality of voltage levels to the respective scan line and the data line based on the power supply voltage. In a partial display mode, the frequency of clocks supplied to the power supply circuit is decreased in a non-display region. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to an electro-optical device and an electronic apparatus having a partial display function that includes a power supply circuit using a charge pump circuit, and that displays only a part of a region and sets other regions to a non-display state.

  In general, an electro-optical device, for example, a liquid crystal device, forms a display unit composed of a plurality of pixels at the intersection of a plurality of scanning lines (hereinafter referred to as gate lines) and a plurality of data lines (hereinafter referred to as source lines). Use to display the video signal. A liquid crystal device includes a plurality of liquid crystal cells whose light transmission amount is controlled based on the data signal of each pixel and a thin film transistor (TFT: an abbreviation of Thin Film Transistor) for switching a data signal supplied from a source line to the liquid crystal cell. And a driving circuit portion having a scanning line driving circuit (hereinafter referred to as a gate driver) and a data line driving circuit (hereinafter referred to as a source driver) for driving the gate line and the source line, respectively.

  On the other hand, in the liquid crystal device, a full-screen display mode in which an image is displayed on the entire screen using all pixels of the display panel, and only a desired scanning line is selected from all the scanning lines of the display panel, and the selected scanning line is selected. Some of them have a partial (partial) display mode in which an image is displayed only on a part of the screen using pixels corresponding to. In this case, in the full screen display mode, scanning is performed over the entire screen, and it is a matter of course that the display data is written from the data lines to the entire screen, but in the display area and the non-display area in the partial display mode, Although scanning is performed over the screen, a driving method is employed in which display data is written from the data lines to the display area and display data is not written from the data lines to the non-display area.

  On the other hand, as a power supply circuit for an electro-optical device such as a liquid crystal device or a semiconductor device, a charge pump circuit is used for reasons such as low loss current and good conversion efficiency to power.

  For example, in a semiconductor memory device using a charge pump circuit as a power supply circuit, the capacity of the charge pump circuit (the amount of current that can be supplied to the load) is controlled by changing the clock according to the load state. There exists what was comprised (for example, refer patent document 1).

Similarly, a charge pump circuit is used as a power supply circuit of a display device using an electro-optical material such as an organic EL as a pixel, and the sum of pixels that are turned on is calculated from data that defines whether the pixel is turned on or off. At the same time, as the calculated sum of the pixels increases, the charge pump circuit's capacity is increased to suppress a decrease in the power supply voltage supplied to the display panel, thereby stabilizing the voltage and preventing a change in luminance. Some are configured as described above (see, for example, Patent Document 2).
JP-A-10-269787 JP 2003-241705 A

  However, when a charge pump circuit is used as a power supply circuit in an electro-optical device having a partial display function in which only a part of the area is displayed and other areas are not displayed, the display is performed in the partial display mode. By changing the capacity of the charge pump circuit between the area and the non-surface area, the current can be changed according to the difference between the display area and the non-display area in the partial display mode and the difference between the normal gradation display and the monochrome display in the display area. There was no one that was able to supply by switching the supply capacity appropriately.

  Therefore, in view of the above problems, the present invention controls the charge pump circuit clock to increase the power supply capability in the display area where a large amount of load current is required in the partial display mode, thereby eliminating the unnecessary display of the load current. An object of the present invention is to provide an electro-optical device and an electronic apparatus that can reduce the power supply capability and can efficiently supply power.

  An electro-optical device according to the present invention includes a plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the scanning lines and the data lines, and displays a full screen. In an electro-optical device capable of selecting a full screen display mode and a partial display mode in which a part of the whole screen is a display area and another area is a non-display area, the scanning line sequentially selects the scanning lines. A driving circuit; a data line driving circuit for supplying display data to the data line when the scanning line is selected; and a conduction state between the data line and the pixel when a selection voltage is applied to the scanning line A power supply circuit that generates a plurality of voltage levels on the scanning line and the data line based on a power supply voltage. If, comprising a, in the partial display mode, the relative non-display region, characterized by lowering the frequency of the clock supplied to the power supply circuit.

  According to such a configuration of the present invention, when the partial display mode is entered, the clock of the charge pump circuit is controlled to be low with respect to the non-display area, so that the power In a normal load state such as a display area, the power supply capacity can be increased, power can be efficiently supplied, and power consumption can be reduced.

  In the present invention, in the partial display mode, writing of display data to the data line in the non-display area is performed using a voltage generated by a power source different from the power source circuit as a data signal.

  According to such a configuration, the display data write voltage to the data line for the non-display area is required to generate a gradation voltage as in the data line driving circuit when the voltage data generated by the data line driving circuit is used. Since the drive power is consumed, the power consumption in the data line drive circuit system is reduced by using a low voltage generated by a power supply different from the data line drive circuit system power supply, and the overall power consumption Can be reduced.

  In the present invention, in the partial display mode, when the display area is displayed in binary, display data is written to the data line using a binary voltage generated by a power supply different from the power supply circuit as a data signal. It is characterized by performing.

  According to such a configuration, the display data write voltage to the data line at the time of binary display such as monochrome display of the display area is generated by a power source different from the data line driving circuit system power source 2. By using the value voltage, the driving voltage required to generate the gradation voltage as in the data line driving circuit is not used, so the power consumption in the data line driving circuit system is reduced and the overall power consumption is reduced. be able to.

  In the present invention, in the partial display mode, the frequency of the clock when the display area is binary-displayed is lower than the frequency of the clock during gradation display of the display area, and the frequency relative to the non-display area It is characterized by being set higher than the clock frequency.

  According to such a configuration, when the display load is small as in binary display such as black and white display, the frequency of the clock of the charge pump circuit is lower than the frequency of clock in gray scale display, By making the frequency higher than the clock frequency for the display area, power can be supplied efficiently and power consumption can be reduced.

  In the present invention, in the partial display mode, the frequency switching from the non-display area to the display area to the higher frequency of the clock is performed prior to display switching by writing display data to the data line. It is characterized by that.

  According to such a configuration, when shifting from the non-display area to the display area in the partial display mode, the charge charge amount per unit time to the pumping capacitor accompanying the increase in the clock frequency of the charge pump circuit is accelerated. By starting display and writing the display data to the data lines with the power supply capacity increased, the power supply voltage fluctuation (decrease) when the display data was actually displayed was suppressed and stable. A high quality display operation can be performed.

  The electro-optical device according to the present invention is selectable between a full screen display mode for displaying a full screen and a partial display mode in which a part of the full screen is a display area and another area is a non-display area. The optical device includes a charge pump circuit whose power supply capability is controlled by a clock, and includes a power supply circuit that generates a plurality of voltage levels based on a power supply voltage. In the partial display mode, the non-display area The frequency of the clock supplied to the power supply circuit is lowered.

  According to such a configuration of the present invention, when the partial display mode is entered, the clock of the charge pump circuit is controlled to be low with respect to the non-display area, so that the power In a normal load state such as a display area, the power supply capacity can be increased, power can be efficiently supplied, and power consumption can be reduced.

An electronic apparatus according to the present invention includes the electro-optical device described above.
According to such a configuration, when shifting to the partial display mode, by controlling the clock of the charge pump circuit, the capacity of the power supply is lowered at a place where load current is unnecessary such as the non-display area, and the display area is The power supply capacity can be increased where a large amount of load current is required, and an electronic apparatus including an electro-optical device that can efficiently supply power can be realized.

Embodiments of the invention will be described with reference to the drawings.
[First Embodiment]
FIG. 1 is a diagram showing a schematic configuration of an electro-optical device according to a first embodiment of the present invention. An example of the electro-optical device is a liquid crystal device.
In FIG. 1, the electro-optical device includes a plurality of data lines (hereinafter referred to as source lines) 1, a plurality of scanning lines (hereinafter referred to as gate lines) 2 arranged substantially orthogonal to the source lines 1, and the plurality of data lines. A plurality of switching elements 3 provided corresponding to a plurality of intersections of the source line 1 and the plurality of gate lines 2, a plurality of pixel electrodes 4 provided corresponding to the plurality of switching elements 3, A counter electrode 5 disposed opposite to the pixel electrode 4, an electro-optical material 6 such as liquid crystal interposed between the pixel electrode 4 and the counter electrode 5, and a scanning line driving circuit (hereinafter referred to as “scanning line driving circuit”) for sequentially driving the plurality of gate lines 2. A gate driver) 7, a data line driving circuit (hereinafter referred to as a source driver) 8 that converts a data signal from the controller 12 into a display pixel signal and outputs the signal, and a charge pump whose power supply capability is controlled by a clock. A power supply circuit 10 including a path 11 for supplying a plurality of voltage levels necessary for driving to the gate driver 7 and the source driver 8 based on a power supply voltage VDD from the battery, and a control for switching between a full screen display mode and a partial display mode. And a controller 12 that generates timing signals, display data signals, and control signals necessary for the gate driver 7, the source driver 8, and the power supply circuit 10. The display mode is switched based on an instruction from an operation button (not shown), an instruction to switch display of specific contents (for example, calendar display and time display related thereto), or display data is not displayed. The display mode control unit 13, which is automatically performed based on the presence / absence determination of the display area, controls the gate driver 7, the source driver 8 and the power supply circuit 10 to set the full screen display mode and a part of the display area as the display area. It has a function of performing control to switch between a partial display mode in which a portion is a non-display area.

  The display unit 14 is a display unit including a plurality of source lines 1, a plurality of gate lines 2, a plurality of switching elements 3, a plurality of pixel electrodes 4, a counter electrode 5, and an electro-optical material 6. In FIG. 1, the gate driver 7, the source driver 8, the power supply circuit 10, and the controller 12 are configured as separate circuits. However, the gate driver 7, the source driver 8, the power supply circuit 10, and the controller 12 are integrated into one chip. Alternatively, the one chip may be electrically connected to the display unit 14.

Display pixel signals S1 to Sm are supplied from the source driver 8 to the plurality of (m) source lines 1 to the plurality of source lines 1 of the display unit 14, respectively.
The plurality of switching elements 3 are provided for each pixel, and TFTs (field effect thin film transistors) are used as the switching elements 3. The TFT as the switching element 3 has a source connected to one of the source lines 1, a gate connected to one of the gate lines 2, and a drain connected to the pixel electrode 4. When a high level signal is applied to the gate of the TFT from the gate line 2, the source and drain are rendered conductive, and the pixel signal from the source line 1 connected to the source driver 8 is applied to the pixel electrode 4. ing. The pixel electrode 4 is disposed to face the counter electrode 5 with the electro-optical material 6 interposed therebetween, and optical characteristics such as light transmittance of the electro-optical material 6 change according to the potential difference between the pixel electrode 4 and the counter electrode 5. Thus, it becomes possible to display with light and shade (gradation) corresponding to the pixel signal voltage.

  On the other hand, scanning line drive signals g1 to gn from the gate driver 7 are sequentially transmitted to the plurality of gate lines 2 of the display unit 14 in time sequence with respect to each of the plurality (n) of gate lines 2. The plurality of switching elements 3 that are gate-connected in the row direction to the gate line to which the scanning line drive signal is supplied are turned on, so that only that gate line is activated. When display pixel signals are simultaneously input from the source driver 8 via the plurality of source lines 1 to the sources of the plurality of switching elements 3 in the ON state, A display pixel signal is written to the pixel electrode 4).

FIG. 2 shows the configuration of the power supply circuit 10. That is, a system diagram of the power supply system is shown.
As described above, the power supply circuit 10 includes the charge pump circuit 11 (11-1 and 11-2 in FIG. 2) in which the power supply capability (the amount of current that can be supplied to the load) is controlled by the frequency of the clock, and the battery 15 The gate driver 7 and the source driver 8 have a function of supplying a plurality of voltage levels necessary for driving based on the power supply voltage VDD.

  In FIG. 2, a power supply circuit 10 includes a battery 15, a charge pump type double booster circuit 11-1, a charge pump type triple booster circuit 11-2, an oscillation circuit 16, and a first power source of a source driver system. 17, a source driver system second power source 18, and a gate driver system first power source 19.

  The battery 15 is an original power source that outputs a power supply voltage VDD (for example, 2.6 V). The charge pump type double booster circuit 11-1 generates a voltage VDD2 (= VDD × 2) obtained by boosting the battery voltage VDD twice, and is used as a source driver power supply. The charge pump type triple booster circuit 11-2 generates a voltage VDD3 (= VDD × 3) obtained by boosting the battery voltage VDD three times and is used as a gate driver power supply. The oscillation circuit 16 is constituted by a clock generating oscillator whose oscillation frequency can be varied by a control signal from the controller 12.

  The first power source 17 of the source driver system is supplied from the double boosted voltage VDD2 to 0. A voltage VDDHS (maximum voltage of DAC analog output) that drops by a margin of several V is generated and provided as a buffer amplifier (voltage follower) at the output stage of the DAC (digital / analog converter) in the source driver 8. The voltage VDDHS is supplied to the source output amplifier 20 as a power supply voltage. The analog output of the source output amplifier 20 is supplied as a display pixel signal to the source line 1 which is a data line of the display unit 14.

  The second power source 18 of the source driver system generates a voltage VGM (maximum voltage of γ gradation) slightly lower than the voltage VDDHS, and is a level provided as a gradation voltage generating means before the source output amplifier 20. One end of the adjustment setting ladder resistor 23 is supplied via the buffer amplifier 21 and the switch 22. The switch 22 is turned on during normal gradation display driving, and is turned off during binary display such as time display or non-display driving where display is not performed, for generating gradation voltages. The voltage supply line to the ladder resistor 23 is disconnected, and display data is written to the source line 1 using a low-level voltage or a binary voltage generated by another power source (not shown). In the case of binary driving or non-display driving, if the ladder resistor 23 for generating the gradation voltage is disconnected, the power flowing through the resistor 23 can be reduced. Note that the data signal is supplied to the source line 1 when this separation is performed by using a voltage for binary display from another power source or a low voltage for non-display, thereby generating a gradation voltage. The power can be reduced compared to the power consumption caused by always passing a current through the ladder resistor 23.

  The switch 24 is selectively connected to appropriate voltage dividing points of a plurality of resistors constituting the ladder resistor 23 according to the digital value of the data signal for gradation display when the switch 22 is in an ON state. The gradation voltage corresponding to the digital value is output and supplied to the input terminal of the source output amplifier 20.

  The first power supply 19 of the gate driver system is supplied from the triple boosted voltage VDD3 to. A voltage VGATE dropped by a margin of several V is generated, and the voltage VGATE is supplied to the gates of the plurality of switching elements 3 connected to each gate line of the display unit 14.

  FIG. 3 shows the magnitude relationship between the various drive voltage levels described in FIG. VSS is the ground level, VDD is the original power supply voltage, VDD2 is the boost voltage of [original power supply voltage] × 2, VDD3 is the boost voltage of [original power supply voltage] × 3, and VGATE is the gate power supply voltage of the gate driver 7 , The analog power supply voltage of the source driver 8 and VGM indicate the gamma gradation power supply voltage of the source driver 8. For example, VDD, VDD2, and VDD3 are 2.6V, 5.2V, and 7.8, respectively.

  The boost of VDD → VDD2 is a double boost, the boost of VDD → VDD3 is a triple boost, and these boosted voltages are generated by a charge pump circuit.

  Here, the control of the power supply capability becomes a problem in the case of a double boost power supply used in the source driver system. This is because the capability of the double boosting power source of the source driver system (that is, current supply capability) is related to actual display and non-display. That is, the capability of the charge pump circuit of double boosting from VDD to VDD2 is varied in accordance with each area of display, non-display, or monochrome display (binary display).

FIG. 4 is a timing chart showing a state where the frequency of the clock of the charge pump circuit is varied in the partial display mode. Vsync indicates a vertical synchronization signal, Hsync indicates a horizontal synchronization signal, DATA indicates a state of display data supplied to the pixel electrode, and CK indicates a frequency of the clock of the charge pump circuit.
In the display state in the full screen display mode and the display state in the partial display mode, both are driven in the display state, and the drive conditions of the source driver 8 are the same gradation display conditions. The drive capability (that is, current supply capability) of the double booster circuit 11-1 in the 10 charge pump circuits 11 needs to be in the highest state (= several times the horizontal frequency) (for example, in the DATA display state of FIG. 4). (See corresponding CK). In other words, in a state where gradation display is performed, the oscillation circuit is set so that the frequency of the clock CK supplied to the charge pump type double booster circuit 11-1 by the display mode control unit 13 is set to a predetermined high first frequency f1. 16 is controlled.

  On the other hand, in the non-display state in the partial display mode, the drive capability (that is, current supply capability) of the double booster circuit 11-1 in the charge pump circuit 11 of the power supply circuit 10 may be in a low state, and the display mode control unit 13 The oscillation circuit 16 is controlled so that the frequency of the clock CK supplied to the charge pump type double booster circuit 11-1 is set to a predetermined second low frequency f2 (= approximately horizontal frequency). The relationship is f2 <f1.

FIG. 5 shows a configuration of a charge pump type double booster circuit 11-1 as an example of the charge pump circuit. FIG. 6 shows the operation of two sets of double throw type switches SW1 and SW2 when charging and pumping in the charge pump type double booster circuit of FIG.
The charge pump type double booster circuit 11-1 has the same frequency supplied from the battery 15, the pumping capacitor Cp, the backup capacitor Cb, and the oscillation circuit 16 (see FIG. 2) and are mutually polar. Two sets of double-throw switches SW1 and SW2 that are turned on and off by inverted clocks CK1 and CK2 are provided. When the clock CK1 is at a high level, the clock CK2 is at a low level, and when the clock CK1 is at a low level, the clock CK2 is at a high level. The double throw type switches SW1 and SW2 are turned on (closed) when the clocks CK1 and CK2 are at a high level, and are turned off (opened) when the clocks CK1 and CK2 are at a low level.

  First, when the clock CK1 is at a high level and the switch SW1 is turned on (switch SW2 is turned off), the pumping capacitor Cp is connected in parallel to the battery 15 while the switch SW1 is turned on, and the battery 15 is connected to the pumping capacitor Cp. Is charged with the power supply voltage VDD. Next, when the clock CK2 becomes a high level and the switch SW2 is turned on (the switch SW1 is turned off), the pumping capacitor Cp and the battery 15 are connected in series while the switch CK2 is turned on. The capacitor Cb is connected in parallel, and the backup capacitor Cb is charged with a voltage VDD2 (= VDD × 2) obtained by adding the charging voltage VDD of the pumping capacitor Cp to the power supply voltage VDD of the battery 15. By repeating this switching operation, the voltage output across the backup capacitor Cb becomes a voltage held at twice the power supply voltage VDD. Here, if the frequency of the clocks CK1 and CK2 is controlled to be low, the number of times of charging per unit time that the power supply voltage VDD is charged to the pumping capacitor Cp from the battery 15 is reduced, so that it is supplied to the load. The amount of current (capacity) possible is reduced. When the frequency of the clocks CK1 and CK2 is controlled to be high, the number of times of charging per unit time that the power supply voltage VDD is charged to the pumping capacitor Cp from the battery 15 increases, so that it can be supplied to the load. The amount of current (capacity) increases.

FIG. 7 shows an example of the screen of the display unit 14 in the partial display mode. FIG. 7 (a) shows the area on the screen, the display area drive method and the drive switching timing. The waveform in FIG. 7 (b) is the difference in the display form on the screen described on the right of the screen in FIG. 7 (a). And the clock waveform of the charge pump circuit corresponding to the difference of the drive form (non-display area, partial binary drive, partial multi-value drive, non-display area) is shown. These are described below.
The drive switching points 1 and 2 and the display switching points 1 and 2 described on the left side of the screen in FIG. The drive switching point 1 means a time point when the clock frequency of the charge pump circuit is switched from a low frequency during non-display to a high frequency during display under the control of the display mode control unit 13 (see FIG. 1). This means a time point at which the clock frequency of the charge pump circuit is switched from a high frequency during display to a low frequency during non-display under the control of the display mode control unit 13 (see FIG. 1). The display switching point 1 means a point in time when the display state is switched from the non-display state by actually starting the writing of display data to the source line, and the display switching point 2 is connected to the source line. When the display data is actually written, the display state is switched to the non-display state (the display end time is the drive switching point 2, that is, the drive start point of the non-display area (to a low clock frequency). Is the same as the switch point).

  If the on / off frequency of the switches SW1 and SW2 of the charge pump circuit shown in FIG. 5 is increased, the power consumption is increased by increasing the number of on / off times of the switches. ) At the time of display, the capability, that is, the on / off frequency (clock frequency) of the switches SW1 and SW2 of the charge pump circuit is lowered so that the power consumption can be reduced.

  In FIG. 7, the hatched portion is a display region in a display state, and the white portion is a non-display region in a non-display state. In the present invention, as described above, when the partial display mode is entered, the clock of the charge pump circuit is controlled to be lower than that in the non-display area, so that the power supply can be turned off in a low load state such as in the non-display area. In the load state of the normal display (gradation display) such as the display area, the capacity of the power source can be increased, power can be efficiently supplied, and power consumption can be reduced.

  The display area in the partial display mode is not a display by scanning lines on the entire screen, but a display that is performed on a part of the area area using a part of scanning lines (one or more scanning lines) on the screen (reverse) In other words, it indicates display when there is at least one non-displayed scanning line. In the partial display area constituted by several scanning lines in the scanning direction, the driving of the pixel electrode corresponding to each scanning line by the source driver 8 is a normal multi-value (gradation) in gradation display. The load amount (load power) at the time of display is different between the case of display and the case of black and white (binary) display. In the case of normal multi-value display, a clock having a predetermined high first frequency f1 is used. In the case of black and white (binary) display, the power supply capacity is increased to cope with a high load amount, and in the case of multi-value display, the second clock frequency for the non-display area is lower than the first clock frequency f1 for the display area. Using a clock having a predetermined third frequency f3 higher than f2, the power supply capacity is made to correspond to the load level at the intermediate level. The relationship is f1> f3> f2. Thereby, when monochrome (binary) display is performed in the partial display mode, power can be efficiently supplied and power consumption can be reduced.

  As described above with reference to FIG. 2, for non-display or monochrome (binary) display, the switch 22 in FIG. 2 is turned off, and the data signals of non-display and binary display are displayed with different power. If it is generated, the power can be reduced. Therefore, if the clock frequency is reduced at the same time, it is possible to further improve the power reduction during non-display or monochrome (binary) display.

  On the other hand, when shifting to the partial display mode, the frequency switching from the non-display area to the display area to the first or third frequency f1 or f3 having the higher clock (display switching point 1 in FIG. 7) Prior to display switching (first display switching point on the upper side in FIG. 7) by writing display data to a line (that is, pixel electrode).

  As described above, the clock control by the charge pump circuit prior to the start of display writing in the display area is performed early in the case of shifting from the non-display area to the display area in the partial display mode. Write the display data to the data line with the power supply capacity increased in advance by increasing the charge amount per unit time (ie, increasing the clock frequency) to the pumping capacitor as the frequency increases. This means that the power supply capability is increased in advance when the display is actually performed, so that fluctuations in the power supply voltage can be suppressed and a stable display operation can be performed.

[Electronics]
Hereinafter, specific examples of an electronic apparatus including the electro-optical device according to the invention will be described.
FIG. 8 is a diagram illustrating an appearance of an electronic apparatus configured using the electro-optical device (for example, a liquid crystal device) described in the above embodiment. It is the perspective view which showed an example of the mobile phone.
In this figure, reference numeral 200 denotes a mobile phone body, and 201 denotes a display unit using the electro-optical device. Reference numeral 202 denotes a display unit side housing, 203 denotes an operation unit side housing, and 204 denotes a hinge portion that couples both housings so that they can be bent.

  When the electronic device shown in FIG. 8 shifts to the partial display mode of the device, the load current as in the non-display region is controlled by controlling the clock frequency of the charge pump circuit to be lower for the non-display region. The power supply capability can be reduced where the load current is not required, and the power supply capability can be increased where load current is required, such as the display area, and an electronic apparatus including an electro-optical device that efficiently supplies power can be realized.

  The electro-optical device of the present invention is not limited to a liquid crystal device, but an electroluminescent device, an organic electroluminescent device, a plasma display device, an electrophoretic device that displays images by supplying video signals such as R, G, and B to an electro-optical material. The present invention can be similarly applied to various electro-optical devices such as a display device and a device using an electron-emitting device (Field Emission Display, Surface-Conduction Electron-Emitter Display, etc.).

1 is a diagram illustrating a schematic configuration of an electro-optical device according to a first embodiment of the invention. The block diagram which shows the structure of the power supply circuit of FIG. The figure which shows the magnitude relationship of the various drive voltage levels demonstrated in FIG. 6 is a timing chart showing a state in which the clock frequency of the charge pump circuit is varied in the partial display mode. The circuit diagram which shows the structure of a charge pump type double booster circuit. FIG. 6 is a diagram for explaining the operation of two sets of double throw switches SW1 and SW2 during charging and during pumping in the charge pump circuit of FIG. 5; The figure which shows an example of the screen of the display part in partial display mode. FIG. 14 is a perspective view illustrating an example of an electronic device including the liquid crystal device of the invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Source line (data line), 2 ... Gate line (scanning line), 3 ... TFT, 4 ... Pixel electrode, 5 ... Counter electrode, 6 ... Electro-optical substance (liquid crystal), 7 ... Gate driver, 8 ... Source driver DESCRIPTION OF SYMBOLS 10 ... Power supply circuit, 11 ... Charge pump circuit, 12 ... Controller, 13 ... Display mode control part, 14 ... Display part.

Claims (7)

A plurality of scanning lines, a plurality of data lines, and a plurality of pixels provided corresponding to intersections of the scanning lines and the data lines, and a full screen display mode for displaying a full screen; In the electro-optical device capable of selecting a partial display mode in which a partial area on the screen is a display area and another area is a non-display area,
A scanning line driving circuit for sequentially selecting the scanning lines;
A data line driving circuit for supplying display data to the data line when the scanning line is selected;
A switching element that brings the data line and the pixel into a conductive state when a selection voltage is applied to the scanning line;
A power supply circuit including a charge pump circuit whose power supply capability is controlled by a clock, and generating a plurality of voltage levels for each of the scanning line and the data line based on a power supply voltage;
Comprising
In the partial display mode, an electro-optical device that reduces a frequency of a clock supplied to the power supply circuit for the non-display area.   2. In the partial display mode, writing display data to the data lines in the non-display area is performed using a voltage generated by a power source different from the power source circuit as a data signal. Electro-optic device.   In the partial display mode, writing of display data to the data lines when the display area is displayed in binary is performed using a binary voltage generated by a power source different from the power supply circuit as a data signal. The electro-optical device according to claim 1 or 2, characterized in that   In the partial display mode, the frequency of the clock when the display area is binary-displayed is lower than the frequency of the clock at the gradation display of the display area, and is lower than the frequency of the clock for the non-display area. The electro-optical device according to claim 1, wherein the electro-optical device is set high.   In the partial display mode, the frequency switching from the non-display area to the display area to the higher frequency of the clock is performed prior to display switching by writing display data to the data line. The electro-optical device according to claim 1. In an electro-optical device capable of selecting a full-screen display mode for displaying a full screen and a partial display mode in which a partial area in the full screen is a display area and another area is a non-display area,
A charge pump circuit whose power supply capability is controlled by a clock, and a power supply circuit that generates a plurality of voltage levels based on a power supply voltage;
In the partial display mode, an electro-optical device that reduces a frequency of a clock supplied to the power supply circuit for the non-display area.   An electronic apparatus comprising the electro-optical device according to claim 1.

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