CN100435352C - 垂直mos功率晶体 - Google Patents

垂直mos功率晶体 Download PDF

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CN100435352C
CN100435352C CNB2003801050173A CN200380105017A CN100435352C CN 100435352 C CN100435352 C CN 100435352C CN B2003801050173 A CNB2003801050173 A CN B2003801050173A CN 200380105017 A CN200380105017 A CN 200380105017A CN 100435352 C CN100435352 C CN 100435352C
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普拉萨德·温卡特拉曼
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Abstract

一种晶体管(10)，如DMOS晶体管，形成在具有用于形成沟道(40)的第一表面(19)的半导体衬底(12)上。覆盖沟道第一部分的栅介质(22)具有第一厚度，介质膜(20)覆盖沟道的第二部分并具有大于第一厚度的第二厚度。该第二厚度减小了晶体管的漏至栅电容，从而改善了其开关速度和频率响应。

Description

垂直MOS功率晶体
技术领域
本发明一般涉及半导体器件，并且更具体地涉及垂直MOS功率晶体管。
背景技术
通过使用晶体管切换经过电感器或变压器的电流以产生调节过的输出电压，开关调节器实现了高效率。经常用于开关调节器的一种类型的开关晶体管是功率双扩散金属氧化物半导体(DMOS)晶体管。DMOS晶体管典型地是垂直晶体管，其中电流横向地流经沿半导体管芯的顶表面形成的多个电平行沟道，到达公共漏极，并且然后垂直地流经漏区，到达在管芯的底表面上形成的漏电极。
已有的DMOS晶体管具有高漏至栅电容的缺点，这使切换减慢，并降低了晶体管和/或系统的效率。结果，开关调节器具有低的效率，并且晶体管具有高的热耗散和降低的可靠性。为了实现小的管芯尺寸和低成本，栅电极被形成在薄介质层上方，并在位于顶表面处的公共漏区的一部分上方布线。栅电极和公共漏区的重叠产生了整个漏至栅电容的实质部分，并导致了开关功率晶体管的开关速度和频率响应的降低。
发明内容
因而，需要一种具有低的漏至栅电容从而以较高的速度切换的功率晶体管，以降低功率耗散并提高可靠性。
根据本发明，提供一种晶体管，包括：具有第一导电类型的半导体衬底，其中，所述半导体衬底形成漏区；形成在所述半导体衬底的水平顶面上的阱区，以提供用于功率开关装置的基本上水平沟道，其中，所述阱区具有第一边缘；形成在所述阱区中的第一导电类型的源区；形成在所述半导体衬底和一部分所述阱区上的栅介质层，其中，所述栅介质层具有第一厚度；以及覆盖于栅介质层的相邻部分之间的顶表面而形成的介质区，其中，所述介质区具有大于所述第一厚度的第二厚度，并且，所述介质区的锥形边缘在所述沟道处与所述第一边缘重叠，从而降低所述晶体管的漏至栅电容，而没有实质地改变有效导通阈值；以及覆盖于所述栅介质层和介质区上的栅电极。
附图说明
图1是垂直功率晶体管的截面图；
图2是在可替代的实施方式中的晶体管截面图。
具体实施方式
在图中，具有相同参考数字的元件具有类似的功能。
图1是垂直功率晶体管10的截面图，该晶体管形成在半导体衬底12上并被设置成双扩散金属氧化物半导体(MOS)晶体管。多个单元体11典型地被连接在衬底12的水平顶表面19上，以形成行、列、单元体或类似图案的阵列。或者，晶体管10可以被制作成单个的、连续的蛇形或分支状的布局。每一个单元体11包括沿顶表面19延伸并由阱区15的反型部分形成的两个沟道40。沟道40如下所述平行连接，并且也被耦接到图1图面外的其它沟道40上，从而提供高电流容量。在一个实施方式中，衬底12由n型单晶硅形成，晶体管10是指定成在至少30伏的漏至源电压和至少0.5安培的漏电流IDS下工作的n沟道器件。在另一个实施方式中，晶体管10被制作成在顶表面具有其漏电极的平面器件，以形成横向DMOS器件。
在衬底12的底表面18上形成下层13，该层被重掺杂，使得晶体管10在低的导通电阻下工作。在一个实施方式中，下层13具有n型导电性和大约1019原子/立方厘米的掺杂浓度。在替代实施方式中，下层13具有p型导电性，用于将晶体管10设置成绝缘栅双极晶体管。
采用选择成提供所需的击穿电压的掺杂浓度，在下层13的上方形成外延层14。外延层14典型地被适当地轻掺杂，具有大约2微米到大约50微米范围内的厚度和大约1014到大约5*1016原子/立方厘米范围内的掺杂浓度。在一个实施方式中，外延层14具有n型导电性和大约3微米的厚度以及大约2*1016原子/立方厘米的掺杂浓度。外延层14和下层13用作晶体管10的公共漏区。
阱区15形成在顶表面19上并进入外延层14内，掺杂分布被选择成提供晶体管10的预定导通阈值。在一个实施方式中，阱区15具有p型导电性、大约1微米的深度，以及大约5*1017原子/立方厘米的表面掺杂浓度。阱区15在表面19处被电互连接到图1的图面之外的其它阱区19。
源区16形成在顶表面19上，并进入阱区15内，用于电耦接在阱区15中形成的两个沟道40。源区16被重掺杂，以提供晶体管10的低导通电阻。在一个实施方式中，源区16被制作成具有n型导电性、大约0.2微米的深度，以及大约1020原子/立方厘米的掺杂浓度。
在表面19上方形成栅介质22，以支持将下面部分的阱区15反转以形成沟道40的电场。栅介质22典型地被制作成具有大约75埃到大约1000埃之间的范围内的厚度，这取决于指定的导通阈值和/或击穿电压。在一个实施方式中，栅介质22被制作成具有大约400埃厚度的热生长二氧化硅。
栅电极25由栅介质22的区域上方的导电材料制成，以接收调节沟道40导电的控制信号。在一个实施方式中，栅电极25由被重掺杂以提供低电阻的多晶硅形成。在一个实施方式中，栅电极25被制作成具有n型导电性，并被沉积到大约0.65微米的厚度。栅电极25的分离部分在图面外被连接在一起。
晶体管10的导通阈值电压是阱区15的掺杂浓度和栅介质22的厚度二者的函数。导通阈值随栅介质22的厚度以及阱区15的表面掺杂浓度的增加而增加。导通阈值电压随栅介质22的厚度或者阱区15的掺杂浓度的减小而减小。在一个实施方式中，晶体管10的导通阈值电压被选择成大约1.5伏。
如图所示在栅介质22的相邻部分之间的表面19上形成介质区20。介质区20被制作成比栅介质22厚，以增加外延层14和栅电极25之间的间隔，从而减小晶体管10的漏至栅电容的相应分量。介质区20典型地被制作成具有大约2000埃和大约10000埃之间范围内的厚度，这取决于指定的击穿电压。在一个实施方式中，介质区20通过图案化和腐蚀其厚度为大约6000埃的沉积或热生长二氧化硅膜而形成。介质区20被表示成具有基本上垂直的侧壁，但也可以采用任意数目的标准腐蚀步骤而制成，以提供更好台阶覆盖度(step coverage)的倾斜侧壁。
注意介质区20覆盖阱区15的边缘23，并从而也覆盖沟道40。结果，栅电极25和外延区14之间的垂直隔离在所有的位置都由介质区20的厚度而不是由栅介质22决定。这种配置实现了较低的漏至栅电容以及比由其它器件提供的更高的开关速度。
由于介质区20覆盖边缘23，所以覆盖沟道40的介质膜在由区域20导致的部分处比由栅介质22导致的其它部分处更厚。因为介质区20基本上比栅介质22厚，在介质区20下面的沟道40部分将具有较高的阈值。然而，由于在制作期间阱区15掺杂剂向外扩散，阱区15在边缘23处具有比邻近源区16的浓度更低的掺杂浓度。更低的掺杂浓度补偿了由介质区20的厚度导致的任何增加，从而沿沟道40的整个长度保持了基本上均匀的导通阈值。因而，沟道40与介质区20重叠提供了具有较高开关速度和/或较高频率响应的晶体管10，而没有降低其导通阈值电压。在一个实施方式中，沟道40具有大约0.8微米的长度，区域20覆盖沟道40达到大约0.2微米，没有改变晶体管10的导通阈值。
在栅电极25和其它区域上方形成介质层27，用于与随后的金属化互连层电隔离。在一个实施方式中，介质层27由沉积到大约6000埃厚度的二氧化硅形成。
在晶体管10的表面上方沉积金属互连膜，并将其图案化以形成如图所示的源电极28。源电极28也连接图1的图面之外的其它源区16和阱区15。在一个实施方式中，源电极28具有大约3微米的厚度。图面之外的金属膜的区域被用于形成用于互连栅电极25的栅端子。
在底表面18上形成金属层，以形成用于对流经沟道40的漏电流IDS形成外部路线的漏电极42。在一个实施方式中，漏电极42为大约3微米厚。
图2是替代实施方式中晶体管10的截面图。晶体管10具有与上述内容类似的结构和操作，除了介质区20被部分地凹进到顶表面19之下。
在该替代实施方式中，采用标准的局部氧化半导体(LOCOS)或类似的工艺形成介质区20。在一种这样的工艺中，经由例如由氮化硅制成的硬掩模(未示出)中的开口热氧化外延层14的暴露部分。通过向开口中注入n型掺杂剂以提高外延区14的局部导电性、从而降低晶体管10的导通电阻，并禁用晶体管10的寄生结场效应晶体管而形成漏增强区21。在注入n型掺杂剂之后，热氧化工艺将暴露的半导体材料转化成半导体的氧化物，例如二氧化硅，其体积超过了所消耗的半导体材料。暴露的半导体材料被消耗，以形成如图所示的表面19之下的介质区20的下部分和表面19之上的上部分。
在热氧化工艺期间，氧在硬掩模的边缘下方扩散，从而氧化半导体材料并在介质区20的周围形成锥形的“鸟嘴”特征。锥形形貌和至少部分凹进的薄膜的组合提供了有利于良好台阶覆盖度的相对平整的表面，使得诸如栅电极25的覆盖膜高度共形，减薄很小或没有减薄，得到高可靠性。因此，介质区20避免了陡直的垂直台阶，同时提供了导致低漏至栅电容的较厚薄膜。在一个实施方式中，介质区20被制作成峰厚度为大约7000埃。
锥形的边缘也允许介质区20在阱区15上方延伸的距离比其它实施方式更大。因此，对于更大部分的沟道40，覆盖的介质厚度可以比栅介质22更大，而没有改变晶体管10的有效导通阈值。在沟道40的长度为大约0.8微米的一个实施方式中，介质区20覆盖沟道40的距离为大约0.3微米。
总之，本发明提供了一种具有降低的漏至栅电容和更高的开关速度和频率响应的垂直DMOS晶体管。该晶体管形成在具有用于形成沟道的第一表面和用于形成漏电极的第二表面的半导体衬底中，使得沟道电流在第一和第二表面之间流过。栅介质具有第一厚度并覆盖沟道的第一部分。介质膜覆盖沟道的第二部分并具有不同于例如大于第一厚度的第二厚度。该增加的厚度提高了晶体管的开关速度和频率响应，从而通过降低功率耗散而提高了其效率，并改善了可靠性。

Claims (7)

1.一种晶体管，包括：
具有第一导电类型的半导体衬底，其中，所述半导体衬底形成漏区；
形成在所述半导体衬底的水平顶面上的阱区，以提供用于功率开关装置的基本上水平沟道，其中，所述阱区具有第一边缘；
形成在所述阱区中的第一导电类型的源区；
形成在所述半导体衬底和一部分所述阱区上的栅介质层，其中，所述栅介质层具有第一厚度；以及
覆盖于栅介质层的相邻部分之间的顶表面而形成的介质区，其中，所述介质区具有大于所述第一厚度的第二厚度，并且，所述介质区的锥形边缘在所述沟道处与所述第一边缘重叠，从而降低所述晶体管的漏至栅电容，而没有实质地改变有效导通阈值；以及
覆盖于所述栅介质层和介质区上的栅电极。
2.权利要求1的晶体管，其中所述介质区包括LOCOS介质区。
3.权利要求2的晶体管，其中所述LOCOS介质区覆盖所述基本上水平沟道的距离为0.3微米。
4.权利要求1的晶体管，其中所述介质区与所述第一边缘重叠0.3微米。
5.权利要求1的晶体管，其中所述阱区在所述第一厚度附近具有第一表面掺杂浓度，在所述第二厚度附近具有第二表面掺杂浓度，其中第一表面掺杂浓度大于第二表面掺杂浓度。
6.权利要求1的晶体管，还包括形成在所述半导体衬底中的漏增强区，所述漏增强区与所述介质区相邻且与所述阱区分隔开。
7.权利要求1的晶体管，还包括形成在所述半导体衬底的第二表面上、用于形成沟道电流流经路线的漏电极。
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