CN100409450C - Nanowire and electronic device - Google Patents

Nanowire and electronic device Download PDF

Info

Publication number
CN100409450C
CN100409450C CNB038068869A CN03806886A CN100409450C CN 100409450 C CN100409450 C CN 100409450C CN B038068869 A CNB038068869 A CN B038068869A CN 03806886 A CN03806886 A CN 03806886A CN 100409450 C CN100409450 C CN 100409450C
Authority
CN
China
Prior art keywords
district
nano wire
etching
growth temperature
growth
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
CNB038068869A
Other languages
Chinese (zh)
Other versions
CN1643695A (en
Inventor
E·P·A·M·巴克斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN1643695A publication Critical patent/CN1643695A/en
Application granted granted Critical
Publication of CN100409450C publication Critical patent/CN100409450C/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B82—NANOTECHNOLOGY
    • B82Y—SPECIFIC USES OR APPLICATIONS OF NANOSTRUCTURES; MEASUREMENT OR ANALYSIS OF NANOSTRUCTURES; MANUFACTURE OR TREATMENT OF NANOSTRUCTURES
    • B82Y10/00—Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02367—Substrates
    • H01L21/0237—Materials
    • H01L21/02373—Group 14 semiconducting materials
    • H01L21/02381—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02524—Group 14 semiconducting materials
    • H01L21/02532—Silicon, silicon germanium, germanium
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02538—Group 13/15 materials
    • H01L21/02543—Phosphides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02587—Structure
    • H01L21/0259—Microstructure
    • H01L21/02603—Nanowires
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/0262—Reduction or decomposition of gaseous compounds, e.g. CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02636—Selective deposition, e.g. simultaneous growth of mono- and non-monocrystalline semiconductor materials
    • H01L21/02653—Vapour-liquid-solid growth
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0673—Nanowires or nanotubes oriented parallel to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/0676—Nanowires or nanotubes oriented perpendicular or at an angle to a substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0657—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body
    • H01L29/0665—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape of the body the shape of the body defining a nanostructure
    • H01L29/0669—Nanowires or nanotubes
    • H01L29/068—Nanowires or nanotubes comprising a junction
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70—Bipolar devices
    • H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/73—Bipolar junction transistors
    • H01L29/7317—Bipolar thin film transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78696—Thin film transistors, i.e. transistors with a channel being at least partly a thin film characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
    • H01L33/04—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction
    • H01L33/06—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a quantum effect structure or superlattice, e.g. tunnel junction within the light emitting region, e.g. quantum confinement structure or tunnel barrier

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Nanotechnology (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Crystallography & Structural Chemistry (AREA)
  • Materials Engineering (AREA)
  • Mathematical Physics (AREA)
  • Theoretical Computer Science (AREA)
  • Thin Film Transistor (AREA)
  • Electrodes Of Semiconductors (AREA)

Abstract

The nanowire ( 10 ) comprises a first region ( 1 ), a second region ( 2 ), and a third region ( 3 ), wherein the diameter (c) of the second region ( 2 ) is greater than the diameters (a) of the first and the third region ( 1, 3 ), therewith interrupting at least partially the quantization of the nanowire ( 10 ) and giving the second region a smaller bandgap. The second region ( 2 ) has a length (b) in axial direction of less than 100 nm, preferably less than 20 nm. The nanowire ( 10 ) can be used in an (opto-)electronic device having electrodes as a quantum dot, a single-electron transistor, or the like.

Description

Nano wire and electronic device
Technical field
The present invention relates to a kind of nano wire with first and second districts of axially-aligned, this first and second district is adjacent one another are.
The invention still further relates to a kind of electronic device that provides first and second electrodes, it utilizes at least one nano wire to interconnect.
The invention still further relates to the manufacture method of nano wire.
The invention further relates to a kind of dispersion (dispersion) of nano wire.
Background technology
Nano wire is the conventional semi-conducting material line that has less than the 100nm diameter.They are considered to be used for the building block of following electronic component and photoelectric cell.Nano wire has advantage, and is promptly not too relevant with the size restrictions that causes by photoetching composition.In addition, because quantum effect nonhmic resistor for example, so nano wire has and is different from those same materials and has the characteristic of the assembly of bigger size.
Just known this nano wire and this device in the 617-620 page or leaf from people such as Gudiksen in the 415th phase of nature (Nature, 415 (2002), 617-620)) in 2002.Known nano wire comprises first district of p type doping and second district of adjacent n type doping on the axial direction of nano wire with first district.Between two districts, there is p-n junction.Nano wire has the diameter of 20-50nm and comprises two types of for example semi-conducting materials of GaP and GaAs; Or the Si that mixes of the Si that mixes of n type and p type and with the InP of preceding identical doping.Can adopt electronic device to be used as light-emitting diode and as rectifier with this nano wire.
A shortcoming of known nano wire is the expectation that can't realize basically nano electron device.Known nano wire is carried out known reduce in scale function, but the quantum potential that it can not utilize the nano wire by two dimensional constraint to provide.
Summary of the invention
Therefore, first purpose of the present invention provides a kind of nano wire of wherein realizing quantum potential.
Second purpose of the present invention provides at a kind of electronic device described in the preamble, and it comprises according to nano wire of the present invention.
The 3rd purpose of the present invention provides a kind of dispersion according to nano wire of the present invention.
In the nano wire in first, second and the 3rd district with axially-aligned, realize first purpose, wherein second district is adjacent with the first and the 3rd district and have length less than 100nm in the axial direction, and second district has the bigger diameter than the first and the 3rd district.
Realize second purpose, nano wire wherein according to the present invention is rendered as the connector between first and second electrodes.
Realize the 3rd purpose, disperse is according to nano wire of the present invention in dispersant.
In nano wire according to the present invention, insert second district, so that this district has littler band gap.Obtained to be suitable for most electric charge carrier thus and be electronics or hole so that appear at more effectively in this district.The result utilizes the electrode of device just can fully on purpose control electron distributions in the nano wire: under certain conditions, electric charge carrier is blocked in second district, can not conducting between first and second electrodes.Under other condition, electric charge carrier is excited effectively, so it just can cross over the energy barrier in second district.Therefore, just may conducting between first and second electrodes.
Thus, in fairly simple mode, novel electronic component and photoelectric cell have just been realized.Embodiment be can be used as " single-electronic transistor " of digital transistor, wherein can digitlization in nanometer range " quantum dot memory " and the photoelectricity complex centre of storage.
In first embodiment according to nano wire of the present invention, the first and the 3rd district has the average diameter of maximum 10nm diametrically, and second district has bigger diameter diametrically.In second district, promote two-dimentional quantization to small part.This shows in the electronics band of crystal and presents more high level.According to k=N π/a, the quantity k of energy level in fact directly and crystal extend into direct ratio, wherein a is that interatomic phase mutual edge distance and N are the atomicities on certain (crystal) direction.In second district, atomicity N is greater than the atomicity in the first and the 3rd district diametrically.This just means and has more high level.Therefore, the non-overlapped quantization that refers to various energy levels in fact just littler degree can not occur or reach.Like that just mean band gap, promptly occupied energy level and the not distance between the occupied energy level subsequently are just less, and therefore, electric charge carrier will have more opportunity to drop into lower energy level.
If two-dimentional quantized part, promote to small part and to be limited to a sub-district, this will be favourable.Therefore, preferably, second district has 20nm or shorter little length in the axial direction.In the axial direction, its diameter is preferably less than 50nm, is more preferably the length that approximates second district greatly.In addition, if the first and the 3rd district has less than 10nm, is more preferably the very little diameter less than 5nm, this will be favourable.The length in the first and the 3rd district is preferably greater than 10nm in the axial direction, more preferably greater than 50nm and less than 2000nm.Has this length and very the nano wire of minor diameter can be manufactured and stable.And the nano wire with this length can easily bond to electrode structure.
In nano wire according to the present invention, first there is no need to have identical diameter in fact with the 3rd district.Unique condition is to have quantum effect in the first and the 3rd district.In fact advantage is asymmetricly to constitute nano wire, for example in order to realize rectifier function.Therefore, the diameter in first district is for example 5nm, and the diameter in the 3rd district is for example 10nm.
In the further embodiment according to nano wire of the present invention, and have the 4th and the 5th district, wherein the 4th district utilizes the quantization that promotes to small part than major diameter and/or some other architectural differences, simultaneously the 5th district displaying quantum effect really.Therefore, just can limit a kind of structure in nano wire according to the present invention, this structure comprises not only quantized interruption.For example, as " many quantum dots ", this structure is favourable, quantity that wherein can the store status discrete state.Under this mode, just can set up a kind of new Digital memory.
In the further embodiment according to nano wire of the present invention, nano wire comprises the different materials in second district of larger diameter, and this material has the band gap littler than the band gap in the first and the 3rd district.The example in this first and the 3rd district comprises Si, and second district comprises SiGe.Selectively, second district can comprise SiC.For SiGe, second district can also comprise C.In second district, use to have more the material of spatia zonularis and strengthened and partly promote quantized effect.
In the alternative embodiment according to nano wire of the present invention, with respect to the first and the 3rd district, the nano wire in second district has different doping.This example is that the p type mixes in second district, is that the n type mixes in the first and the 3rd district.This has just produced a kind of p-n-p knot or transistor, and wherein part has promoted quantization in the n district.This just causes for the introducing of optical coupling and/or output can optimize the n zone properties.If second district for example has the approximately more length of 80nm, more likely be limited to the contact at place, second district in addition.For example, this just can utilize photoetching technique.This same similar n-p knot, particularly n-p-n knot or transistor of being applicable to.This knot is used for light-emitting diode (LED) very knownly.In fact, in the compound p type district that preferably occurs among the LED of electric charge carrier; This district produces higher effect than spatia zonularis.
This nano wire has further advantage, and wherein second district of larger diameter can easily make it by etching technique except comprising different materials or different the doping.Have different etch-rates for other material or other etchant that uses that mixes, cause the diameter variation that is obtained.Meet especially especially for etching anode and for the final etching of the nano wire under thermal oxidation and the elevated temperature.
Further between preferred first and second districts and the step transition between the second and the 3rd district.The result of this step transition is that second district will have cylindrical shape.When controlling manufacturing process well, just can form this step transition.It is oval or circular also wishing to specify second district, is owing to realized from first district to second district and from the gradual transition of the 3rd district to second district.
Nano wire according to the present invention preferably includes one or more semi-conducting materials.Be Si, SiC, SiGe, GaAs, InP, InAsP in this example.What may replace is that the first and the 3rd district comprises metallization material, and second district comprises semi-conducting material.
Nano wire not only can be used for the specific function of big circuit, and can realize the integrated circuit based on nano wire.Preferably, electrode and the wherein interior various nano wires formation contacts that are connected.Selectively, nano wire can be used for discrete transistor, for example is used in the thin-film transistor of control chart as screen pixels.
In the embodiment that device according to the present invention is fit to, have nano wire with the first, second, third, fourth and the 5th district, wherein in second district and in the 4th district to small part interruption quantization.Also there are first and second gate electrodes.First and second gate electrodes separate with nano wire by dielectric layer and interconnect in non-conductive mode.The vertical protrusion of the first grid electrode on the nano wire and second area overlapping, and the vertical protrusion of second gate electrode on the nano wire and the 4th area overlapping in this way, have just obtained to have the transistor of several gate electrodes.Therefore, each gate electrode is all controlled a district of nano wire, and this district has littler bandwidth, and wherein part promotes quantization.Limiting the capacitive coupling between first and second gate electrodes, is favourable if the 3rd district has greater than 300nm, more preferably greater than the length of 1000nm.Nano wire can also be used for gate electrode.
The 4th purpose of the present invention provides the method that can make according to nano wire of the present invention.
Make in the method for nano wire, realized this purpose utilizing catalytic reaction to grow, wherein growth second district under than the higher temperature in the first and the 3rd district.
In manufacture method according to nano wire of the present invention, also realized this purpose, the method comprising the steps of:
The etching mask of composition is provided on the surface of Semiconductor substrate; And
The etching semiconductor substrate, so that under different condition during the Semiconductor substrate of first, second and the 3rd layer of etching, be substantially perpendicular on this surperficial direction and forming nano wire, this first, second and the 3rd floor corresponding to first, second and the 3rd district of nano wire.
Have been found that and to make that wherein adopt the condition that is fit to during growing period or etching, consequently the more material of deposit or general's material still less etch away in second district according to nano wire of the present invention.In known manner, particularly by regulating certain material or intermediate products, adjusting temperature and being adjusted in the dynamics that electromotive force in the electrochemical process is provided with these technologies.Under this consular district technical staff known " steam-liquid-solid " technology kind growing state, be particularly suitable for the adjusting of the condition of serviceability temperature.The engraving method that adopts can be reactive ion etching, dry etching and etching anode.Described among the formerly unpub application EP02075950.2 (NL020199) and a kind ofly made the method for nano wire, quoted and reference at this by etching anode.
If wish nano wire not only how much variations but also changes in material on diameter, preferably make the latter, wherein utilize reactive ion etching or dry etching to come the etching semiconductor substrate.Therefore, must select Semiconductor substrate, wherein provide to have required composition and/or each layer of doping, perhaps construct Semiconductor substrate by these layers basically.For example, in Semiconductor substrate, can utilize epitaxial growth that this layer is provided.
In a preferred embodiment, after growth, remove nano wire from substrate.This just can adopt them in disperse, be used for the application on the substrate.Yet, for other application, for example display element and optical memory element, advantage is to provide the nano-wire array on a kind of substrate.For example, can remove nano wire with ultrasonic vibration.
Description of drawings
To explain these aspects and others in further detail with non-restrictive example with reference to the accompanying drawings according to nano wire of the present invention and electronic device, wherein:
Fig. 1 shows a kind of nano wire, and
Fig. 2 shows a kind of electronic device with nano wire.
Embodiment
Fig. 1 shows according to nano wire 10 of the present invention, and nano wire 10 has first district 1, second district 2 and the 3rd district 3.The diameter c in second district 2 is greater than the diameter in the first and the 3rd district 1,3.This has just interrupted the quantization of nano wire 10 to small part, and the littler band gap in given second district 2.Second district 2 has less than 100nm in the axial direction, is more preferably the length b less than 20nm.As shown in Figure 2, nano wire 10 can be used for electronic device 100, and has nano wire 10 between first and second electrodes 101,102.Therefore, whole assembly especially can form single-electronic transistor, quantum dot memory or photoelectric cell.
Embodiment 1
Has the thin gold layer that 0.5-3nm is set on the silicon semiconductor substrate of oxidized surface.This Semiconductor substrate is put into the quartz ampoule at the first end place of reacting furnace.Fixing InP target is put into the second end place of reacting furnace, so that the InP of evaporation can be carried to substrate along quartz ampoule by air-flow.Find time reacting furnace to be lower than 10Pa.Then, pressure is set to 3 * 10 4Pa, Ar flow are 100-300sccm.Reacting furnace is heated to 500 ℃.So just golden slabbing is opened and is formed the whisker (cluster) of nanometer range.Under this temperature, melt target with ArF laser with 193nm wavelength.This has just caused with the growth of Au whisker as the InP nano wire 10 of catalyst.The nano wire that obtains comprises first district 1, second district 2 and the 3rd district 3.
Have 200nm, usually after first district 1 of the nano wire 10 of 100-1000nm and diameter 10nm, temperature be increased to 550-600 ℃ having grown.Consequently dissolved more InP in the Au whisker, the volume of whisker increases thus.Also has the result that grown nano wire can become thicker.Therefore, form second district 2 with 15-50nm diameter.Yet the diameter in first district does not increase, because adopted higher laser pulse frequency.After during 10-60 second, temperature is reduced to 500 ℃ once more.Under this temperature, the 3rd district 3 of grow nanowire 10 grows into the nano wire 10 with about 200-2000nm total length until.The result is the nano wire with shape as shown in fig. 1, its have the diameter (a) in the first and the 3rd district that equals 10nm, in the axial direction equal 15nm second district length (b) and 15 and 50nm between the diameter (c) in second district.If desired this example be the length in the first and the 3rd district of 100nm can select greatlyyer, up to the scope of millimeter magnitude.
Embodiment 2
With with the same way as of embodiment 1, on substrate, form the Au whisker.At 3cm 3STP/ minute silane and 18cm 3Pass through the chemical vapor deposition grow silicon nanowires under the environment of the 100ppm phosphine under STP/ minute the He, under 450 ℃.After the nano wire of 100-1000nm of growing, temperature is increased to 500 ℃ thus.This result just makes more Si be dissolved in the Au whisker, and the volume of whisker and diameter just increase thus.The result is that the part width of nano wire expands to 15-50nm, has therefore formed second district.After second, temperature is reduced to 450 ℃ at 10-60 once more.Further grow nanowire under this temperature is the nano wire of 200-2000nm up to producing total length.
Embodiment 3
Double-deck photosensitive layer is provided on Semiconductor substrate, and this bilayer photosensitive layer is made up of the thick lower floor of the 400nm of the ShipleyAXS1813 that cures by force and the thick upper strata of 80nm of electron sensitive resist.Utilize ray (electron beam, 100kV, 100 μ C/cm 2) come the composition should the bilayer photosensitive layer, limit isolated area thus.These isolated areas have the diameter of 50 * 50nm and each other at a distance of 1.0 μ m.The development upper strata, and immerse in the isopropyl alcohol subsequently.Then, in 0.3Pa oxygen plasma etch step, at 0.07W/cm 2The low radio frequency power density and-figure anisotropically is converted to lower floor from the upper strata under the 170V Dc bias.
Then, etching semiconductor substrate on the direction that is substantially perpendicular to the surface.(ICP) carries out this etching by dry etching with inductively coupled plasma, wherein alternately carries out etching step and passivation step.Radio frequency control (13.56MHz) is handled.Etching step adopts SF 6/ O 2/ C 4F 8Mist.Here, under the pressure of about 2Pa, standard value is the SF of 130sccm 6The O of air-flow, 13sccm 2The C of air-flow and 40sccm 4F 8Air-flow.The gas that is used for passivation step and adopts is the C with 140sccm gas flow rate 4F 8Be 8 seconds the normal period of etching step and passivation step.
Mainly carry out etching at three phases.In the phase I, etching has the micropore of cone diameter.Wherein carry out etching step within a short period of time or the etching step littler than passivation step intensity obtains micropore.The result has only removed the passivation layer that provides fully at the recess of micropore during passivation step.The part passivation layer is retained on the hole wall of micropore, and thus on passivation layer deposit a passivation layer.The result that this has just caused micropore to become narrower.
In second stage, etching step is bigger and/or the duration is longer than passivation step intensity.This has just caused the micropore depression to be widened to the result of about initial diameter.
In the phase III, etching step and passivation step are all very short.This has just caused micropore to narrow down or no longer or can not etch away the projection of hole wall basically.A large amount of short etching steps and passivation step just cause embedding projection in passivation layer.Yet, in the depression of micropore, all having removed passivation layer fully at every turn, the result is an isotropic etching.
Downward etching semiconductor substrate is until the degree of depth of about 0.5 μ m and produce nano wire.Said hole wall convex to form larger-diameter second district.In oxygen atmosphere, during 2 hours, continue heated substrate to about 850 ℃.Thermal oxidation silicon thus.Then, Semiconductor substrate is put into the hydrogen fluoride bath that concentration is about 5 mol.In bath, keep circulation, so that the component of bath is remained unchanged.The result is the nano wire that obtains the 10nm diameter in the first and the 3rd district.In the second bigger district of original depth, after this processing, thickness is still bigger.The Semiconductor substrate that will have nano wire is put into the ethanol bath.This bath is put into Vltrasonic device.By ultrasonic vibration, from the substrate separation nano wire.
The disperse of the nano wire that forms thus is provided on silicon substrate.Utilize electron ray (electron beam), photoetching limits and electrically contacts in the Au bilayer of the Ti of 2nm and 10nm.After applying nano wire, heating is until 400 ℃.
Embodiment 4
Has n type doping (doped level 10 19Atom/cm 3) Semiconductor substrate on epitaxial growth have the Si layer that the p type mixes.The thickness of grown layer is about 10-30nm.Epitaxial growth has the silicon layer that the n type mixes on it.The thickness of grown layer is about 300nm, usually 100 and 1000nm between.Described in embodiment 3, the substrate that obtains is carried out composition and etch processes.In this way, just obtained to have the nano wire of the interior n-p-n knot of having of larger-diameter p district.
Embodiment 5
On the surface of Semiconductor substrate, provide etching mask.The opening that it is 1.5 μ m that etching mask has regular phase mutual edge distance.Utilize the KOH etch processes, just define the depression of pointing out by etching mask.Then, Semiconductor substrate is put into anode unit.Then, the back side of Semiconductor substrate is immersed in the potassium sulfate solution, so that this back side is connected with anode conducting.The surface of Semiconductor substrate is immersed in the hydrofluoric acid solution.Under the current density in 0.9 and 1 time that is provided with, the anodization etch substrate has been described peak current density among the formerly unpub application EP02075950.2 (NL020199) in further detail, quotes and reference at this.Formed nano wire thus.The part that has obtained nano wire is widened, the lower current density of wherein instantaneous employing.
Embodiment 6
Fig. 2 is the schematic cross sectional view as the semiconductor element 100 of thin-film transistor.Source electrode 101 and drain electrode 102 are set on the substrate 110 of polyimides.Electrode 101,102 comprises for example Au, and photoetching limits electrode 101,102.Electrode 101,102 is separated from each other by path 10 5, and path 10 5 comprises the dielectric material with preferred low-k.The known suitable material of this consular district technical staff, wherein silicon dioxide, hydrogeneous silicate hydrogen sesquialter silica (hydrogensilsesquioxane) and methylic silicate (methyl silsesquioxane), porous silicon, SiLK and benzocyclobutene.The selection of material also depends on the selection of substrate.The surface 111 of planarization electrode 101,102 and path 10 5, so that on smooth basically surface 111, have nano wire 10.Place and aim at nano wire 10, wherein on surface 111, provide dispersion to drip, simultaneously, apply voltage with nano wire.The 0.1-1V/ μ m electric field that applies under the frequency of 0.1-10kHz has just caused the aligning of nano wire 10.Dielectric layer 106 is set on nano wire 10, gate electrode 103 is separated with nano wire 10.Selectively, can obtain to aim at, wherein on surface 11, channelled mold is set, and whole assembly is put into the bath that contains dispersion.Then, utilize pressure differential to influence air-flow, nano wire is sucked in the passage of mold thus.This has just caused the arrangement of the nano wire 10 of aligning.
This consular district technical staff should be understood that electronic device preferably includes a large amount of semiconductor element 100, and it interconnects by required figure and forms circuit.Should also be noted that, in single semiconductor element 100, can have one or a large amount of nano wires 10, and to select various materials for substrate 110, electrode 101,102,103 and dielectric layer 105,106 be that the technical staff of field of thin film transistors is known.

Claims (13)

1. a nano wire has first district, second district and the 3rd district in axially-aligned,
Wherein this second district in abutting connection with this first and the 3rd district and have length in the axial direction less than 100nm, and
Wherein this second district have than this first and the bigger diameter in the 3rd district, in the first and the 3rd district, produce quantum effect.
2. according to the nano wire of claim 1, it is characterized in that this second district in the axial direction has the length less than 20nm.
3. according to the nano wire of claim 1, it is characterized in that in the radial direction this first and the 3rd district have the average diameter of maximum 10nm.
4. according to the nano wire of claim 3, it is characterized in that this second district has the maximum gauge of 50nm.
5. according to the nano wire of claim 1, it is characterized in that this first district is that the n type mixes, and this second district is that the p type mixes.
6. according to the nano wire of claim 1, it is characterized in that existing the 4th and the 5th district, by the 3rd and the 5th district surround in the axial direction the 4th district and in the axial direction the 4th district have length less than 100nm, and the 4th plot structure is different from the 3rd and the 5th district, and wherein it has littler band gap.
7. electronic device that provides first and second electrodes, it utilizes at least one nano wire to interconnect, and it is characterized in that, has any one described nano wire in the claim 1 to 6.
8. according to the electronic device of claim 7, it is characterized in that existing the nano wire of claim 6, and there are first and second gate electrodes, the wherein vertical protrusion of this first grid electrode on this nano wire and this second area overlapping, and the vertical protrusion of this second gate electrode on this nano wire and the 4th area overlapping.
9. the manufacture method of the nano wire described in the claim 1 is utilized the catalytic reaction growth, wherein than this first and the higher temperature in the 3rd district under this second district of growing.
10. according to the method for claim 9, it is characterized in that the method comprising the steps of:
This first district of this nano wire of growth under first growth temperature;
This second district of this nano wire of growth under second growth temperature, this second growth temperature is higher than this first growth temperature; And
The 3rd district of this nano wire of growth under the 3rd growth temperature, the 3rd growth temperature is lower than this second growth temperature.
11. the manufacture method according to any one described nano wire in the claim 1 to 6 comprises step:
In the surface of Semiconductor substrate, provide the etching mask of composition; And
This Semiconductor substrate of etching, so that form this nano wire on the direction surperficial perpendicular to this, during etching, etch-rate reduces in this second district that is forming larger diameter.
12., wherein from this Semiconductor substrate, remove this nano wire according to the method for claim 11.
13. one kind in dispersant according to the dispersion of any one described nano wire in the claim 1 to 6.
CNB038068869A 2002-03-28 2003-03-27 Nanowire and electronic device Expired - Lifetime CN100409450C (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP02076428 2002-03-28
EP02076428.8 2002-03-28

Publications (2)

Publication Number Publication Date
CN1643695A CN1643695A (en) 2005-07-20
CN100409450C true CN100409450C (en) 2008-08-06

Family

ID=28459552

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB038068869A Expired - Lifetime CN100409450C (en) 2002-03-28 2003-03-27 Nanowire and electronic device

Country Status (6)

Country Link
US (1) US20050161659A1 (en)
EP (1) EP1502302A1 (en)
JP (1) JP4920872B2 (en)
CN (1) CN100409450C (en)
AU (1) AU2003215840A1 (en)
WO (1) WO2003083949A1 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007525830A (en) * 2003-12-22 2007-09-06 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Fabrication of semiconductor nanowire group and electronic device including nanowire group
US7180107B2 (en) * 2004-05-25 2007-02-20 International Business Machines Corporation Method of fabricating a tunneling nanotube field effect transistor
CN101010793B (en) 2004-06-30 2011-09-28 Nxp股份有限公司 Method for manufacturing an electric device with a layer of conductive material contacted by nanowire
GB0415891D0 (en) 2004-07-16 2004-08-18 Koninkl Philips Electronics Nv Nanoscale fet
JP2008515181A (en) 2004-09-27 2008-05-08 コーニンクレッカ フィリップス エレクトロニクス エヌ ヴィ Electrical device having nanowires with phase change material
TWI311213B (en) * 2004-12-24 2009-06-21 Au Optronics Corp Crystallizing method for forming poly-si films and thin film transistors using same
US7518196B2 (en) 2005-02-23 2009-04-14 Intel Corporation Field effect transistor with narrow bandgap source and drain regions and method of fabrication
FR2883101B1 (en) * 2005-03-08 2007-06-08 Centre Nat Rech Scient NANOMETRIC MOS TRANSISTOR WITH MAXIMIZED CURRENT TO CURRENT AND CURRENT STATE RATE
FR2904304B1 (en) * 2006-07-27 2008-10-17 Commissariat Energie Atomique METHOD FOR MANUFACTURING NANOSTRUCTURE ON A PRE-GRAVE SUBSTRATE
KR100905869B1 (en) 2006-10-10 2009-07-03 충북대학교 산학협력단 Method for preparing Single-Electron Logic Transistor with Dual Gates operating at Room Temperature
KR101334174B1 (en) * 2007-01-12 2013-11-28 삼성전자주식회사 Wire structure and semiconductor device comprising the wire structure
US7859036B2 (en) * 2007-04-05 2010-12-28 Micron Technology, Inc. Memory devices having electrodes comprising nanowires, systems including same and methods of forming same
US7719678B2 (en) * 2007-04-25 2010-05-18 Hewlett-Packard Development Company, L.P. Nanowire configured to couple electromagnetic radiation to selected guided wave, devices using same, and methods of fabricating same
JP5096824B2 (en) * 2007-07-24 2012-12-12 日本電信電話株式会社 Nanostructure and method for producing nanostructure
EP2056350A1 (en) * 2007-11-01 2009-05-06 Interuniversitair Microelektronica Centrum Method for making quantum dots
US8389387B2 (en) * 2009-01-06 2013-03-05 Brookhaven Science Associates, Llc Segmented nanowires displaying locally controllable properties
CN102169889A (en) * 2011-03-17 2011-08-31 复旦大学 Ultra-long semiconductor nano-wire structure and manufacturing method thereof
WO2016122005A1 (en) * 2015-01-26 2016-08-04 Duksan Hi-Metal Co., Ltd. Metal nanowire, method for synthesizing the metal nanowire, and transparent electrode and organic light emitting diode including the metal nanowire manufactured by the method
US10629838B2 (en) * 2015-01-26 2020-04-21 Duksan Hi-Metal Co., Ltd. Core-shell nanowire, method for synthesizing the core-shell nanowire, and transparent electrode and organic light emitting diode including the core-shell nanowire
WO2016122008A1 (en) * 2015-01-26 2016-08-04 Duksan Hi-Metal Co., Ltd. Method for synthesizing core-shell nanowire, core-shell nanowire manufactured by the same, and transparent electrode and organic light emitting diode including the core-shell nanowire

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510647A (en) * 1993-03-15 1996-04-23 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6294450B1 (en) * 2000-03-01 2001-09-25 Hewlett-Packard Company Nanoscale patterning for the formation of extensive wires
US6322713B1 (en) * 1999-07-15 2001-11-27 Agere Systems Guardian Corp. Nanoscale conductive connectors and method for making same
JP2002067000A (en) * 2000-08-29 2002-03-05 National Institute Of Advanced Industrial & Technology Metal nanowire and metal nanoparticle

Family Cites Families (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2679381B1 (en) * 1991-07-19 1993-10-08 Alcatel Alsthom Cie Gle Electric OPTO-ELECTRONIC CONVERTER.
US5347140A (en) * 1991-08-27 1994-09-13 Matsushita Electric Industrial Co., Ltd. Resonant electron transfer device
GB9213824D0 (en) * 1992-06-30 1992-08-12 Isis Innovation Light emitting devices
JPH06271306A (en) * 1993-03-17 1994-09-27 Nec Corp Rosary-like macromolecular cluster and formation thereof
USH1570H (en) * 1993-03-31 1996-08-06 The United States Of America As Represented By The Secretary Of The Army Variable lateral quantum confinement transistor
US5679961A (en) * 1994-09-13 1997-10-21 Kabushiki Kaisha Toshiba Correlation tunnel device
US5604154A (en) * 1994-10-27 1997-02-18 Nippon Telegraph And Telephone Corporation Method of manufacturing coulamb blockade element using thermal oxidation
JP3745015B2 (en) * 1995-09-21 2006-02-15 株式会社東芝 Electronic devices
JP2904095B2 (en) * 1996-01-31 1999-06-14 日本電気株式会社 Method of manufacturing single electronic device
US6538262B1 (en) * 1996-02-02 2003-03-25 The Regents Of The University Of California Nanotube junctions
JPH09312378A (en) * 1996-03-19 1997-12-02 Fujitsu Ltd Semiconductor device and manufacture thereof
US5972744A (en) * 1996-04-05 1999-10-26 Matsushita Electric Industrial Co., Ltd. Quantum effect device, method of manufacturing the same
US5917194A (en) * 1996-07-17 1999-06-29 The United States Of America As Represented By The Secretary Of The Army Mesoscopic electronic devices with tailored energy loss scattering
US6191432B1 (en) * 1996-09-02 2001-02-20 Kabushiki Kaisha Toshiba Semiconductor device and memory device
JP3487724B2 (en) * 1996-10-11 2004-01-19 沖電気工業株式会社 Method of forming tunnel junction
KR100223807B1 (en) * 1997-06-04 1999-10-15 구본준 Method of manufacturing semiconductor device
WO1999048810A1 (en) * 1998-03-24 1999-09-30 Kia Silverbrook Method for construction of nanotube matrix material
CA2268997C (en) * 1998-05-05 2005-03-22 National Research Council Of Canada Quantum dot infrared photodetectors (qdip) and methods of making the same
AU1864799A (en) * 1998-12-30 2000-07-24 Alexandr Mikhailovich Ilyanok Quantum-size electronic devices and methods of operating thereof
FR2818439B1 (en) * 2000-12-18 2003-09-26 Commissariat Energie Atomique METHOD FOR MANUFACTURING A CONFINED MATERIAL ISLAND BETWEEN ELECTRODES, AND APPLICATIONS TO TRANSISTORS
KR101008294B1 (en) * 2001-03-30 2011-01-13 더 리전트 오브 더 유니버시티 오브 캘리포니아 Methods of fabricating nanostructures and nanowires and devices fabricated therefrom
EP1262911A1 (en) * 2001-05-30 2002-12-04 Hitachi Europe Limited Quantum computer
US6843902B1 (en) * 2001-07-20 2005-01-18 The Regents Of The University Of California Methods for fabricating metal nanowires
US6978070B1 (en) * 2001-08-14 2005-12-20 The Programmable Matter Corporation Fiber incorporating quantum dots as programmable dopants
FR2830686B1 (en) * 2001-10-04 2004-10-22 Commissariat Energie Atomique TRANSISTOR WITH AN ELECTRON AND A VERTICAL CHANNEL, AND METHODS OF REALIZING A SUCH TRANSISTOR
KR100426495B1 (en) * 2001-12-28 2004-04-14 한국전자통신연구원 Semiconductor device using a single carbon nanotube and a method for manufacturing of the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5510647A (en) * 1993-03-15 1996-04-23 Kabushiki Kaisha Toshiba Semiconductor device and method of manufacturing the same
US6322713B1 (en) * 1999-07-15 2001-11-27 Agere Systems Guardian Corp. Nanoscale conductive connectors and method for making same
US6294450B1 (en) * 2000-03-01 2001-09-25 Hewlett-Packard Company Nanoscale patterning for the formation of extensive wires
JP2002067000A (en) * 2000-08-29 2002-03-05 National Institute Of Advanced Industrial & Technology Metal nanowire and metal nanoparticle

Also Published As

Publication number Publication date
CN1643695A (en) 2005-07-20
AU2003215840A1 (en) 2003-10-13
JP4920872B2 (en) 2012-04-18
EP1502302A1 (en) 2005-02-02
US20050161659A1 (en) 2005-07-28
JP2005522037A (en) 2005-07-21
WO2003083949A1 (en) 2003-10-09

Similar Documents

Publication Publication Date Title
CN100409450C (en) Nanowire and electronic device
CN100380603C (en) Method of manufacturing nanowires and electronic device
JP3000360B2 (en) Method for forming quantum dots in semiconductor device
US6544870B2 (en) Silicon nitride film comprising amorphous silicon quantum dots embedded therein, its fabrication method and light-emitting device using the same
US20070232028A1 (en) Method of manufacturing silicon nanowires using porous glass template and device comprising silicon nanowires formed by the same
TW201011859A (en) Semiconductor trench structure having a sealing plug and method
KR20110084178A (en) Method for making side growth semiconductor nanowires and transistors obtained by said method
CN106057915B (en) The RTD diode and production method of indium gallium nitrogen emitter ohmic contact layer
JPH06338631A (en) Light-emitting element and manufacture thereof
WO2007018076A1 (en) Crystal silicon element and method for fabricating same
JP2008130712A (en) Three terminal crystal silicon element
CN109545855B (en) Preparation method of active region of silicon carbide double-groove MOSFET device
CN107910747A (en) More ridge type semiconductor lasers and preparation method thereof
CN107731980A (en) A kind of UV LED structure and preparation method thereof
KR100462468B1 (en) Single nano wire and nano devices using thereof
KR100822745B1 (en) Semiconductor nanowire by porous nanotemplate, a method for manufacturing thereof, and a semiconductor device comprising the same
US6566692B2 (en) Electron device and junction transistor
CN117321785A (en) High efficiency InGaN light emitting diode
KR100966007B1 (en) Room Temperature operating Single Electron Device using Carbon Nano Tube and Fabrication Method thereof
CN106847910B (en) GaN-based semiconductor device and preparation method thereof
CN109860302A (en) A kind of power metal-oxide-semiconductor field effect transistor and its manufacture of new model
TW200816369A (en) Method of manufacturing a semiconductor device and semiconductor device obtained with such a method
KR100800508B1 (en) Single electron transistor having self-aligned trench and fabricating method of the same
CN117238738B (en) Vertical structure vacuum channel transistor based on wide bandgap material and preparation method thereof
KR100817535B1 (en) Semiconductor nanowire, method for manufacturing thereof, and semiconductor device comprising the same

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
CP01 Change in the name or title of a patent holder

Address after: Eindhoven, Netherlands

Patentee after: KONINKLIJKE PHILIPS N.V.

Address before: Eindhoven, Netherlands

Patentee before: KONINKLIJKE PHILIPS ELECTRONICS N.V.

CP01 Change in the name or title of a patent holder
TR01 Transfer of patent right

Effective date of registration: 20200715

Address after: Holland Schiphol

Patentee after: KONINKLIJKE PHILIPS NV

Address before: Eindhoven, Netherlands

Patentee before: KONINKLIJKE PHILIPS N.V.

TR01 Transfer of patent right
CX01 Expiry of patent term

Granted publication date: 20080806

CX01 Expiry of patent term