CN100403502C - 半导体器件的辅助设计装置 - Google Patents

半导体器件的辅助设计装置 Download PDF

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CN100403502C
CN100403502C CNB2004800378664A CN200480037866A CN100403502C CN 100403502 C CN100403502 C CN 100403502C CN B2004800378664 A CNB2004800378664 A CN B2004800378664A CN 200480037866 A CN200480037866 A CN 200480037866A CN 100403502 C CN100403502 C CN 100403502C
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insert
semiconductor chip
bonding wire
data
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CN1894786A (zh
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后藤明广
松岛弘伦
小川宏成
松田义雄
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NEC Electronics Corp
Mitsubishi Electric Corp
Renesas Electronics Corp
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Mitsubishi Electric Corp
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Abstract

一种辅助连接半导体芯片与插入物的键合引线的布线设计的半导体器件的辅助设计装置，具备作成模拟了半导体芯片的在插入物上的配置位置的偏差的发生和插入物的键合引线连接端子位置偏差的发生的模拟设计数据的作成单元。此外，具备根据上述模拟设计数据来分析起因于半导体芯片的在插入物上的配置位置的偏差和插入物的键合引线连接端子位置的偏差的半导体器件的制造中的不良情况的分析单元。

Description

半导体器件的辅助设计装置
技术领域
本发明涉及在配置逻辑电路或存储器等的半导体芯片的引线键合类型的半导体封装设计中考虑半导体制造工序中的制造偏差来进行关于键合引线布线的设计的半导体器件的辅助设计装置。
背景技术
以前，在半导体封装等的半导体器件中，利用半导体器件的辅助设计装置预先研究并设计插入物(interposer)或半导体芯片的配置位置或布线位置等。作为这样的半导体器件的辅助设计装置，例如有具备下述的单元的装置：输入例如具有芯片的布局信息的芯片数据和具有框架的布局信息的框架数据并配置在规定的位置上以作成合成图面的数据合成单元；对于用数据合成单元作成的合成图面参照在同一芯片中使用其它的框架作成的连线图信息自动地或以对话方式作成芯片、框架间连线图的连线图作成单元；以及根据利用连线图作成单元作成的芯片、框架间连线图抽出并存储上述连线图作成单元在作成连线图时参照的连线图信息的连线图信息存储单元。在这样的半导体器件的辅助设计装置中，连线图信息存储单元存储连线图或所使用的焊盘等的连线图信息，以便在以后的与其它的框架的连线作业中来参照。由此，由于连线图作成单元参照利用该连线图信息存储单元存储了的连线图信息来作成连线图，故具有可正确地进行连线的优点。
专利文献1：特开平5-67679号公报
发明的公开
发明打算解决的课题
但是，在上述的以前的技术中，关于连接半导体芯片与引线框架间的键合引线，实施了键合引线环规则检验。但是，在这样的技术中，在制造前不能实施考虑了半导体器件的制造工序中的半导体芯片的配置位置的偏差的设计规则测定。因此，事先不能检测键合引线相互间的接触或键合引线与半导体芯片的接触等关于键合引线的不良情况，存在有时在实际的半导体器件的制造工序中发现这些不良情况的问题。这样的在实际的半导体器件的制造工序中的不良情况的发现与制品成品率下降相联系。
本发明是鉴于上述问题而进行的，其目的在于得到事先防止在半导体器件的制造时键合引线相互间的接触等的关于键合引线的不良情况从而以良好的制品成品率制造半导体器件的半导体器件的辅助设计装置。
用于解决课题的方法
为了解决上述课题以达到目的，与本发明有关的半导体器件的辅助设计装置是一种辅助连接半导体芯片与插入物的键合引线的布线设计的半导体器件的辅助设计装置，其特征在于，具备：作成模拟了半导体芯片的在插入物上的配置位置的偏差的发生和插入物的键合引线连接端子位置偏差的发生的模拟设计数据的单元；以及根据上述模拟设计数据来分析起因于半导体芯片的在插入物上的配置位置的偏差和插入物的键合引线连接端子位置的偏差的半导体器件的制造中的不良情况的分析单元。
以上那样的与本发明有关的半导体器件的辅助设计装置预先作成模拟了半导体芯片的在插入物上的配置位置的偏差的发生和插入物的键合引线连接端子位置偏差的发生的模拟设计数据。然后，根据该模拟设计数据进行考虑了半导体器件的制造工序中的制造偏差的设计规则检验。即，通过分析、验证模拟设计数据，事先检测起因于半导体芯片的在插入物上的配置位置的偏差和插入物的键合引线连接端子位置的偏差的半导体器件的制造中的不良情况。
发明的效果
按照与本发明有关的半导体器件的辅助设计装置，通过实施考虑了半导体器件的制造工序中的制造偏差的设计规则测定，可在事先、即实施实际的半导体器件的制造之前在半导体器件的设计阶段中检测在半导体器件的制造时键合引线相互间的接触或键合引线与插入物的接触等的关于键合引线的不良情况。然后，在半导体器件的设计阶段中检测出关于键合引线的不良情况的情况下，可在设计阶段中修正这些不良情况以设计正常的半导体器件。因而，按照与本发明有关的半导体器件的辅助设计装置，可事先避免在半导体器件的制造时键合引线相互间的接触等的关于键合引线的不良情况的发生以提高制品成品率，起到可得到能进行制品成品率良好的半导体器件的制造的半导体器件的辅助设计装置的效果。
附图的简单地说明
图1是示出与本发明的实施形态有关的半导体器件的辅助设计装置的主要结构的框图。
图2是示出半导体封装的结构的一例的剖面图。
图3是示出半导体封装的结构的一例的俯视图。
图4是示出半导体芯片偏离插入物中的设计上的配置位置而配置的状态的图。
图5是示出插入物偏离设计上的配置位置而配置的状态的图。
图6是示出插入物偏离设计上的配置位置而配置的状态的图。
图7是示出插入物偏离设计上的配置位置而配置的状态的图。
图8是示出半导体芯片偏离设计上的配置位置而配置的状态的图。
图9是示出半导体芯片偏离设计上的配置位置而配置的状态的图。
图10是示出半导体芯片偏离设计上的配置位置而配置的状态的图。
图11是示出半导体芯片偏离设计上的配置位置而配置的状态的图。
图12是示出半导体芯片偏离设计上的配置位置而配置的状态的图。
图13是示出在主要因素表中分配制造偏差的主要因素及其水准的例子的图。
图14是示出在L9正交表中分配图13中的主要因素的例子的图。
图15是示出数据分析部中的输入与输出的图。
符号的说明
1半导体封装的设计数据
2输入控制部
3装配部
4插入物配置部
5芯片粘接部
6引线键合部
7设计规则测定部
7a测定结果
8测定结果数据
9数据分析部
10分析结果数据
11a半导体芯片
11b半导体芯片
12插入物
13键合引线
14键合焊盘
15键合指
16主要因素表
17正交表
用于实施发明的最佳形态
以下，根据附图详细地说明与本发明有关的半导体器件的辅助设计装置。再有，本发明不限于以下的记述，在不脱离本发明的要旨的范围内可适当地变更。
实施形态
图1是示出与本发明的实施形态有关的半导体器件的辅助设计装置的主要结构的框图。如图1中所示，与本实施形态有关的半导体器件的辅助设计装置100具备下述部分而构成：输入控制部2、插入物配置部4、芯片粘接部5、引线键合部6、设计规则测定部7、存储部8和数据分析部9。再有，在图1中，箭头线表示数据的流向，例如，1表示设计数据、7a表示测定结果、9a表示分析结果。此外，将插入物配置部4、芯片粘接部5、引线键合部6总称为装配部3。
此外，图2和图3是示出用该辅助设计装置可设计的半导体封装的结构的一例的图，图2是示出半导体封装的剖面的剖面图。此外，图3是从上面看半导体封装的俯视图。如图2和图3中所示，该半导体封装具备下述部分而构成：半导体芯片11a；半导体芯片11b(以下，关于半导体芯片，有时总称为半导体芯片11)；插入物12；键合引线13；键合焊盘14和键合指15。再有，在图2和图3中，示出了层叠2个半导体芯片的半导体封装的例子，但本发明不限定于此。因而，本发明也可适用于只具备1个半导体芯片的半导体封装的设计，此外，也可广泛地适用于具备大于等于3个半导体芯片的半导体封装的设计。
输入控制部2接受半导体封装的设计数据1。即，对输入控制部2输入图2和图3中示出的半导体封装用基板或引线框架等的插入物12的形状、半导体芯片11的形状、半导体芯片11的在插入物12上的配置位置、连接半导体芯片11与插入物12的键合引线13的形状、引线键合坐标即连接半导体芯片11与插入物12的键合引线13的配置位置等的关于半导体封装的设计数据1。装配部3以在输入控制部2中所输入的半导体封装的设计数据1为输入，作成模拟了制造偏差的发生的模拟设计数据。再有，不一定需要设置输入控制部2，也可作成从外部直接对装配部3输入关于半导体封装的设计数据1的形态。
插入物配置部4根据能够从输入控制部2输入的设计数据1，设想在插入物12的配置中产生了制造偏差的情况，作成在模拟了制造偏差的发生的位置上配置插入物12的情况的数据。即，在插入物配置部4中，作成进行了例如如图4中所示对于插入物12的设计上的配置位置在X方向(插入物的主面中的面内方向)上或例如如图5中所示在Y方向(插入物的主面中的面内方向)上产生制造偏差(插入物12的配置位置的偏差)的情况的插入物12的配置的数据。
此外，在插入物配置部4中，作成进行了例如如图6中所示对于插入物12的设计上的配置位置在倾斜方向、即X方向和Y方向的两个方向上或例如如图7中所示在旋转方向(插入物的主面中的旋转方向)或对于插入物的主面的Z方向(插入物的安装高度方向)上产生制造偏差(插入物12的配置位置的偏差)的情况的插入物12的配置的数据。图4～图7中的一点划线示出插入物12的设计上的配置位置。
芯片粘接部5根据从输入控制部2输入的设计数据1和用插入物配置部4作成的数据，设想在插入物12上的半导体芯片11的配置中产生了制造偏差的情况，作成在模拟了插入物12上的制造偏差的发生的位置上配置半导体芯片11的情况的半导体芯片模拟配置数据。例如设图8中示出的半导体芯片11的配置位置为插入物12上的半导体芯片11的设计上的配置位置。在该情况下，在芯片粘接部5中，作成进行了例如如图9中所示对于插入物12上的半导体芯片11的设计上的配置位置在X方向(插入物的半导体芯片的配置面中的面内方向)上或例如如图10中所示在Y方向(插入物的半导体芯片的配置面中的面内方向)上产生制造偏差(插入物12上的半导体芯片11的配置位置的偏差)的情况的插入物12的配置的数据。
此外，在芯片粘接部5中，作成进行了例如如图11中所示对于插入物12上的半导体芯片11的设计上的配置位置在倾斜方向、即X方向和Y方向的两个方向上或例如如图12中所示在旋转方向(插入物的半导体芯片的配置面中的旋转方向)或对于插入物的主面的Z方向(插入物的厚度方向)的倾斜中产生制造偏差(插入物12上的半导体芯片11的配置位置的偏差)的情况的半导体芯片11的配置的数据。图9～图12中的一点划线示出半导体芯片11的设计上的配置位置。
在引线键合部6中，根据从输入控制部2输入的设计数据1和用芯片粘接部5作成的数据，作成对在从用芯片粘接部5作成的插入物12上的设计上的配置位置产生制造偏差的情况、即在模拟了插入物12上的制造偏差的发生的位置上配置半导体芯片11的情况的连接偏离设计上的配置位置而配置的半导体芯片11的键合焊盘14与插入物12的键合指15的键合引线13进行了布线的键合引线模拟数据。
设计规则测定部7实施关于用引线键合部6进行了布线的键合引线13的设计规则测定。即，设计规则测定部7测定键合引线13间的间隙、键合引线13与半导体芯片11的间隙、键合引线13与插入物12的间隙、键合引线13与键合焊盘14的间隙和键合引线13与键合指15的间隙。
数据分析部9以设计规则测定部7中的测定结果7a为输入，进行统计分析。例如关于满足设计规则的半导体芯片11的在插入物12上的配置位置的偏差的容许范围、满足设计规则的半导体芯片11的插入物12的键合引线连接端子位置的偏差的容许范围、偏差分布图、工序能力指数、标准偏差、分散、平均、合格品率/不合格率、SN比等进行数据分析部9中的分析。
接着，说明与上述那样的本实施形态有关的半导体器件的辅助设计装置的工作。首先，对输入控制部2输入插入物12的形状、半导体芯片11的形状、半导体芯片11的在插入物12上的配置位置、连接半导体芯片11与插入物12的键合引线13的形状、引线键合坐标等的关于半导体封装的设计数据1。输入控制部2接受这些关于半导体封装的设计数据1，对插入物配置部4输出该设计数据1。
在插入物配置部4中，如果从输入控制部2接受关于半导体封装的设计数据1，则根据该设计数据1设想在插入物12的配置中产生制造偏差的情况，作成在模拟了制造偏差的发生的位置上配置插入物12的情况的数据。然后，在插入物配置部4中，与关于半导体封装的设计数据1一起对引线键合部6输出已作成的数据。
在芯片粘接部5中，如果从插入物配置部4接受数据，则根据设计数据1和用插入物配置部4作成的数据，设想在插入物12上的半导体芯片11的配置中产生制造偏差的情况，作成在模拟了插入物12上的制造偏差的发生的位置上配置半导体芯片11的情况的半导体芯片模拟配置数据。然后，在芯片粘接部5中，与关于半导体封装的设计数据1一起对引线键合部6输出已作成的数据。
在此，在插入物配置部4中的制造偏差的发生方法中例如可使用2种方法。第1种方法是按照正规分布或一样分布等的偏差分布随机地发生制造偏差的方法。此外，第2种方法是按照实验计划法来发生制造偏差的方法。
在图13中示出按照以半导体芯片11的配置位置的横方向或纵方向或旋转方向或半导体芯片11的配置高度和半导体芯片11的倾斜为主要因素的实验计划法来发生制造偏差的方法。图13示出了表示主要因素及其水准的表16。在图13中，取半导体芯片11的配置位置的横方向、纵方向和高度方向作为主要因素，示出了将各自的主要因素取作3个水准的例子。此外，图14示出了将图13中的主要因素分配给L9正交表17的例子。再有，在本发明中，可任意地选择主要因素的数目和水准，分配主要因素的正交表不限于图14中示出的L9正交表17，可选择任意的正交表。通过使用这样的正交表，可检验设计时的最佳条件的选择的错误，可防止错误的检验结果、条件选择流到后面的工序中，可进行高品质的设计。
接着，在引线键合部6中，根据设计数据1和用芯片粘接部5作成的数据，作成对在模拟了插入物12上的制造偏差的发生的位置上配置半导体芯片11的情况的连接半导体芯片11的键合焊盘14与插入物12的键合指15的键合引线13进行了布线的键合引线模拟数据。然后，引线键合部6与关于半导体封装的设计数据1一起对设计规则测定部7输出已作成的数据。
然后，在设计规则测定部7中，根据从引线键合部6输入的数据，实施关于用引线键合部6进行了布线的键合引线13的设计规则测定。对于键合引线13间的间隙、键合引线13与半导体芯片11的间隙、键合引线13与插入物12的间隙、键合引线13与键合焊盘14的间隙和键合引线13与键合指15的间隙进行设计规则测定。然后，在设计规则测定部7中，在测定结束后，将该测定结果7a作为测定结果与关于半导体封装的设计数据1一起输出给存储部8。在存储部8中，与关于半导体封装的设计数据1一起存储从设计规则测定部7输入的测定结果7a。
然后，以规定的次数重复在上述示出的装配部3、设计规则测定部7和存储部8中的处理。在数据分析部9中进行设计规则测定部7中的测定结果的分析，输出分析结果9a。在使用图14中示出的L9正交表17发生制造偏差的例子中，合计重复9次装配部3、设计规则测定部7和存储部8中的处理。
接着，在数据分析部9中，如图15中所示，以存储部8中存储的设计规则测定部7中的测定结果7a作为输入，进行统计分析。例如对于偏差的容许范围、即满足设计规则的半导体芯片11的在插入物12上的配置位置的偏差的容许范围、满足设计规则的半导体芯片11的插入物12的键合引线连接端子位置的偏差的容许范围、偏差分布图、工序能力指数、标准偏差、分散、平均、合格品率/不合格率、SN比等进行数据分析部9中的分析。然后，将这些分析结果9a输出给存储部8。在存储部8中，存储从数据分析部9输入的分析结果9a。此外，在数据分析部9中，也可将这些分析结果9a输出给外部。
这样，在本实施形态中，通过在数据分析部9中进行上述那样的分析，进行考虑了半导体器件的制造工序中的制造偏差的设计规则检验。即，通过分析、验证模拟设计数据，事先检测起因于半导体芯片的在插入物上的配置位置的偏差和插入物的键合引线连接端子位置的偏差的半导体器件的制造中的不良情况。具体地说，可在半导体器件的设计阶段中检测在半导体器件的制造时键合引线相互间的接触或键合引线与插入物的接触等的关于键合引线的不良情况。
由此，在半导体器件的设计阶段中检测关于键合引线的不良情况的情况下，可在设计阶段中修正这些不良情况以便能再次设计正常的半导体器件。因而，按照该半导体器件的辅助设计装置，可避免在半导体器件的制造时的键合引线相互间的接触等的关于键合引线的不良情况以提高制品成品率，可得到能进行制品成品率良好的半导体器件的制造的半导体器件的辅助设计装置。
再有，本发明不限定于上述那样的半导体封装的设计，可广泛地应用于将半导体芯片直接安装在功率模块或印刷基板上的情况。
产业上利用的可能性
如上所述，与本发明有关的半导体器件的辅助设计装置在半导体器件的设计中是有用的，特别是适合于由于进一步的微细化而有可能产生键合引线的不良情况的半导体器件的制造。

Claims (10)

1.一种半导体器件的辅助设计装置，辅助连接半导体芯片与插入物的键合引线的布线设计，其特征在于，具备：
作成模拟了半导体芯片的在插入物上的配置位置偏差的发生和插入物的键合引线连接端子位置偏差的发生的模拟设计数据的单元；以及
根据上述模拟设计数据来分析起因于上述半导体芯片的在插入物上的配置位置的偏差和上述插入物的键合引线连接端子位置的偏差的半导体器件的制造中的不良情况的分析单元。
2.如权利要求1中所述的半导体器件的辅助设计装置，辅助连接半导体芯片与插入物的键合引线的布线设计，其特征在于，具备：
作成模拟了半导体芯片的在插入物上的配置位置偏差的发生和插入物的键合引线连接端子位置偏差的发生的模拟设计数据的单元；以及
根据上述模拟设计数据来分析上述半导体芯片的在插入物上的配置位置偏差的容许范围和上述插入物的键合引线连接端子位置偏差的容许范围的分析单元。
3.一种半导体器件的辅助设计装置，其特征在于，具备：
第1数据作成单元，根据半导体封装的设计数据来作成在模拟了在插入物上配置半导体芯片时的半导体芯片的配置位置偏差的位置上配置半导体芯片的半导体芯片模拟配置数据；
第2数据作成单元，根据上述半导体封装的设计数据和半导体芯片模拟配置数据来作成用键合引线对偏离上述设计数据中的配置位置而配置的半导体芯片的键合引线连接端子与上述插入物的键合引线连接端子之间进行了布线的键合引线模拟数据；
测定单元，从上述键合引线模拟数据来测定上述已布线的键合引线的设计规则；以及
分析单元，进行上述测定单元中的测定结果的分析。
4.如权利要求3中所述的半导体器件的辅助设计装置，其特征在于：
使用上述插入物的形状、上述半导体芯片的形状、上述半导体芯片在上述插入物上的配置位置、连接上述半导体芯片与上述插入物的键合引线的形状和连接上述半导体芯片与上述插入物的键合引线的配置位置作为上述半导体封装的设计数据。
5.如权利要求4中所述的半导体器件的辅助设计装置，其特征在于：
第1数据作成单元对于上述半导体封装的设计数据中的在上述插入物上的上述半导体芯片的配置位置作成在模拟了上述插入物的半导体芯片配置面中的面内方向或旋转方向上的上述半导体芯片的配置位置偏差或上述插入物的厚度方向上的上述半导体芯片的倾斜的偏差的位置上配置半导体芯片的半导体芯片模拟配置数据。
6.如权利要求3中所述的半导体器件的辅助设计装置，其特征在于：
上述测定单元测定上述键合引线间的间隙、上述键合引线与上述半导体芯片的间隙来作为上述已布线的键合引线的设计规则。
7.如权利要求6中所述的半导体器件的辅助设计装置，其特征在于：
上述分析单元分析满足设计规则的上述半导体芯片的在上述插入物上的配置位置偏差的容许范围。
8.如权利要求6中所述的半导体器件的辅助设计装置，其特征在于：
上述分析单元分析满足设计规则的上述插入物的键合引线连接端子位置偏差的容许范围。
9.如权利要求3中所述的半导体器件的辅助设计装置，其特征在于：
具备存储上述测定单元中的测定结果的存储单元。
10.如权利要求3中所述的半导体器件的辅助设计装置，其特征在于：
具备存储上述分析单元中的分析结果的存储单元。
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US7725847B2 (en) 2010-05-25
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