CN100339997C - 含有非易失性存储器的半导体器件及其制造方法 - Google Patents

含有非易失性存储器的半导体器件及其制造方法 Download PDF

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Publication number
CN100339997C
CN100339997C CNB2004100037500A CN200410003750A CN100339997C CN 100339997 C CN100339997 C CN 100339997C CN B2004100037500 A CNB2004100037500 A CN B2004100037500A CN 200410003750 A CN200410003750 A CN 200410003750A CN 100339997 C CN100339997 C CN 100339997C
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China
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gate insulating
insulating film
film
gate electrode
electrode film
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Expired - Fee Related
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Chinese (zh)
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CN1577863A (zh
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竹渕政孝
荒井史隆
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Toshiba Corp
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Toshiba Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/49—Simultaneous manufacture of periphery and memory cells comprising different types of peripheral transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
    • H01L27/105—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including field-effect components
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/41—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region of a memory region comprising a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/46—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with an inter-gate dielectric layer also being used as part of the peripheral transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H10B41/42—Simultaneous manufacture of periphery and memory cells
    • H10B41/43—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor
    • H10B41/44—Simultaneous manufacture of periphery and memory cells comprising only one type of peripheral transistor with a control gate layer also being used as part of the peripheral transistor

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CNB2004100037500A 2003-06-30 2004-01-30 含有非易失性存储器的半导体器件及其制造方法 Expired - Fee Related CN100339997C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2003188889A JP2005026380A (ja) 2003-06-30 2003-06-30 不揮発性メモリを含む半導体装置及びその製造方法
JP188889/2003 2003-06-30

Publications (2)

Publication Number Publication Date
CN1577863A CN1577863A (zh) 2005-02-09
CN100339997C true CN100339997C (zh) 2007-09-26

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Country Status (6)

Country Link
US (4) US7023049B2 (ko)
EP (2) EP1494276A3 (ko)
JP (1) JP2005026380A (ko)
KR (1) KR100583708B1 (ko)
CN (1) CN100339997C (ko)
TW (1) TWI261897B (ko)

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US7183153B2 (en) * 2004-03-12 2007-02-27 Sandisk Corporation Method of manufacturing self aligned non-volatile memory cells
JP4040602B2 (ja) * 2004-05-14 2008-01-30 Ｎｅｃエレクトロニクス株式会社 半導体装置
JP4331070B2 (ja) * 2004-08-06 2009-09-16 株式会社東芝 半導体記憶装置
JP2006073939A (ja) * 2004-09-06 2006-03-16 Toshiba Corp 不揮発性半導体記憶装置及び不揮発性半導体記憶装置の製造方法
US7482223B2 (en) * 2004-12-22 2009-01-27 Sandisk Corporation Multi-thickness dielectric for semiconductor memory
US7202125B2 (en) * 2004-12-22 2007-04-10 Sandisk Corporation Low-voltage, multiple thin-gate oxide and low-resistance gate electrode
JP2006186073A (ja) * 2004-12-27 2006-07-13 Toshiba Corp 半導体装置およびその製造方法
JP2006253461A (ja) * 2005-03-11 2006-09-21 Toshiba Corp 半導体集積回路装置およびその製造方法
US7541240B2 (en) 2005-10-18 2009-06-02 Sandisk Corporation Integration process flow for flash devices with low gap fill aspect ratio
JP2007123526A (ja) * 2005-10-27 2007-05-17 Toshiba Corp 半導体装置及びその製造方法
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US8932925B1 (en) 2013-08-22 2015-01-13 Freescale Semiconductor, Inc. Split-gate non-volatile memory (NVM) cell and device structure integration
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KR20200140391A (ko) 2018-05-03 2020-12-15 램 리써치 코포레이션 3d nand 구조체들에 텅스텐 및 다른 금속들을 증착하는 방법
JP2022509621A (ja) * 2018-11-19 2022-01-21 ラム リサーチ コーポレーション タングステン用モリブデンテンプレート
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Also Published As

Publication number Publication date
US20080029806A1 (en) 2008-02-07
US7592667B2 (en) 2009-09-22
EP1494276A3 (en) 2009-06-24
EP1494276A2 (en) 2005-01-05
US7282413B2 (en) 2007-10-16
KR100583708B1 (ko) 2006-05-26
TWI261897B (en) 2006-09-11
US20090283815A1 (en) 2009-11-19
US20040262670A1 (en) 2004-12-30
CN1577863A (zh) 2005-02-09
US20060102950A1 (en) 2006-05-18
JP2005026380A (ja) 2005-01-27
TW200507189A (en) 2005-02-16
US7948023B2 (en) 2011-05-24
EP2346076A2 (en) 2011-07-20
EP2346076A3 (en) 2017-05-03
US7023049B2 (en) 2006-04-04
KR20050004681A (ko) 2005-01-12

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