CH559430A5 - - Google Patents

Info

Publication number
CH559430A5
CH559430A5 CH213574A CH213574A CH559430A5 CH 559430 A5 CH559430 A5 CH 559430A5 CH 213574 A CH213574 A CH 213574A CH 213574 A CH213574 A CH 213574A CH 559430 A5 CH559430 A5 CH 559430A5
Authority
CH
Switzerland
Application number
CH213574A
Original Assignee
Ibm
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ibm filed Critical Ibm
Publication of CH559430A5 publication Critical patent/CH559430A5/xx

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/535—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including internal interconnections, e.g. cross-under constructions
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76278—Vertical isolation by selective deposition of single crystal silicon, i.e. SEG techniques
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/051—Etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/053—Field effect transistors fets
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/085—Isolated-integrated
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/117—Oxidation, selective
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/914—Doping
    • Y10S438/924—To facilitate selective etching
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/928—Front and rear surface processing

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Element Separation (AREA)
  • Bipolar Transistors (AREA)
  • Local Oxidation Of Silicon (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
CH213574A 1973-03-12 1974-02-15 CH559430A5 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/340,150 US3944447A (en) 1973-03-12 1973-03-12 Method for fabrication of integrated circuit structure with full dielectric isolation utilizing selective oxidation

Publications (1)

Publication Number Publication Date
CH559430A5 true CH559430A5 (de) 1975-02-28

Family

ID=23332104

Family Applications (1)

Application Number Title Priority Date Filing Date
CH213574A CH559430A5 (de) 1973-03-12 1974-02-15

Country Status (14)

Country Link
US (1) US3944447A (de)
JP (2) JPS5544454B2 (de)
AU (1) AU6613374A (de)
BE (1) BE811197A (de)
BR (1) BR7401876D0 (de)
CA (1) CA1005931A (de)
CH (1) CH559430A5 (de)
DE (1) DE2410786C3 (de)
ES (1) ES423968A1 (de)
FR (1) FR2221814B1 (de)
GB (1) GB1442726A (de)
IT (1) IT1009579B (de)
NL (1) NL7402623A (de)
SE (1) SE406664B (de)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5252582A (en) * 1975-10-25 1977-04-27 Toshiba Corp Device and production for semiconductor
JPS5261973A (en) * 1975-11-18 1977-05-21 Mitsubishi Electric Corp Production of semiconductor device
JPS5344681U (de) * 1976-09-20 1978-04-17
JPS5344680U (de) * 1976-09-20 1978-04-17
US4131910A (en) * 1977-11-09 1978-12-26 Bell Telephone Laboratories, Incorporated High voltage semiconductor devices
US4232328A (en) * 1978-12-20 1980-11-04 Bell Telephone Laboratories, Incorporated Dielectrically-isolated integrated circuit complementary transistors for high voltage use
JPS56150759U (de) * 1980-04-10 1981-11-12
US4487639A (en) * 1980-09-26 1984-12-11 Texas Instruments Incorporated Localized epitaxy for VLSI devices
JPS57100670A (en) * 1980-12-16 1982-06-22 Victor Co Of Japan Ltd Tape recorder
US4599792A (en) * 1984-06-15 1986-07-15 International Business Machines Corporation Buried field shield for an integrated circuit
JPH0671043B2 (ja) * 1984-08-31 1994-09-07 株式会社東芝 シリコン結晶体構造の製造方法
JPS6173345A (ja) * 1984-09-19 1986-04-15 Toshiba Corp 半導体装置
US4897698A (en) * 1984-10-31 1990-01-30 Texas Instruments Incorporated Horizontal structure thin film transistor
JPS633024A (ja) * 1986-06-20 1988-01-08 Kanegafuchi Chem Ind Co Ltd イオン結合を含む高分子化合物
US4810667A (en) * 1987-04-28 1989-03-07 Texas Instruments Incorporated Dielectric isolation using isolated silicon by limited anodization of an N+ epitaxially defined sublayer in the presence of a diffusion under film layer
US4889832A (en) * 1987-12-23 1989-12-26 Texas Instruments Incorporated Method of fabricating an integrated circuit with metal interconnecting layers above and below active circuitry
KR0133730B1 (ko) * 1988-11-21 1998-04-23 Pulse Microwave M 링 쿼드에 있어서 쇼트키-배리어 다이오드 용 빔리드
US5280194A (en) * 1988-11-21 1994-01-18 Micro Technology Partners Electrical apparatus with a metallic layer coupled to a lower region of a substrate and metallic layer coupled to a lower region of a semiconductor device
KR100292851B1 (ko) * 1991-09-27 2001-09-17 스콧 티. 마이쿠엔 높은얼리전압,고주파성능및고항복전압특성을구비한상보형바이폴라트랜지스터및그제조방법
US5521420A (en) * 1992-05-27 1996-05-28 Micro Technology Partners Fabricating a semiconductor with an insulative coating
US5403729A (en) * 1992-05-27 1995-04-04 Micro Technology Partners Fabricating a semiconductor with an insulative coating
US5488012A (en) * 1993-10-18 1996-01-30 The Regents Of The University Of California Silicon on insulator with active buried regions
US5656547A (en) * 1994-05-11 1997-08-12 Chipscale, Inc. Method for making a leadless surface mounted device with wrap-around flange interface contacts
JPH10508430A (ja) * 1994-06-09 1998-08-18 チップスケール・インコーポレーテッド 抵抗器の製造
US5920779A (en) * 1997-05-21 1999-07-06 United Microelectronics Corp. Differential gate oxide thickness by nitrogen implantation for mixed mode and embedded VLSI circuits
US6143646A (en) * 1997-06-03 2000-11-07 Motorola Inc. Dual in-laid integrated circuit structure with selectively positioned low-K dielectric isolation and method of formation
DE10150040A1 (de) * 2001-10-10 2003-04-17 Merck Patent Gmbh Kombinierte Ätz- und Dotiermedien
US7465903B2 (en) * 2003-11-05 2008-12-16 Avago Technologies Fiber Ip (Singapore) Pte. Ltd. Use of mesa structures for supporting heaters on an integrated circuit
JP2009005754A (ja) * 2007-06-26 2009-01-15 Daito Giken:Kk 遊技台
US10295591B2 (en) * 2013-01-02 2019-05-21 Texas Instruments Incorporated Method and device for testing wafers

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3423255A (en) * 1965-03-31 1969-01-21 Westinghouse Electric Corp Semiconductor integrated circuits and method of making the same
US3534234A (en) * 1966-12-15 1970-10-13 Texas Instruments Inc Modified planar process for making semiconductor devices having ultrafine mesa type geometry
NL6706735A (de) * 1967-05-13 1968-11-14
NL158024B (nl) * 1967-05-13 1978-09-15 Philips Nv Werkwijze ter vervaardiging van een halfgeleiderinrichting en halfgeleiderinrichting verkregen door toepassing van de werkwijze.
US3640806A (en) * 1970-01-05 1972-02-08 Nippon Telegraph & Telephone Semiconductor device and method of producing the same

Also Published As

Publication number Publication date
JPS49122978A (de) 1974-11-25
JPS5340875B2 (de) 1978-10-30
JPS5344187A (en) 1978-04-20
FR2221814A1 (de) 1974-10-11
AU6613374A (en) 1975-08-28
JPS5544454B2 (de) 1980-11-12
DE2410786A1 (de) 1974-09-26
DE2410786B2 (de) 1978-10-26
US3944447A (en) 1976-03-16
CA1005931A (en) 1977-02-22
FR2221814B1 (de) 1977-09-09
SE406664B (sv) 1979-02-19
GB1442726A (en) 1976-07-14
DE2410786C3 (de) 1979-06-28
BR7401876D0 (pt) 1974-12-03
NL7402623A (de) 1974-09-16
ES423968A1 (es) 1976-05-01
BE811197A (fr) 1974-06-17
IT1009579B (it) 1976-12-20

Similar Documents

Publication Publication Date Title
AU476761B2 (de)
AU474593B2 (de)
AU474511B2 (de)
FR2221814B1 (de)
AU474838B2 (de)
AU465453B2 (de)
AU471343B2 (de)
AU476714B2 (de)
AU476696B2 (de)
AU472848B2 (de)
AU466283B2 (de)
AU477823B2 (de)
AU471461B2 (de)
AR210729A1 (de)
AU476873B1 (de)
AU447540B2 (de)
AU477824B2 (de)
AU1891376A (de)
AU5288673A (de)
BG20397A3 (de)
BG19015A1 (de)
AU479453A (de)
AU479496A (de)
AU479422A (de)
AU479420A (de)

Legal Events

Date Code Title Description
PL Patent ceased