CH450556A - Verfahren zum Erzeugen von elektrischen Nebenschlüssen zum Überbrücken von pn-Übergängen in Halbleiterkörpern - Google Patents

Verfahren zum Erzeugen von elektrischen Nebenschlüssen zum Überbrücken von pn-Übergängen in Halbleiterkörpern

Info

Publication number
CH450556A
CH450556A CH102267A CH102267A CH450556A CH 450556 A CH450556 A CH 450556A CH 102267 A CH102267 A CH 102267A CH 102267 A CH102267 A CH 102267A CH 450556 A CH450556 A CH 450556A
Authority
CH
Switzerland
Prior art keywords
junctions
bridging
generating electrical
semiconductor bodies
electrical shunts
Prior art date
Application number
CH102267A
Other languages
German (de)
English (en)
Inventor
Kurt Dr Raithel
Rosenheinrich Rene
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH450556A publication Critical patent/CH450556A/de

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304—Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3046—Mechanical treatment, e.g. grinding, polishing, cutting using blasting, e.g. sand-blasting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3081—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their composition, e.g. multilayer masks, materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/106—Masks, special

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Thyristors (AREA)
CH102267A 1966-02-12 1967-01-23 Verfahren zum Erzeugen von elektrischen Nebenschlüssen zum Überbrücken von pn-Übergängen in Halbleiterkörpern CH450556A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DES0101984 1966-02-12

Publications (1)

Publication Number Publication Date
CH450556A true CH450556A (de) 1968-01-31

Family

ID=7524118

Family Applications (1)

Application Number Title Priority Date Filing Date
CH102267A CH450556A (de) 1966-02-12 1967-01-23 Verfahren zum Erzeugen von elektrischen Nebenschlüssen zum Überbrücken von pn-Übergängen in Halbleiterkörpern

Country Status (8)

Country Link
US (1) US3589937A (US07655688-20100202-C00109.png)
BE (1) BE693884A (US07655688-20100202-C00109.png)
CH (1) CH450556A (US07655688-20100202-C00109.png)
DE (1) DE1514683B1 (US07655688-20100202-C00109.png)
FR (1) FR1511259A (US07655688-20100202-C00109.png)
GB (1) GB1107497A (US07655688-20100202-C00109.png)
NL (1) NL6701904A (US07655688-20100202-C00109.png)
SE (1) SE319838B (US07655688-20100202-C00109.png)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4079406A (en) * 1974-08-13 1978-03-14 Siemens Aktiengesellschaft Thyristor having a plurality of emitter shorts in defined spacial relationship
DE3744308A1 (de) * 1987-12-28 1989-07-06 Bbc Brown Boveri & Cie Leistungshalbleiter-bauelement sowie verfahren zu dessen herstellung

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE966879C (de) * 1953-02-21 1957-09-12 Standard Elektrik Ag Verfahren zur Reinigung und/oder Abtragung von Halbleitermaterial, insbesondere von Germanium- und Siliziumsubstanz
DE1152293B (de) * 1958-08-12 1963-08-01 Siemens Ag Verfahren zum oertlich begrenzten AEtzen von pn-UEbergaengen benachbarten Flaechen an Halbleiterkoerpern von elektrischen Halbleiteranordnungen
DE1132405B (de) * 1960-11-04 1962-06-28 Siemens Ag Verfahren zum lokalisierten AEtzen der Oberflaeche von Werkstuecken, insbesondere von Halbleiterkristallen

Also Published As

Publication number Publication date
DE1514683B1 (de) 1970-04-02
GB1107497A (en) 1968-03-27
SE319838B (US07655688-20100202-C00109.png) 1970-01-26
FR1511259A (fr) 1968-01-26
BE693884A (US07655688-20100202-C00109.png) 1967-08-09
NL6701904A (US07655688-20100202-C00109.png) 1967-08-14
US3589937A (en) 1971-06-29

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