CH445649A - Verfahren zum Herstellen von Halbleiterschaltungen - Google Patents

Verfahren zum Herstellen von Halbleiterschaltungen

Info

Publication number
CH445649A
CH445649A CH600466A CH600466A CH445649A CH 445649 A CH445649 A CH 445649A CH 600466 A CH600466 A CH 600466A CH 600466 A CH600466 A CH 600466A CH 445649 A CH445649 A CH 445649A
Authority
CH
Switzerland
Prior art keywords
manufacturing semiconductor
semiconductor circuits
circuits
manufacturing
semiconductor
Prior art date
Application number
CH600466A
Other languages
English (en)
Inventor
Heinz Dr Dorendorf
Original Assignee
Siemens Ag
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens Ag filed Critical Siemens Ag
Publication of CH445649A publication Critical patent/CH445649A/de

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495Lead-frames or other flat leads
    • H01L23/49575Assemblies of semiconductor devices on lead frames
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56Encapsulations, e.g. encapsulation layers, coatings
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • H01L23/295Organic, e.g. plastic containing a filler
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/051Etching
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00Metal treatment
    • Y10S148/085Isolated-integrated
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/49002Electrical device making
    • Y10T29/49117Conductor or circuit manufacturing
    • Y10T29/49124On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/4913Assembling to base an electrical component, e.g., capacitor, etc.
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10TTECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00Metal working
    • Y10T29/49Method of mechanical manufacture
    • Y10T29/4981Utilizing transitory attached element or associated separate material

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Weting (AREA)
  • Element Separation (AREA)
CH600466A 1965-04-26 1966-04-25 Verfahren zum Herstellen von Halbleiterschaltungen CH445649A (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DES0096768 1965-04-26

Publications (1)

Publication Number Publication Date
CH445649A true CH445649A (de) 1967-10-31

Family

ID=7520280

Family Applications (1)

Application Number Title Priority Date Filing Date
CH600466A CH445649A (de) 1965-04-26 1966-04-25 Verfahren zum Herstellen von Halbleiterschaltungen

Country Status (7)

Country Link
US (1) US3494023A (de)
AT (1) AT263083B (de)
CH (1) CH445649A (de)
DE (1) DE1514453A1 (de)
GB (1) GB1101906A (de)
NL (1) NL6605366A (de)
SE (1) SE315951B (de)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3654000A (en) * 1969-04-18 1972-04-04 Hughes Aircraft Co Separating and maintaining original dice position in a wafer
US3810300A (en) * 1969-05-20 1974-05-14 Ferranti Ltd Electrical circuit assemblies
US3679941A (en) * 1969-09-22 1972-07-25 Gen Electric Composite integrated circuits including semiconductor chips mounted on a common substrate with connections made through a dielectric encapsulator
GB1335201A (en) * 1970-05-21 1973-10-24 Lucas Industries Ltd Method of manufacturing semi-conductor devices
US3770531A (en) * 1972-05-04 1973-11-06 Bell Telephone Labor Inc Bonding substance for the fabrication of integrated circuits
US3839783A (en) * 1972-07-12 1974-10-08 Rodan Ind Inc Thermistor manufacturing method
NL7215200A (de) * 1972-11-10 1974-05-14
US4504427A (en) * 1983-06-17 1985-03-12 At&T Bell Laboratories Solder preform stabilization for lead frames
US6173490B1 (en) * 1997-08-20 2001-01-16 National Semiconductor Corporation Method for forming a panel of packaged integrated circuits
US6582990B2 (en) * 2001-08-24 2003-06-24 International Rectifier Corporation Wafer level underfill and interconnect process
WO2009138990A1 (en) * 2008-05-15 2009-11-19 Pythagoras Solar Inc. Encapsulation material

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3076051A (en) * 1959-03-05 1963-01-29 Rca Corp Thermoelectric devices and methods of making same
US3158788A (en) * 1960-08-15 1964-11-24 Fairchild Camera Instr Co Solid-state circuitry having discrete regions of semi-conductor material isolated by an insulating material
US3271625A (en) * 1962-08-01 1966-09-06 Signetics Corp Electronic package assembly
US3307239A (en) * 1964-02-18 1967-03-07 Bell Telephone Labor Inc Method of making integrated semiconductor devices

Also Published As

Publication number Publication date
AT263083B (de) 1968-07-10
SE315951B (de) 1969-10-13
NL6605366A (de) 1966-10-27
US3494023A (en) 1970-02-10
GB1101906A (en) 1968-02-07
DE1514453A1 (de) 1969-08-14

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