CA994924A - Process for the elimination of interface states in mios structures - Google Patents

Process for the elimination of interface states in mios structures

Info

Publication number
CA994924A
CA994924A CA201,981A CA201981A CA994924A CA 994924 A CA994924 A CA 994924A CA 201981 A CA201981 A CA 201981A CA 994924 A CA994924 A CA 994924A
Authority
CA
Canada
Prior art keywords
mios
elimination
structures
interface states
states
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA201,981A
Other languages
English (en)
Other versions
CA201981S (en
Inventor
Alan B. Fowler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA994924A publication Critical patent/CA994924A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/024—Defect control-gettering and annealing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/91—Controlling charging state at semiconductor-insulator interface

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Computer Hardware Design (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Manufacturing & Machinery (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Formation Of Insulating Films (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
CA201,981A 1973-06-29 1974-06-07 Process for the elimination of interface states in mios structures Expired CA994924A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US00375283A US3849204A (en) 1973-06-29 1973-06-29 Process for the elimination of interface states in mios structures

Publications (1)

Publication Number Publication Date
CA994924A true CA994924A (en) 1976-08-10

Family

ID=23480255

Family Applications (1)

Application Number Title Priority Date Filing Date
CA201,981A Expired CA994924A (en) 1973-06-29 1974-06-07 Process for the elimination of interface states in mios structures

Country Status (5)

Country Link
US (1) US3849204A (ja)
JP (1) JPS5433917B2 (ja)
CA (1) CA994924A (ja)
DE (1) DE2422195C2 (ja)
GB (1) GB1454237A (ja)

Families Citing this family (30)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3923559A (en) * 1975-01-13 1975-12-02 Bell Telephone Labor Inc Use of trapped hydrogen for annealing metal-oxide-semiconductor devices
DE2507366C3 (de) * 1975-02-20 1980-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Unterdrückung parasitärer Schaltungselemente
US4047976A (en) * 1976-06-21 1977-09-13 Motorola, Inc. Method for manufacturing a high-speed semiconductor device
US4364779A (en) * 1980-08-04 1982-12-21 Bell Telephone Laboratories, Incorporated Fabrication of semiconductor devices including double annealing steps for radiation hardening
US4447272A (en) * 1982-11-22 1984-05-08 The United States Of America As Represented By The Secretary Of The Navy Method for fabricating MNOS structures utilizing hydrogen ion implantation
US4522657A (en) * 1983-10-20 1985-06-11 Westinghouse Electric Corp. Low temperature process for annealing shallow implanted N+/P junctions
JPH0687503B2 (ja) * 1987-03-11 1994-11-02 株式会社日立製作所 薄膜半導体装置
JP2589327B2 (ja) * 1987-11-14 1997-03-12 株式会社リコー 薄膜トランジスタの製造方法
JPH02218132A (ja) * 1989-02-20 1990-08-30 Nec Corp 半導体装置の製造方法
DE4306565C2 (de) * 1993-03-03 1995-09-28 Telefunken Microelectron Verfahren zur Herstellung eines blauempfindlichen Photodetektors
US5407850A (en) * 1993-06-29 1995-04-18 Digital Equipment Corporation SOI transistor threshold optimization by use of gate oxide having positive charge
US5387530A (en) * 1993-06-29 1995-02-07 Digital Equipment Corporation Threshold optimization for soi transistors through use of negative charge in the gate oxide
JPH07153769A (ja) * 1993-11-30 1995-06-16 Hitachi Ltd 半導体集積回路装置の製造方法および製造装置
US5897346A (en) * 1994-02-28 1999-04-27 Semiconductor Energy Laboratory Co., Ltd. Method for producing a thin film transistor
US5620906A (en) * 1994-02-28 1997-04-15 Semiconductor Energy Laboratory Co., Ltd. Method for producing semiconductor device by introducing hydrogen ions
US6489219B1 (en) * 1995-11-09 2002-12-03 Micron Technology, Inc. Method of alloying a semiconductor device
US20020031920A1 (en) 1996-01-16 2002-03-14 Lyding Joseph W. Deuterium treatment of semiconductor devices
US5872387A (en) * 1996-01-16 1999-02-16 The Board Of Trustees Of The University Of Illinois Deuterium-treated semiconductor devices
JP3865145B2 (ja) * 1996-01-26 2007-01-10 株式会社半導体エネルギー研究所 半導体装置の作製方法
US5744202A (en) * 1996-09-30 1998-04-28 Xerox Corporation Enhancement of hydrogenation of materials encapsulated by an oxide
US6071751A (en) * 1997-04-28 2000-06-06 Texas Instruments Incorporated Deuterium sintering with rapid quenching
US6328801B1 (en) 1997-07-25 2001-12-11 L'air Liquide, Societe Anonyme Pour L'etude Et L'exploitation Des Procedes Georges Claude Method and system for recovering and recirculating a deuterium-containing gas
US6143631A (en) 1998-05-04 2000-11-07 Micron Technology, Inc. Method for controlling the morphology of deposited silicon on a silicon dioxide substrate and semiconductor devices incorporating such deposited silicon
FR2784796B1 (fr) * 1998-10-15 2001-11-23 Commissariat Energie Atomique Procede de realisation d'une couche de materiau enterree dans un autre materiau
US6268269B1 (en) * 1999-12-30 2001-07-31 United Microelectronics Corp. Method for fabricating an oxide layer on silicon with carbon ions introduced at the silicon/oxide interface in order to reduce hot carrier effects
US6576522B2 (en) 2000-12-08 2003-06-10 Agere Systems Inc. Methods for deuterium sintering
US6603181B2 (en) * 2001-01-16 2003-08-05 International Business Machines Corporation MOS device having a passivated semiconductor-dielectric interface
DE10334353A1 (de) * 2003-07-25 2005-02-17 Forschungszentrum Jülich GmbH Verfahren zur Herstellung eines Kontaktes und elektronisches Bauelement, umfassend derartige Kontakte
US7407871B2 (en) * 2006-09-05 2008-08-05 Tech Semiconductor Singapore Pte Ltd Method for passivation of plasma etch defects in DRAM devices
KR20100060652A (ko) * 2008-11-28 2010-06-07 주식회사 동부하이텍 반도체 소자의 제조 방법

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1095412A (ja) * 1964-08-26
US3540925A (en) * 1967-08-02 1970-11-17 Rca Corp Ion bombardment of insulated gate semiconductor devices
US3513035A (en) * 1967-11-01 1970-05-19 Fairchild Camera Instr Co Semiconductor device process for reducing surface recombination velocity
US3590477A (en) * 1968-12-19 1971-07-06 Ibm Method for fabricating insulated-gate field effect transistors having controlled operating characeristics
DE2056947C3 (de) * 1970-11-20 1975-12-18 Fraunhofer-Gesellschaft Zur Foerderung Der Angewandten Forschung E.V., 8000 Muenchen Verfahren zur Stabilisierung von Halbleiteranordnungen

Also Published As

Publication number Publication date
JPS5433917B2 (ja) 1979-10-23
DE2422195C2 (de) 1986-02-06
JPS516679A (ja) 1976-01-20
GB1454237A (en) 1976-11-03
DE2422195A1 (de) 1975-01-16
US3849204A (en) 1974-11-19

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