CA970478A - Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, and semiconductor devices manufactured in this manner - Google Patents
Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, and semiconductor devices manufactured in this mannerInfo
- Publication number
- CA970478A CA970478A CA167,713A CA167713A CA970478A CA 970478 A CA970478 A CA 970478A CA 167713 A CA167713 A CA 167713A CA 970478 A CA970478 A CA 970478A
- Authority
- CA
- Canada
- Prior art keywords
- semiconductor devices
- silicon
- inset
- manner
- oxide regions
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title 2
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical group O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 title 1
- 238000004519 manufacturing process Methods 0.000 title 1
- 230000000873 masking effect Effects 0.000 title 1
- 230000003647 oxidation Effects 0.000 title 1
- 238000007254 oxidation reaction Methods 0.000 title 1
- 229910052710 silicon Inorganic materials 0.000 title 1
- 239000010703 silicon Substances 0.000 title 1
- 229910052814 silicon oxide Inorganic materials 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76213—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose
- H01L21/76216—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO introducing electrical inactive or active impurities in the local oxidation region, e.g. to alter LOCOS oxide growth characteristics or for additional isolation purpose introducing electrical active impurities in the local oxidation region for the sole purpose of creating channel stoppers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/32—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers using masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
- H01L21/76205—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO in a region being recessed from the surface, e.g. in a recess, groove, tub or trench region
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
- H01L23/291—Oxides or nitrides or carbides, e.g. ceramics, glass
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/037—Diffusion-deposition
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/043—Dual dielectric
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/085—Isolated-integrated
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/114—Nitrides of silicon
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/122—Polycrystalline
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/151—Simultaneous diffusion
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Ceramic Engineering (AREA)
- Element Separation (AREA)
- Bipolar Transistors (AREA)
- Local Oxidation Of Silicon (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
NL7204741A NL7204741A (fr) | 1972-04-08 | 1972-04-08 |
Publications (1)
Publication Number | Publication Date |
---|---|
CA970478A true CA970478A (en) | 1975-07-01 |
Family
ID=19815806
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CA167,713A Expired CA970478A (en) | 1972-04-08 | 1973-04-02 | Method of manufacturing semiconductor devices in which silicon oxide regions inset in silicon are formed by a masking oxidation, and semiconductor devices manufactured in this manner |
Country Status (8)
Country | Link |
---|---|
US (1) | US3900350A (fr) |
JP (1) | JPS5212070B2 (fr) |
AU (1) | AU463001B2 (fr) |
CA (1) | CA970478A (fr) |
FR (1) | FR2179864B1 (fr) |
GB (1) | GB1421212A (fr) |
IT (1) | IT980775B (fr) |
NL (1) | NL7204741A (fr) |
Families Citing this family (33)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2409910C3 (de) * | 1974-03-01 | 1979-03-15 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Verfahren zum Herstellen einer Halbleiteranordnung |
JPS5824951B2 (ja) * | 1974-10-09 | 1983-05-24 | ソニー株式会社 | コウガクソウチ |
JPS6022497B2 (ja) * | 1974-10-26 | 1985-06-03 | ソニー株式会社 | 半導体装置 |
JPS5187979A (ja) * | 1975-01-31 | 1976-07-31 | Hitachi Ltd | Bunryosankabutsuryoikiojusuru handotaisochinoseizohoho |
JPS5197385A (en) * | 1975-02-21 | 1976-08-26 | Handotaisochino seizohoho | |
US4044454A (en) * | 1975-04-16 | 1977-08-30 | Ibm Corporation | Method for forming integrated circuit regions defined by recessed dielectric isolation |
US3961999A (en) * | 1975-06-30 | 1976-06-08 | Ibm Corporation | Method for forming recessed dielectric isolation with a minimized "bird's beak" problem |
JPS5246784A (en) * | 1975-10-11 | 1977-04-13 | Hitachi Ltd | Process for production of semiconductor device |
JPS5253679A (en) * | 1975-10-29 | 1977-04-30 | Hitachi Ltd | Productin of semiconductor device |
JPS5261972A (en) * | 1975-11-18 | 1977-05-21 | Mitsubishi Electric Corp | Production of semiconductor device |
JPS5922381B2 (ja) * | 1975-12-03 | 1984-05-26 | 株式会社東芝 | ハンドウタイソシノ セイゾウホウホウ |
US4098618A (en) * | 1977-06-03 | 1978-07-04 | International Business Machines Corporation | Method of manufacturing semiconductor devices in which oxide regions are formed by an oxidation mask disposed directly on a substrate damaged by ion implantation |
US4401691A (en) * | 1978-12-18 | 1983-08-30 | Burroughs Corporation | Oxidation of silicon wafers to eliminate white ribbon |
US4269636A (en) * | 1978-12-29 | 1981-05-26 | Harris Corporation | Method of fabricating self-aligned bipolar transistor process and device utilizing etching and self-aligned masking |
JPS5645051A (en) * | 1979-09-20 | 1981-04-24 | Toshiba Corp | Manufacture of semiconductor device |
US4287661A (en) * | 1980-03-26 | 1981-09-08 | International Business Machines Corporation | Method for making an improved polysilicon conductor structure utilizing reactive-ion etching and thermal oxidation |
US4465705A (en) * | 1980-05-19 | 1984-08-14 | Matsushita Electric Industrial Co., Ltd. | Method of making semiconductor devices |
EP0048175B1 (fr) * | 1980-09-17 | 1986-04-23 | Hitachi, Ltd. | Dispositif semi-conducteur et procédé pour sa fabrication |
US4506435A (en) * | 1981-07-27 | 1985-03-26 | International Business Machines Corporation | Method for forming recessed isolated regions |
US4454647A (en) * | 1981-08-27 | 1984-06-19 | International Business Machines Corporation | Isolation for high density integrated circuits |
US4454646A (en) * | 1981-08-27 | 1984-06-19 | International Business Machines Corporation | Isolation for high density integrated circuits |
US4372033A (en) * | 1981-09-08 | 1983-02-08 | Ncr Corporation | Method of making coplanar MOS IC structures |
US4508757A (en) * | 1982-12-20 | 1985-04-02 | International Business Machines Corporation | Method of manufacturing a minimum bird's beak recessed oxide isolation structure |
JPS6054453A (ja) * | 1983-09-05 | 1985-03-28 | Oki Electric Ind Co Ltd | 半導体集積回路装置の製造方法 |
US4541167A (en) * | 1984-01-12 | 1985-09-17 | Texas Instruments Incorporated | Method for integrated circuit device isolation |
US4691222A (en) * | 1984-03-12 | 1987-09-01 | Harris Corporation | Method to reduce the height of the bird's head in oxide isolated processes |
US4612701A (en) * | 1984-03-12 | 1986-09-23 | Harris Corporation | Method to reduce the height of the bird's head in oxide isolated processes |
US4630356A (en) * | 1985-09-19 | 1986-12-23 | International Business Machines Corporation | Method of forming recessed oxide isolation with reduced steepness of the birds' neck |
US4824795A (en) * | 1985-12-19 | 1989-04-25 | Siliconix Incorporated | Method for obtaining regions of dielectrically isolated single crystal silicon |
JPS6410644A (en) * | 1987-07-02 | 1989-01-13 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
US5039625A (en) * | 1990-04-27 | 1991-08-13 | Mcnc | Maximum areal density recessed oxide isolation (MADROX) process |
KR960005556B1 (ko) * | 1993-04-24 | 1996-04-26 | 삼성전자주식회사 | 반도체장치의 소자분리방법 |
JP4746639B2 (ja) * | 2008-02-22 | 2011-08-10 | 株式会社東芝 | 半導体デバイス |
Family Cites Families (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB1147014A (en) * | 1967-01-27 | 1969-04-02 | Westinghouse Electric Corp | Improvements in diffusion masking |
NL169121C (nl) * | 1970-07-10 | 1982-06-01 | Philips Nv | Werkwijze voor het vervaardigen van een halfgeleiderinrichting met een halfgeleiderlichaam, dat aan een oppervlak is voorzien van een althans ten dele in het halfgeleiderlichaam verzonken, door thermische oxydatie gevormd oxydepatroon. |
US3719535A (en) * | 1970-12-21 | 1973-03-06 | Motorola Inc | Hyperfine geometry devices and method for their fabrication |
US3784847A (en) * | 1972-10-10 | 1974-01-08 | Gen Electric | Dielectric strip isolation for jfet or mesfet depletion-mode bucket-brigade circuit |
-
1972
- 1972-04-08 NL NL7204741A patent/NL7204741A/xx unknown
-
1973
- 1973-04-02 CA CA167,713A patent/CA970478A/en not_active Expired
- 1973-04-04 US US347806A patent/US3900350A/en not_active Expired - Lifetime
- 1973-04-04 AU AU54064/73A patent/AU463001B2/en not_active Expired
- 1973-04-05 GB GB1631073A patent/GB1421212A/en not_active Expired
- 1973-04-05 IT IT67984/73A patent/IT980775B/it active
- 1973-04-09 JP JP48039625A patent/JPS5212070B2/ja not_active Expired
- 1973-04-09 FR FR7312668A patent/FR2179864B1/fr not_active Expired
Also Published As
Publication number | Publication date |
---|---|
AU5406473A (en) | 1974-10-10 |
NL7204741A (fr) | 1973-10-10 |
JPS5212070B2 (fr) | 1977-04-04 |
JPS4917977A (fr) | 1974-02-16 |
DE2317087A1 (de) | 1973-10-18 |
IT980775B (it) | 1974-10-10 |
GB1421212A (en) | 1976-01-14 |
DE2317087B2 (de) | 1976-11-04 |
US3900350A (en) | 1975-08-19 |
FR2179864B1 (fr) | 1976-09-10 |
FR2179864A1 (fr) | 1973-11-23 |
AU463001B2 (en) | 1975-07-10 |
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