CA954231A - Memory control in a multiprocessing system utilizing a broadcast - Google Patents

Memory control in a multiprocessing system utilizing a broadcast

Info

Publication number
CA954231A
CA954231A CA143,833A CA143833A CA954231A CA 954231 A CA954231 A CA 954231A CA 143833 A CA143833 A CA 143833A CA 954231 A CA954231 A CA 954231A
Authority
CA
Canada
Prior art keywords
broadcast
memory control
system utilizing
multiprocessing system
multiprocessing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
CA143,833A
Other languages
English (en)
Other versions
CA143833S (en
Inventor
Robert P. Barner
John A. De Veer
Jan G. Oblonsky
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Application granted granted Critical
Publication of CA954231A publication Critical patent/CA954231A/en
Expired legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means
    • G06F12/0833Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means in combination with broadcast means (e.g. for invalidation or updating)
CA143,833A 1971-09-10 1972-06-05 Memory control in a multiprocessing system utilizing a broadcast Expired CA954231A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US17937671A 1971-09-10 1971-09-10

Publications (1)

Publication Number Publication Date
CA954231A true CA954231A (en) 1974-09-03

Family

ID=22656338

Family Applications (1)

Application Number Title Priority Date Filing Date
CA143,833A Expired CA954231A (en) 1971-09-10 1972-06-05 Memory control in a multiprocessing system utilizing a broadcast

Country Status (8)

Country Link
US (1) US3771137A (de)
JP (1) JPS5149535B2 (de)
CA (1) CA954231A (de)
DE (1) DE2226382C3 (de)
FR (1) FR2155203A5 (de)
GB (1) GB1387043A (de)
IT (1) IT953791B (de)
SE (1) SE426110B (de)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860379A (en) * 1979-05-18 1989-08-22 General Instrument Corporation Data communications system

Families Citing this family (120)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1354827A (en) * 1971-08-25 1974-06-05 Ibm Data processing systems
US3723976A (en) 1972-01-20 1973-03-27 Ibm Memory system with logical and real addressing
US4115866A (en) * 1972-02-25 1978-09-19 International Standard Electric Corporation Data processing network for communications switching system
IT988956B (it) * 1973-06-12 1975-04-30 Olivetti & Co Spa Governo multiplo
US3916384A (en) * 1973-06-15 1975-10-28 Gte Automatic Electric Lab Inc Communication switching system computer memory control arrangement
JPS546171B2 (de) * 1973-09-19 1979-03-26
US3940743A (en) * 1973-11-05 1976-02-24 Digital Equipment Corporation Interconnecting unit for independently operable data processing systems
US3889237A (en) * 1973-11-16 1975-06-10 Sperry Rand Corp Common storage controller for dual processor system
US3934227A (en) * 1973-12-05 1976-01-20 Digital Computer Controls, Inc. Memory correction system
NL7317545A (nl) * 1973-12-21 1975-06-24 Philips Nv Geheugensysteem met hoofd- en buffergeheugen.
US4073005A (en) * 1974-01-21 1978-02-07 Control Data Corporation Multi-processor computer system
JPS5440182B2 (de) * 1974-02-26 1979-12-01
JPS5812608B2 (ja) * 1974-03-05 1983-03-09 日本電気株式会社 デンシケイサンキシステム
GB1506972A (en) * 1976-02-06 1978-04-12 Int Computers Ltd Data processing systems
FR2344094A1 (fr) * 1976-03-10 1977-10-07 Cii Systeme de gestion coherente des echanges entre deux niveaux contigus d'une hierarchie de memoires
US4065809A (en) * 1976-05-27 1977-12-27 Tokyo Shibaura Electric Co., Ltd. Multi-processing system for controlling microcomputers and memories
GB1505603A (en) * 1976-07-07 1978-03-30 Ibm Data processing systems
US4126893A (en) * 1977-02-17 1978-11-21 Xerox Corporation Interrupt request controller for data processing system
US4157586A (en) * 1977-05-05 1979-06-05 International Business Machines Corporation Technique for performing partial stores in store-thru memory configuration
US4136386A (en) * 1977-10-06 1979-01-23 International Business Machines Corporation Backing store access coordination in a multi-processor system
US4142234A (en) * 1977-11-28 1979-02-27 International Business Machines Corporation Bias filter memory for filtering out unnecessary interrogations of cache directories in a multiprocessor system
US4357656A (en) * 1977-12-09 1982-11-02 Digital Equipment Corporation Method and apparatus for disabling and diagnosing cache memory storage locations
US4354232A (en) * 1977-12-16 1982-10-12 Honeywell Information Systems Inc. Cache memory command buffer circuit
JPS5849945B2 (ja) * 1977-12-29 1983-11-08 富士通株式会社 バツフア合せ方式
US4305124A (en) * 1978-06-09 1981-12-08 Ncr Corporation Pipelined computer
FR2430637A1 (fr) * 1978-07-06 1980-02-01 Cii Honeywell Bull Procede et dispositif pour garantir la coherence des informations entre des caches et d'autres memoires d'un systeme de traitement de l'information travaillant en multitraitement
FR2431733A1 (fr) * 1978-07-21 1980-02-15 Sfena Systeme de communication par memoire commune dans un calculateur comprenant plusieurs processeurs
US4228503A (en) * 1978-10-02 1980-10-14 Sperry Corporation Multiplexed directory for dedicated cache memory system
US4257097A (en) * 1978-12-11 1981-03-17 Bell Telephone Laboratories, Incorporated Multiprocessor system with demand assignable program paging stores
US4282572A (en) * 1979-01-15 1981-08-04 Ncr Corporation Multiprocessor memory access system
JPS55134459A (en) * 1979-04-06 1980-10-20 Hitachi Ltd Data processing system
US4293910A (en) * 1979-07-02 1981-10-06 International Business Machines Corporation Reconfigurable key-in-storage means for protecting interleaved main storage
DE2939412C2 (de) * 1979-09-28 1983-11-17 Siemens AG, 1000 Berlin und 8000 München Schaltungsanordung zum Adressieren von Daten für Lese- und Schreibzugriffe in einer Datenverarbeitungsanlage
US4313161A (en) * 1979-11-13 1982-01-26 International Business Machines Corporation Shared storage for multiple processor systems
JPS5680872A (en) * 1979-12-06 1981-07-02 Fujitsu Ltd Buffer memory control system
AU543278B2 (en) * 1979-12-14 1985-04-18 Honeywell Information Systems Incorp. Cache clearing in multiprocessor system
FR2474201B1 (fr) * 1980-01-22 1986-05-16 Bull Sa Procede et dispositif pour gerer les conflits poses par des acces multiples a un meme cache d'un systeme de traitement numerique de l'information comprenant au moins deux processus possedant chacun un cache
US4345309A (en) * 1980-01-28 1982-08-17 Digital Equipment Corporation Relating to cached multiprocessor system with pipeline timing
US4507781A (en) * 1980-03-14 1985-03-26 Ibm Corporation Time domain multiple access broadcasting, multipoint, and conferencing communication apparatus and method
DE3012205C2 (de) * 1980-03-28 1982-05-27 Siemens AG, 1000 Berlin und 8000 München Multiprozessor-Datenverarbeitungsanlage mit mehreren jeweils einem Prozessor zugeordneten Pufferspeichern
FR2479532B1 (fr) * 1980-04-01 1986-09-19 Bull Sa Procede et dispositif pour gerer les transferts d'informations entre un ensemble memoire et les differentes unites de traitement d'un systeme de traitement numerique de l'information
US4399506A (en) * 1980-10-06 1983-08-16 International Business Machines Corporation Store-in-cache processor means for clearing main storage
DE3177181D1 (de) * 1980-11-10 1990-06-21 Ibm Anordnung zur erkennung und verarbeitung von synonymen in cache-speichern.
US4394731A (en) * 1980-11-10 1983-07-19 International Business Machines Corporation Cache storage line shareability control for a multiprocessor system
JPS57105879A (en) * 1980-12-23 1982-07-01 Hitachi Ltd Control system for storage device
US4410944A (en) * 1981-03-24 1983-10-18 Burroughs Corporation Apparatus and method for maintaining cache memory integrity in a shared memory environment
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
US4945471A (en) * 1981-04-01 1990-07-31 Teradata Corporation Message transmission system for selectively transmitting one of two colliding messages based on contents thereof
US4814979A (en) * 1981-04-01 1989-03-21 Teradata Corporation Network to transmit prioritized subtask pockets to dedicated processors
US4539636A (en) * 1981-06-24 1985-09-03 Elevator Gmbh Apparatus for inter-processor data transfer in a multi-processor system
US4525777A (en) * 1981-08-03 1985-06-25 Honeywell Information Systems Inc. Split-cycle cache system with SCU controlled cache clearing during cache store access period
US4463420A (en) * 1982-02-23 1984-07-31 International Business Machines Corporation Multiprocessor cache replacement under task control
US4503497A (en) * 1982-05-27 1985-03-05 International Business Machines Corporation System for independent cache-to-cache transfer
JPS5955565A (ja) * 1982-09-24 1984-03-30 Fujitsu Ltd マルチフア−ムウエア方式
US4491915A (en) * 1982-11-30 1985-01-01 Rca Corporation Multiprocessor-memory data transfer network
US4698746A (en) * 1983-05-25 1987-10-06 Ramtek Corporation Multiprocessor communication method and apparatus
US4695951A (en) * 1983-07-07 1987-09-22 Honeywell Bull Inc. Computer hierarchy control
US4858111A (en) * 1983-07-29 1989-08-15 Hewlett-Packard Company Write-back cache system using concurrent address transfers to setup requested address in main memory before dirty miss signal from cache
US4875154A (en) * 1983-10-13 1989-10-17 Mitchell Maurice E Microcomputer with disconnected, open, independent, bimemory architecture, allowing large interacting, interconnected multi-microcomputer parallel systems accomodating multiple levels of programmer defined heirarchy
JPS60138653A (ja) * 1983-12-27 1985-07-23 Hitachi Ltd 階層記憶制御方式
US4905145A (en) * 1984-05-17 1990-02-27 Texas Instruments Incorporated Multiprocessor
JPS60258671A (ja) * 1984-06-05 1985-12-20 Nec Corp プロセツサ
JPS6170654A (ja) * 1984-09-14 1986-04-11 Hitachi Ltd 分散処理システムにおける資源管理方式
US4713755A (en) * 1985-06-28 1987-12-15 Hewlett-Packard Company Cache memory consistency control with explicit software instructions
JPS6279797U (de) * 1985-11-08 1987-05-21
US4800488A (en) * 1985-11-12 1989-01-24 American Telephone And Telegraph Company, At&T Bell Laboratories Method of propagating resource information in a computer network
JPH059965Y2 (de) * 1986-03-03 1993-03-11
US4768148A (en) * 1986-06-27 1988-08-30 Honeywell Bull Inc. Read in process memory apparatus
US5220657A (en) * 1987-12-02 1993-06-15 Xerox Corporation Updating local copy of shared data in a collaborative system
US5008853A (en) * 1987-12-02 1991-04-16 Xerox Corporation Representation of collaborative multi-user activities relative to shared structured data objects in a networked workstation environment
US5317716A (en) * 1988-08-16 1994-05-31 International Business Machines Corporation Multiple caches using state information indicating if cache line was previously modified and type of access rights granted to assign access rights to cache line
US5029070A (en) * 1988-08-25 1991-07-02 Edge Computer Corporation Coherent cache structures and methods
US4928225A (en) * 1988-08-25 1990-05-22 Edgcore Technology, Inc. Coherent cache structures and methods
US5276806A (en) * 1988-09-19 1994-01-04 Princeton University Oblivious memory computer networking
US5247659A (en) * 1988-10-06 1993-09-21 International Computers Limited Method for bootstrap loading in a data processing system comprising searching a plurality of program source devices for a bootstrap program if initial data indicating a bootstrap program source device fails a validity check
US5187793A (en) * 1989-01-09 1993-02-16 Intel Corporation Processor with hierarchal memory and using meta-instructions for software control of loading, unloading and execution of machine instructions stored in the cache
US5161219A (en) * 1989-01-13 1992-11-03 International Business Machines Corporation Computer system with input/output cache
US5371874A (en) * 1989-01-27 1994-12-06 Digital Equipment Corporation Write-read/write-pass memory subsystem cycle
US5185875A (en) * 1989-01-27 1993-02-09 Digital Equipment Corporation Method and apparatus for reducing memory read latency in a shared memory system with multiple processors
US5210848A (en) * 1989-02-22 1993-05-11 International Business Machines Corporation Multi-processor caches with large granularity exclusivity locking
WO1991006910A1 (en) * 1989-10-17 1991-05-16 Mitchell Maurice E A microcomputer with disconnected, open, independent, bimemory architecture
US5206941A (en) * 1990-01-22 1993-04-27 International Business Machines Corporation Fast store-through cache memory
US5297269A (en) * 1990-04-26 1994-03-22 Digital Equipment Company Cache coherency protocol for multi processor computer system
US5263144A (en) * 1990-06-29 1993-11-16 Digital Equipment Corporation Method and apparatus for sharing data between processors in a computer system
US5544347A (en) 1990-09-24 1996-08-06 Emc Corporation Data storage system controlled remote data mirroring with respectively maintained data indices
US5953510A (en) * 1991-09-05 1999-09-14 International Business Machines Corporation Bidirectional data bus reservation priority controls having token logic
US5530835A (en) * 1991-09-18 1996-06-25 Ncr Corporation Computer memory data merging technique for computers with write-back caches
US5361345A (en) * 1991-09-19 1994-11-01 Hewlett-Packard Company Critical line first paging system
US5727164A (en) * 1991-12-13 1998-03-10 Max Software, Inc. Apparatus for and method of managing the availability of items
EP0630499A4 (de) * 1992-03-09 1996-07-24 Auspex Systems Inc Beschleunigungssystem mit nichtflüchtigem, geschütztem, schreibbarem ram-cachespeicher.
JP2568017B2 (ja) * 1992-03-12 1996-12-25 株式会社東芝 マイクロプロセッサ及びそれを使用したデータ処理システム
US5319766A (en) * 1992-04-24 1994-06-07 Digital Equipment Corporation Duplicate tag store for a processor having primary and backup cache memories in a multiprocessor computer system
US5689679A (en) * 1993-04-28 1997-11-18 Digital Equipment Corporation Memory system and method for selective multi-level caching using a cache level code
US5504874A (en) * 1993-09-29 1996-04-02 Silicon Graphics, Inc. System and method of implementing read resources to maintain cache coherency in a multiprocessor environment permitting split transactions
US5581704A (en) * 1993-12-06 1996-12-03 Panasonic Technologies, Inc. System for maintaining data coherency in cache memory by periodically broadcasting invalidation reports from server to client
US5649152A (en) * 1994-10-13 1997-07-15 Vinca Corporation Method and system for providing a static snapshot of data stored on a mass storage system
US5835953A (en) * 1994-10-13 1998-11-10 Vinca Corporation Backup system that takes a snapshot of the locations in a mass storage device that has been identified for updating prior to updating
US5649157A (en) * 1995-03-30 1997-07-15 Hewlett-Packard Co. Memory controller with priority queues
US5680640A (en) 1995-09-01 1997-10-21 Emc Corporation System for migrating data by selecting a first or second transfer means based on the status of a data element map initialized to a predetermined state
US5870625A (en) * 1995-12-11 1999-02-09 Industrial Technology Research Institute Non-blocking memory write/read mechanism by combining two pending commands write and read in buffer and executing the combined command in advance of other pending command
US6601147B1 (en) * 1999-03-31 2003-07-29 International Business Machines Corporation Computer system and method for maintaining an integrated shared buffer memory in a group of interconnected hosts
US6728823B1 (en) * 2000-02-18 2004-04-27 Hewlett-Packard Development Company, L.P. Cache connection with bypassing feature
JP4704659B2 (ja) 2002-04-26 2011-06-15 株式会社日立製作所 記憶装置システムの制御方法および記憶制御装置
JP2004110367A (ja) 2002-09-18 2004-04-08 Hitachi Ltd 記憶装置システムの制御方法、記憶制御装置、および記憶装置システム
US7263593B2 (en) 2002-11-25 2007-08-28 Hitachi, Ltd. Virtualization controller and data transfer control method
JP2004220450A (ja) 2003-01-16 2004-08-05 Hitachi Ltd ストレージ装置、その導入方法、及びその導入プログラム
JP2005018193A (ja) 2003-06-24 2005-01-20 Hitachi Ltd ディスク装置のインタフェースコマンド制御方法ならびに計算機システム
JP4386694B2 (ja) 2003-09-16 2009-12-16 株式会社日立製作所 記憶システム及び記憶制御装置
JP4598387B2 (ja) * 2003-09-17 2010-12-15 株式会社日立製作所 記憶システム
US7219201B2 (en) 2003-09-17 2007-05-15 Hitachi, Ltd. Remote storage disk control device and method for controlling the same
JP4307202B2 (ja) 2003-09-29 2009-08-05 株式会社日立製作所 記憶システム及び記憶制御装置
JP4307964B2 (ja) 2003-11-26 2009-08-05 株式会社日立製作所 アクセス制限情報設定方法および装置
JP2005202893A (ja) 2004-01-19 2005-07-28 Hitachi Ltd 記憶デバイス制御装置、ストレージシステム、プログラムを記録した記録媒体、情報処理装置、及びストレージシステムの制御方法
JP4391265B2 (ja) 2004-02-26 2009-12-24 株式会社日立製作所 ストレージサブシステムおよび性能チューニング方法
JP4646574B2 (ja) * 2004-08-30 2011-03-09 株式会社日立製作所 データ処理システム
JP2006127028A (ja) 2004-10-27 2006-05-18 Hitachi Ltd 記憶システム及び記憶制御装置
JP2006134049A (ja) * 2004-11-05 2006-05-25 Hitachi Ltd ホスト装置が接続される制御装置の接続部とその制御装置が備える記憶デバイスとの間の論理パスを生成する装置及び方法
US8621154B1 (en) 2008-04-18 2013-12-31 Netapp, Inc. Flow based reply cache
US8161236B1 (en) 2008-04-23 2012-04-17 Netapp, Inc. Persistent reply cache integrated with file system
US8171227B1 (en) 2009-03-11 2012-05-01 Netapp, Inc. System and method for managing a flow based reply cache

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4860379A (en) * 1979-05-18 1989-08-22 General Instrument Corporation Data communications system

Also Published As

Publication number Publication date
DE2226382A1 (de) 1973-03-15
FR2155203A5 (de) 1973-05-18
DE2226382C3 (de) 1980-08-28
SE426110B (sv) 1982-12-06
JPS4838036A (de) 1973-06-05
GB1387043A (en) 1975-03-12
IT953791B (it) 1973-08-10
US3771137A (en) 1973-11-06
JPS5149535B2 (de) 1976-12-27
DE2226382B2 (de) 1979-12-13

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