CA2420027C - Systeme et procede de vcd sur demande - Google Patents

Systeme et procede de vcd sur demande Download PDF

Info

Publication number
CA2420027C
CA2420027C CA2420027A CA2420027A CA2420027C CA 2420027 C CA2420027 C CA 2420027C CA 2420027 A CA2420027 A CA 2420027A CA 2420027 A CA2420027 A CA 2420027A CA 2420027 C CA2420027 C CA 2420027C
Authority
CA
Canada
Prior art keywords
simulation
hardware
logic
user
software
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CA2420027A
Other languages
English (en)
Other versions
CA2420027A1 (fr
Inventor
Ping-Sheng Tseng
Yogesh Kumar Goel
Quincy Kun-Hsu Shen
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Verisity Design Inc
Original Assignee
Verisity Design Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Verisity Design Inc filed Critical Verisity Design Inc
Publication of CA2420027A1 publication Critical patent/CA2420027A1/fr
Application granted granted Critical
Publication of CA2420027C publication Critical patent/CA2420027C/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Debugging And Monitoring (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

L'invention se rapporte à une technique appelée VCD sur demande. Dans un système type, l'outil EDA intégrant la technique VCD sur demande possède les attributs de haut niveau suivants : (1) compression et enregistrement de l'historique de la simulation parallèle de type RCC ; (2) décompression de l'historique de la simulation parallèle de type RCC, et génération de fichiers VCD ; et (3) régénération de logiciels sur demande pour une plage cible de simulation sélectionnée, et révision de la conception sans réexécution de la simulation. Chacun de ces attributs seront décrits plus en détail. Lorsque l'utilisateur sélectionne une plage de simulation (105), le système RCC enregistre une version hautement compressée des entrées primaires issues du processus d'évaluation des performances. L'utilisateur sélectionne ensuite une zone plus réduite, appelée la plage cible de simulation (135), dans la plage de session de simulation, en vue d'une analyse plus concentrée. Le système RCC vide les informations d'état de matériel (autrement dit, les entrées primaires) du modèle de matériel dans un fichier VCD. Le système RCC permet ensuite à l'utilisateur de visualiser directement le fichier VCD à partir du début de la plage cible de simulation (105), sans devoir réexécuter la simulation entière à partir du tout début de la plage de session de simulation.
CA2420027A 2001-08-14 2001-08-14 Systeme et procede de vcd sur demande Expired - Fee Related CA2420027C (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2001/025558 WO2003017099A1 (fr) 2001-08-14 2001-08-14 Systeme et procede de vcd sur demande

Publications (2)

Publication Number Publication Date
CA2420027A1 CA2420027A1 (fr) 2003-02-27
CA2420027C true CA2420027C (fr) 2012-01-03

Family

ID=21742775

Family Applications (1)

Application Number Title Priority Date Filing Date
CA2420027A Expired - Fee Related CA2420027C (fr) 2001-08-14 2001-08-14 Systeme et procede de vcd sur demande

Country Status (7)

Country Link
EP (1) EP1417577A4 (fr)
JP (1) JP4102752B2 (fr)
KR (1) KR100928134B1 (fr)
CN (1) CN1308819C (fr)
CA (1) CA2420027C (fr)
IL (3) IL154481A0 (fr)
WO (1) WO2003017099A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005093575A1 (fr) * 2004-03-09 2005-10-06 Seiyang Yang Appareil de verification dynamique permettant d'obtenir une performance et une efficacite de verification elevees et procede de verification associe
JP2007305137A (ja) * 2006-05-12 2007-11-22 Samsung Electronics Co Ltd 分配された同時的シミュレーション
WO2014038030A1 (fr) * 2012-09-06 2014-03-13 株式会社日立製作所 Système informatique de co-simulation, système de vérification pour systèmes embarqués, et procédé de vérification pour systèmes embarqués
US9208008B2 (en) 2013-07-24 2015-12-08 Qualcomm Incorporated Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience
KR101660580B1 (ko) 2014-04-02 2016-09-28 프레스티지 바이오파마 피티이. 엘티디. 항체의 당 함량 조절을 통한 항체의 제조 방법
CN109426518B (zh) * 2017-08-29 2021-02-19 杭州旗捷科技有限公司 单核处理器设备的并行写码方法、电子设备、存储介质
CN109710536B (zh) * 2018-12-29 2022-03-18 湖北航天技术研究院总体设计所 一种自动提取fpga软件验证结果仿真波形的系统及方法
CN109740250B (zh) * 2018-12-29 2022-03-18 湖北航天技术研究院总体设计所 基于uvm的fpga软件验证结果仿真波形的获取方法和系统
CN111125975B (zh) * 2019-12-09 2024-06-14 上海思尔芯技术股份有限公司 一种fpga时分复用多路数据传输的方法、存储介质及终端
CN112486076B (zh) * 2020-12-08 2022-02-15 长光卫星技术有限公司 一种多fpga间时钟同步与复位同步系统
CN113342697B (zh) * 2021-07-19 2022-08-26 英韧科技(上海)有限公司 闪存转换层仿真测试系统及方法
US20240070345A1 (en) * 2022-08-30 2024-02-29 Rockwell Automation Technologies, Inc. Parallel emulation for controls testing

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
JP3506202B2 (ja) * 1997-06-30 2004-03-15 住友電装株式会社 基板用コネクタ
US6083269A (en) 1997-08-19 2000-07-04 Lsi Logic Corporation Digital integrated circuit design system and methodology with hardware
US6249891B1 (en) * 1998-07-02 2001-06-19 Advantest Corp. High speed test pattern evaluation apparatus
US6061283A (en) * 1998-10-23 2000-05-09 Advantest Corp. Semiconductor integrated circuit evaluation system
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation

Also Published As

Publication number Publication date
CN1308819C (zh) 2007-04-04
CN1491385A (zh) 2004-04-21
KR20040028598A (ko) 2004-04-03
JP4102752B2 (ja) 2008-06-18
JP2005500618A (ja) 2005-01-06
IL160392A0 (en) 2004-07-25
KR100928134B1 (ko) 2009-11-25
IL154481A0 (en) 2003-09-17
CA2420027A1 (fr) 2003-02-27
EP1417577A4 (fr) 2009-08-26
IL154481A (en) 2008-03-20
WO2003017099A1 (fr) 2003-02-27
EP1417577A1 (fr) 2004-05-12

Similar Documents

Publication Publication Date Title
US7480606B2 (en) VCD-on-demand system and method
US6321366B1 (en) Timing-insensitive glitch-free logic system and method
US7512728B2 (en) Inter-chip communication system
US6651225B1 (en) Dynamic evaluation logic system and method
US6785873B1 (en) Emulation system with multiple asynchronous clocks
US6389379B1 (en) Converification system and method
US9195784B2 (en) Common shared memory in a verification system
US6810442B1 (en) Memory mapping system and method
US6754763B2 (en) Multi-board connection system for use in electronic design automation
JP4125675B2 (ja) タイミングに鈍感なグリッチのない論理システムおよび方法
US6026230A (en) Memory simulation system and method
US6134516A (en) Simulation server system and method
US6421251B1 (en) Array board interconnect system and method
US6009256A (en) Simulation/emulation system and method
JP4456420B2 (ja) ネットワークベースの階層エミュレーションシステム
US7366652B2 (en) Method of programming a co-verification system
KR19980032933A (ko) 에뮬레이션 및 시뮬레이션을 이용한 설계 검증 방법 및 장치
CA2420027C (fr) Systeme et procede de vcd sur demande
Shabany et al. ECE1373 VLSI Systems Design project report MonteCarlo-based Channel Estimator (MCCE)

Legal Events

Date Code Title Description
EEER Examination request
MKLA Lapsed

Effective date: 20140814