CN1308819C - 改值转储随选系统与方法 - Google Patents

改值转储随选系统与方法 Download PDF

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Publication number
CN1308819C
CN1308819C CNB018227910A CN01822791A CN1308819C CN 1308819 C CN1308819 C CN 1308819C CN B018227910 A CNB018227910 A CN B018227910A CN 01822791 A CN01822791 A CN 01822791A CN 1308819 C CN1308819 C CN 1308819C
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CN
China
Prior art keywords
simulation
hardware
logic
simulated
clock
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
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CNB018227910A
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English (en)
Chinese (zh)
Other versions
CN1491385A (zh
Inventor
曾平圣
约格西·库马·戈尔
沈崑旭
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Cadence Design Systems Inc
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Verisity Design Inc
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Publication date
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Publication of CN1491385A publication Critical patent/CN1491385A/zh
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Publication of CN1308819C publication Critical patent/CN1308819C/zh
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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/44—Arrangements for executing specific programs
    • G06F9/455—Emulation; Interpretation; Software simulation, e.g. virtualisation or emulation of application or operating system execution engines
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/33—Design verification, e.g. functional simulation or model checking

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  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Software Systems (AREA)
  • Computer Hardware Design (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Evolutionary Computation (AREA)
  • Geometry (AREA)
  • Debugging And Monitoring (AREA)
  • Management, Administration, Business Operations System, And Electronic Commerce (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)
CNB018227910A 2001-08-14 2001-08-14 改值转储随选系统与方法 Expired - Fee Related CN1308819C (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2001/025558 WO2003017099A1 (fr) 2001-08-14 2001-08-14 Systeme et procede de vcd sur demande

Publications (2)

Publication Number Publication Date
CN1491385A CN1491385A (zh) 2004-04-21
CN1308819C true CN1308819C (zh) 2007-04-04

Family

ID=21742775

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB018227910A Expired - Fee Related CN1308819C (zh) 2001-08-14 2001-08-14 改值转储随选系统与方法

Country Status (7)

Country Link
EP (1) EP1417577A4 (fr)
JP (1) JP4102752B2 (fr)
KR (1) KR100928134B1 (fr)
CN (1) CN1308819C (fr)
CA (1) CA2420027C (fr)
IL (3) IL154481A0 (fr)
WO (1) WO2003017099A1 (fr)

Families Citing this family (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2007528553A (ja) * 2004-03-09 2007-10-11 セヤン ヤン 検証性能と検証效率性を高める動的検証−基盤方式の検証装置及びこれを用いた検証方法論
JP2007305137A (ja) * 2006-05-12 2007-11-22 Samsung Electronics Co Ltd 分配された同時的シミュレーション
WO2014038030A1 (fr) * 2012-09-06 2014-03-13 株式会社日立製作所 Système informatique de co-simulation, système de vérification pour systèmes embarqués, et procédé de vérification pour systèmes embarqués
US9208008B2 (en) 2013-07-24 2015-12-08 Qualcomm Incorporated Method and apparatus for multi-chip reduced pin cross triggering to enhance debug experience
KR101660580B1 (ko) 2014-04-02 2016-09-28 프레스티지 바이오파마 피티이. 엘티디. 항체의 당 함량 조절을 통한 항체의 제조 방법
CN109426518B (zh) * 2017-08-29 2021-02-19 杭州旗捷科技有限公司 单核处理器设备的并行写码方法、电子设备、存储介质
CN109740250B (zh) * 2018-12-29 2022-03-18 湖北航天技术研究院总体设计所 基于uvm的fpga软件验证结果仿真波形的获取方法和系统
CN109710536B (zh) * 2018-12-29 2022-03-18 湖北航天技术研究院总体设计所 一种自动提取fpga软件验证结果仿真波形的系统及方法
CN111125975B (zh) * 2019-12-09 2024-06-14 上海思尔芯技术股份有限公司 一种fpga时分复用多路数据传输的方法、存储介质及终端
CN112486076B (zh) * 2020-12-08 2022-02-15 长光卫星技术有限公司 一种多fpga间时钟同步与复位同步系统
CN113342697B (zh) * 2021-07-19 2022-08-26 英韧科技(上海)有限公司 闪存转换层仿真测试系统及方法
US20240070345A1 (en) * 2022-08-30 2024-02-29 Rockwell Automation Technologies, Inc. Parallel emulation for controls testing

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6083269A (en) * 1997-08-19 2000-07-04 Lsi Logic Corporation Digital integrated circuit design system and methodology with hardware
US6161283A (en) * 1997-06-30 2000-12-19 Sumitomo Wiring Systems, Ldt. Connector for circuit board and method for producing a connector
US6249891B1 (en) * 1998-07-02 2001-06-19 Advantest Corp. High speed test pattern evaluation apparatus

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6009256A (en) * 1997-05-02 1999-12-28 Axis Systems, Inc. Simulation/emulation system and method
US6061283A (en) * 1998-10-23 2000-05-09 Advantest Corp. Semiconductor integrated circuit evaluation system
US6678645B1 (en) * 1999-10-28 2004-01-13 Advantest Corp. Method and apparatus for SoC design validation

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6161283A (en) * 1997-06-30 2000-12-19 Sumitomo Wiring Systems, Ldt. Connector for circuit board and method for producing a connector
US6083269A (en) * 1997-08-19 2000-07-04 Lsi Logic Corporation Digital integrated circuit design system and methodology with hardware
US6249891B1 (en) * 1998-07-02 2001-06-19 Advantest Corp. High speed test pattern evaluation apparatus

Also Published As

Publication number Publication date
EP1417577A1 (fr) 2004-05-12
JP4102752B2 (ja) 2008-06-18
KR20040028598A (ko) 2004-04-03
CA2420027A1 (fr) 2003-02-27
IL154481A (en) 2008-03-20
WO2003017099A1 (fr) 2003-02-27
KR100928134B1 (ko) 2009-11-25
IL160392A0 (en) 2004-07-25
JP2005500618A (ja) 2005-01-06
CN1491385A (zh) 2004-04-21
IL154481A0 (en) 2003-09-17
CA2420027C (fr) 2012-01-03
EP1417577A4 (fr) 2009-08-26

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Patentee before: Verisity Design Inc.

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Granted publication date: 20070404

Termination date: 20140814

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